JP2001291826A - Semiconductor integrated device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated device which can ensure a capacitance value necessary for normal operation of a dynamic shift register when an element is micronized, in a semiconductor integrated device having a dynamic shift register. SOLUTION: This integrated device is provided with a semiconductor substrate, a plurality of transistor cells which are formed in a prescribed region of the substrate and contain a first conducting layer having parts turning to plural gate electrodes and plural impurity diffusion regions turning to sources or drains, and a second conducting layer which is connected selectively with the first conducting layer or the plural impurity diffusion regions. A part of the plurality of transistor cells constitute a clocked inverter which inverts and outputs input data on the basis of a clock signal. A gate electrode of at least one transistor cell to which the input data are supplied is connected with a gate electrode of at least one transistor cell which does not constitute a clocked inverter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated device, and more particularly, to a semiconductor integrated device having a dynamic shift register.

[0002]

2. Description of the Related Art FIG. 5 shows an equivalent circuit of a general dynamic shift register included in a semiconductor integrated device. FIG.
, The dynamic shift register is composed of two stages of clocked inverters. The first-stage clocked inverter includes two P-channel transistors Tr1 and Tr2 connected in series, and two P-channel transistors Tr1 and Tr2 connected in series.
It includes two N-channel transistors Tr3 and Tr4 and performs a complementary operation. Transistor Tr1
The data D is input to the gates of the transistors Tr4 and Tr4, where a parasitic capacitance C1 exists. The clock signal C is input to the gate of the transistor Tr2,
The inverted clock signal XC is input to the gate of r3.

The second stage clocked inverter is the same as the first stage except that the connection between the clock signal C and the inverted clock signal XC is reversed. Note that these clocked inverters are connected to the power supply voltage V on the high potential side.
The operation is performed by supplying DD and the low-potential-side power supply voltage VSS. In FIG. 5, the ground potential is used as the low-potential-side power supply voltage VSS.

FIG. 6 is a diagram showing the relationship between the waveforms of the clock signal C and the inverted clock signal XC and the operation of the dynamic shift register shown in FIG. Inverted clock signal X
When C is at a high level and the clock signal C is at a low level, the clocked inverter in the first stage becomes active. When the inverted clock signal XC is at a low level and the clock signal C is at a high level, the second stage is driven. The clocked inverter becomes active. Thus, the first
Data D input to the clocked inverter of the stage
Is output from the first-stage clocked inverter together with the change in the clock signal C and the inverted clock signal XC, and is further output along with the next change in the clock signal C and the inverted clock signal XC. The output data Q is obtained by being inverted and output from the inverter. Here, the parasitic capacitances C1 and C2 are
When the clocked inverter is in the non-active state, it plays an essential role of temporarily holding the data value at the output of the clocked inverter.

FIG. 7 is a plan view showing wiring of a dynamic shift register included in a conventional semiconductor integrated device. On a silicon substrate, a polysilicon layer (portion surrounded by a solid line) to be a gate electrode and a wiring layer is formed via a gate insulating film. In the silicon substrate on both sides of the gate electrode, impurity diffusion regions (regions surrounded by broken lines) serving as sources and drains are formed. A metal wiring layer (shaded portion) is formed thereon via an interlayer insulating film. An opening is provided in a part of the interlayer insulating film for wiring connection between the layers, and a contact cell (a black portion) is formed.

In FIG. 7, a metal wiring for supplying a power supply voltage VDD on the high potential side and a power supply voltage VSS on the low potential side is provided in parallel in the horizontal direction in which the source, gate and drain of each transistor are arranged. On the other hand, the polysilicon wiring for supplying the clock signal C and the inverted clock signal XC is provided in the vertical direction.

Here, since the output of the first-stage clocked inverter is connected to the input of the second-stage clocked inverter, the drain capacitances of the first-stage transistors Tr2 and Tr3, First-stage output wiring interlayer capacitance or inter-wiring capacitance, second-stage transistors Tr5 and T
The gate capacitance of r8 and the like constitute the parasitic capacitance C2.

[0008]

In the semiconductor integrated device as described above, the dynamic shift register is generally composed of standard cells for high integration.
However, as the size of the standard cell is reduced with the conventional cell structure as the elements become finer in the manufacturing process of the semiconductor integrated device, the reduction of each capacitance component constituting the parasitic capacitance, in particular, the interlayer capacitance due to the reduction of the area of the output wiring. As a result, the normal operation of the dynamic shift register may be impaired by the influence of noise or the like due to a decrease in the value of the parasitic capacitance.

In view of the above, an object of the present invention is to provide a semiconductor integrated device having a dynamic shift register which can secure a capacitance value necessary for normal operation of the dynamic shift register even if the elements are miniaturized. An object of the present invention is to provide a semiconductor integrated device.

[0010]

In order to solve the above problems, a semiconductor integrated device according to the present invention comprises a semiconductor substrate and a plurality of transistor cells formed in a predetermined region of the semiconductor substrate. A first conductive layer having a plurality of gate electrodes that are regularly formed thereon via an insulating film, and a plurality of regularly formed source or drain formed in the semiconductor substrate on both sides of the plurality of gate electrodes A plurality of transistor cells including an impurity diffusion region; and a second transistor selectively connected to the plurality of impurity diffusion regions or the first conductive layer.
Part of the plurality of transistor cells constitutes a clocked inverter that inverts and outputs input data based on a clock signal, and at least one of the transistor cells to which input data is supplied is provided. The gate electrode is connected to the gate electrode of at least one transistor cell that does not form a clocked inverter.

Here, the gate electrode of at least one transistor cell to which input data is supplied may be connected to the gate electrode of at least one transistor cell that does not form a clocked inverter in the first conductive layer. . Alternatively, a gate electrode of at least one transistor cell to which input data is supplied may be connected to a gate electrode of at least one transistor cell not forming a clocked inverter via a second conductive layer.

Further, 8N transistor cells are provided in a predetermined region of the semiconductor substrate (N is a natural number), and 4N of the 8N transistor cells are N complementary clocked transistors. Each of the gate electrodes of the 2N transistor cells forming the inverter and supplied with the input data may be connected to the gate electrode of at least one transistor cell not forming the clocked inverter.

Further, two adjacent transistor cells may share one impurity diffusion region as a source or a drain.

[0014] The semiconductor device may further include a third conductive layer selectively connected to the second conductive layer. Here, the semiconductor substrate may be formed of silicon, the first conductive layer may be formed of polysilicon containing impurities, and the second and third conductive layers may be formed of aluminum.

According to the semiconductor integrated device of the present invention configured as described above, it is possible to secure a capacitance value required for normal operation of the dynamic shift register even if the elements are miniaturized.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same elements are denoted by the same reference numerals and description thereof is omitted.

The equivalent circuit of the dynamic shift register included in the semiconductor integrated device according to one embodiment of the present invention is the same as that shown in FIG. 5, but the values of the parasitic capacitances C1 and C2 are smaller than those of the standard cells. The feature is that it is possible to take large.

FIG. 1 is a plan view showing wiring of a dynamic shift register included in a semiconductor integrated device according to one embodiment of the present invention. On a semiconductor substrate 1 such as silicon,
A first conductive layer 3 such as polysilicon (including impurities) serving as a gate electrode and a wiring layer is formed via the first insulating film. In the semiconductor substrate 1 on both sides of the gate electrode, an impurity diffusion region 2 serving as a source / drain is formed. Thereon, a second conductive layer 4 of aluminum or the like serving as a wiring layer is formed via a second insulating film. Second conductive layer 4
An opening is provided in a part of the second insulating film for connection between the first conductive layer 3 or the impurity diffusion region 2, and a contact cell 5 (a small black portion) is formed. Is done. Further thereon, a third conductive layer 6 of aluminum or the like to be a wiring layer is formed via a third insulating film. For the connection between the third conductive layer 6 and the second conductive layer 4, an opening is provided in a part of the third insulating film, and a via cell 7 (a large black portion) is formed. You.

In the present embodiment, since the second conductive layer 4 and the third conductive layer 6 are formed of aluminum, they may be hereinafter referred to as aluminum wiring. Aluminum wiring for supplying the high-potential-side power supply voltage VDD and the low-potential-side power supply voltage VSS is provided in parallel with the vertical direction in which the source, gate, and drain of each transistor are arranged. Aluminum wiring for supplying the signal C and the inverted clock signal XC is also provided in parallel.

Generally, in the design of a semiconductor integrated device, each transistor cell and aluminum wiring are arranged such that the horizontal and vertical wiring grids shown in FIG. 1 coincide with the center line of the aluminum wiring. . The dynamic shift register shown in FIG. 1 is composed of two stages of clocked inverters as shown in FIG. 5, and includes eight transistors Tr1 to Tr8. Note that the number of clocked inverters included in the dynamic shift register is not limited to two, and may include N clocked inverters (N is a natural number). In this case, for example, 4N transistor cells out of 8N transistor cells formed in a predetermined region constitute an N-stage complementary clocked inverter.

In the present invention, the transistors Tr1 and Tr4 to which data is input and the transistor Tr5
And each gate of Tr8 is laid out so as to be connected to the gate of an unused transistor cell.
The values of the input capacitances C1 and C2 of the inverter are increased.

Next, the present embodiment will be described in detail along the manufacturing process of the semiconductor integrated device with reference to FIGS.

First, as shown in FIG. 2, a first conductive layer 3 of polysilicon or the like to be a gate electrode and a wiring layer is formed on a semiconductor substrate 1 of silicon or the like via a first insulating film. . In the semiconductor substrate 1 on both sides of the gate electrode, an impurity diffusion region 2 serving as a source / drain is formed. In the region shown in FIG. 2, four N-type impurity diffusion regions, four P-type impurity diffusion regions, and 16 gate electrodes
They are regularly arranged so that two transistor cells are formed in one impurity diffusion region. Note that two horizontally adjacent gate electrodes are integrally formed.

Of these 16 transistor cells, 8
One transistor cell is used as the transistors Tr1 to Tr8 forming the dynamic shift register, and the other eight transistor cells are unused. Here, the transistors Tr1, Tr4 to which data is input,
Since the gate electrodes of Tr5 and Tr8 are respectively connected to the gate electrodes (hatched portions) of unused transistors laterally adjacent to these transistors, the parasitic capacitance of the gate electrodes of unused transistors causes 5
Can increase the values of the input capacitors C1 and C2 of the clocked inverters at each stage. Thereby, it is easy to ensure the normal operation of the dynamic shift register.

According to the present embodiment, the input capacitances C1 and C2 of the clocked inverter can be increased without changing the aluminum wiring layer, so that there is a great advantage that the pattern design is not complicated. On the other hand, when it is permitted to change the aluminum wiring layer, for example, by connecting the gate electrode of the transistor Tr1 to the gate electrode of an unused transistor vertically adjacent (upper side) to this, the clock is increased. The value of the input capacitance C1 of the inverter can be further increased.

FIGS. 3 and 4 show two aluminum wiring layers. First, after forming the second insulating film, the second conductive layer 4 shown in FIG. 3 is formed. In the contact cell 5, the second conductive layer 4 is connected to the first conductive layer 3 or the impurity diffusion region 2 through an opening provided in the second insulating film. Next, after forming a third insulating film, a third conductive layer 6 shown in FIG. 4 is formed. In Viacell 7,
Third conductive layer 6 is connected to second conductive layer 4 through an opening provided in a part of the third insulating film.

Through the above steps, the basic structure of the semiconductor integrated device according to the present embodiment is completed.

[0028]

As described above, according to the present invention, it is possible to secure a capacitance value required for normal operation of the dynamic shift register even if the elements are miniaturized.

[Brief description of the drawings]

FIG. 1 is a plan view showing wiring of a dynamic shift register included in a semiconductor integrated device according to an embodiment of the present invention.

FIG. 2 is a plan view showing an impurity diffusion region 2 and a first conductive layer 3 in the semiconductor integrated device shown in FIG.

FIG. 3 is a plan view showing a second conductive layer 4 in the semiconductor integrated device shown in FIG.

FIG. 4 is a plan view showing a third conductive layer 6 in the semiconductor integrated device shown in FIG.

FIG. 5 is a circuit diagram showing an equivalent circuit of a general dynamic shift register included in the semiconductor integrated device.

6 is a diagram showing waveforms of a clock signal C and an inverted clock signal XC used in the dynamic shift register shown in FIG.

FIG. 7 is a plan view showing wiring of a dynamic shift register included in a conventional semiconductor integrated device.

[Description of Signs] 1 Semiconductor substrate 2 Impurity diffusion region 3 First conductive layer 4 Second conductive layer 5 Contact hole 6 Third conductive layer 7 Via hole Tr1 to Tr8 Transistors C1, C2 Parasitic capacitance VDD High potential side Power supply voltage VSS Low-side power supply voltage

Claims (7)

[Claims] 1. A semiconductor substrate, and a plurality of transistor cells formed in a predetermined region of the semiconductor substrate, the portions being regularly formed on the semiconductor substrate via an insulating film to become a plurality of gate electrodes. A plurality of transistor cells including: a first conductive layer having: a plurality of impurity diffusion regions that are regularly formed in the semiconductor substrate on both sides of the plurality of gate electrodes and serve as a source or a drain; And a second conductive layer selectively connected to the plurality of impurity diffusion regions, wherein a part of the plurality of transistor cells inverts input data based on a clock signal and outputs the inverted data. And the gate electrode of at least one transistor cell to which the input data is supplied does not constitute a clocked inverter. The semiconductor integrated device, characterized in that connected to the gate electrode of the One of the transistor cell. 2. A gate electrode of at least one transistor cell to which the input data is supplied is provided with a clocked transistor.
2. The semiconductor integrated device according to claim 1, wherein a gate electrode of at least one transistor cell that does not form an inverter is connected in the first conductive layer. 3. The gate electrode of at least one transistor cell to which the input data is supplied is a clocked transistor.
2. The semiconductor integrated device according to claim 1, wherein a gate electrode of at least one transistor cell that does not constitute an inverter is connected via said second conductive layer. 4. The semiconductor device according to claim 1, wherein the predetermined area of the semiconductor substrate is 8N.
Transistor cells (N is a natural number),
Of the N transistor cells, 4N transistor cells constitute N complementary clocked inverters, and each of the gate electrodes of the 2N transistor cells to which the input data is supplied has a clocked inverter. 3. The semiconductor device according to claim 1, wherein said gate electrode is connected to a gate electrode of at least one transistor cell which does not form an inverter.
4. The semiconductor integrated device according to claim 3. 5. The semiconductor integrated device according to claim 1, wherein two adjacent transistor cells share one impurity diffusion region as a source or a drain. 6. The semiconductor integrated device according to claim 1, further comprising a third conductive layer selectively connected to said second conductive layer. 7. The semiconductor substrate is formed of silicon,
7. The semiconductor integrated device according to claim 6, wherein said first conductive layer is formed of polysilicon containing impurities, and said second and third conductive layers are formed of aluminum.