JP2001291803A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001291803A JP2001291803A JP2000102481A JP2000102481A JP2001291803A JP 2001291803 A JP2001291803 A JP 2001291803A JP 2000102481 A JP2000102481 A JP 2000102481A JP 2000102481 A JP2000102481 A JP 2000102481A JP 2001291803 A JP2001291803 A JP 2001291803A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- filler
- semiconductor
- semiconductor device
- active surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、半導体チップを
別の半導体チップや配線基板などの固体装置の表面にフ
ェースダウン状態で接合させた構造を有する半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure in which a semiconductor chip is joined face-down to a surface of a solid-state device such as another semiconductor chip or a wiring board.
【0002】[0002]
【従来の技術】従来から、半導体チップの表面に他の半
導体チップを重ね合わせて接合したチップ・オン・チッ
プ構造の半導体装置が知られている。このようなチップ
・オン・チップ構造の半導体装置では、図2に示すよう
に、一方の半導体チップ91は、いわゆるフェースダウ
ン方式で他方の半導体チップ92に接合されており、こ
の半導体チップ92との間に設けられた複数個のバンプ
93によって、所定間隔を保つように連結され、かつ、
互いに電気的に接続されている。そして、半導体チップ
91,92の対向する表面間は、エポキシ樹脂などの合
成樹脂94中にフィラー95を混入してなる充填材96
で封止されており、この半導体チップ91,92間を充
填材96で封止して得られる半導体モジュールは、さら
にモールド樹脂で封止されてパッケージ(図示せず)内
に収容されている。2. Description of the Related Art Conventionally, there has been known a semiconductor device having a chip-on-chip structure in which another semiconductor chip is superimposed on and joined to the surface of a semiconductor chip. In a semiconductor device having such a chip-on-chip structure, as shown in FIG. 2, one semiconductor chip 91 is joined to the other semiconductor chip 92 by a so-called face-down method. By a plurality of bumps 93 provided therebetween, they are connected so as to keep a predetermined interval, and
They are electrically connected to each other. A filler 96 formed by mixing a filler 95 into a synthetic resin 94 such as an epoxy resin is provided between the opposing surfaces of the semiconductor chips 91 and 92.
The semiconductor module obtained by sealing the space between the semiconductor chips 91 and 92 with the filler 96 is further sealed with a mold resin and accommodated in a package (not shown).
【0003】[0003]
【発明が解決しようとする課題】ところが、充填材96
中のフィラー95は吸湿性を有しており、このフィラー
95が湿気を吸収すると、合成樹脂94とフィラー95
との間の結合力が弱まるため、この半導体装置に熱膨張
などによる応力が生じた場合に、充填材96が破損する
おそれがあった。また、半導体チップ91,92の最表
面に形成されている表面保護膜が、充填材96中のフィ
ラー95で傷つけられることにより、半導体チップ9
1,92の性能の劣化を招くおそれがあった。However, the filler 96
The filler 95 in the inside has a hygroscopic property, and when the filler 95 absorbs moisture, the synthetic resin 94 and the filler 95
When the stress due to thermal expansion or the like is generated in the semiconductor device, the filler 96 may be damaged because the bonding force between the filler 96 and the semiconductor material is weakened. Further, the surface protection film formed on the outermost surfaces of the semiconductor chips 91 and 92 is damaged by the filler 95 in the filler 96, so that the semiconductor chips 9 and 92 are damaged.
However, there was a possibility that the performance of 1,92 would be deteriorated.
【0004】そこで、この発明の目的は、充填材の破損
およびチップ表面の損傷を防止することにより、品質の
向上が図られた半導体装置を提供することである。An object of the present invention is to provide a semiconductor device having improved quality by preventing damage to a filler and damage to a chip surface.
【0005】[0005]
【課題を解決するための手段および発明の効果】前記の
目的を達成するための請求項1記載の発明は、固体装置
の表面に、半導体チップをその活性表面を対向させたフ
ェースダウン状態で接合した構造を有する半導体装置で
あって、前記固体装置の表面と前記半導体チップの活性
表面との間が、ノンフィラー充填材で封止されているこ
とを特徴とする半導体装置である。According to the first aspect of the present invention, a semiconductor chip is bonded to a surface of a solid-state device in a face-down state in which an active surface thereof is opposed to the semiconductor chip. A semiconductor device having a structure described above, wherein a space between the surface of the solid-state device and the active surface of the semiconductor chip is sealed with a non-filler filler.
【0006】前記固体装置は、前記半導体チップとは別
の半導体チップであってもよいし、配線基板であっても
よい。この発明によれば、半導体チップの活性表面と固
体装置の表面との間がノンフィラー充填材で封止されて
いる。ノンフィラー充填材は、フィラーを含まない充填
材である。したがって、たとえ熱膨張などによる応力が
生じても、ノンフィラー充填材に亀裂などの破損を生じ
るおそれがないうえに、半導体チップの活性表面が傷つ
けられることによる性能劣化を招くおそれがないので、
半導体装置の品質を良好に保つことができる。[0006] The solid state device may be a semiconductor chip different from the semiconductor chip, or may be a wiring board. According to the present invention, the space between the active surface of the semiconductor chip and the surface of the solid-state device is sealed with the non-filler filler. The non-filler filler is a filler containing no filler. Therefore, even if stress due to thermal expansion or the like is generated, there is no possibility that the non-filler filler may be damaged such as a crack, and there is no possibility that the active surface of the semiconductor chip is deteriorated and performance is deteriorated.
Good quality of the semiconductor device can be maintained.
【0007】[0007]
【発明の実施の形態】以下では、この発明の実施の形態
を、添付図面を参照して詳細に説明する。図1は、この
発明の一実施形態に係る半導体装置の構成を示す図解的
な断面図である。この半導体装置は、親チップ1の活性
表面11に、子チップ2をその活性表面21を対向させ
たフェースダウン状態で接合したチップ・オン・チップ
構造を有しており、親チップ1と子チップ2とを接合し
た後、これらをパッケージ3内に納めることにより構成
されている。活性表面とは、半導体基板においてトラン
ジスタなどの素子が形成された活性表層領域側の表面を
指す。親チップ1および子チップ2は、いずれもシリコ
ンチップであってもよいが、化合物半導体(ガリウム砒
素やガリウム燐など)やゲルマニウム半導体などの他の
種類の半導体チップであってもよいし、親チップ1と子
チップ2との半導体の種類が一致している必要もない。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an illustrative sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. This semiconductor device has a chip-on-chip structure in which a child chip 2 is bonded to an active surface 11 of a parent chip 1 in a face-down state with its active surface 21 opposed. After joining them, they are housed in a package 3. The active surface refers to a surface on the active surface layer region side on which a device such as a transistor is formed on a semiconductor substrate. Each of the parent chip 1 and the child chip 2 may be a silicon chip, but may be another type of semiconductor chip such as a compound semiconductor (such as gallium arsenide or gallium phosphide) or a germanium semiconductor. It is not necessary that the types of semiconductors of the semiconductor chip 1 and the child chip 2 match.
【0008】親チップ1は、平面視における外形が子チ
ップ2よりも大きく形成されている。親チップ1の活性
表面11の内方の領域には、子チップ2の接合領域が設
定されており、その周囲には、複数個の外部接続用のパ
ッド(図示せず)が最表面に形成された表面保護膜から
露出した状態に配置されている。外部接続用パッドは、
ボンディングワイヤ4を介してリードフレーム5に接続
されている。子チップ2は、親チップ1の活性表面11
にフェースダウンで接合されており、互いに対向する活
性表面11,21間に設けられた複数個のバンプ6によ
って、所定間隔を保つように連結され、かつ、互いに電
気的に接続されている。そして、親チップ1の活性表面
11と子チップ2の活性表面21との間は、たとえば、
エポキシ樹脂などの合成樹脂を主材料とし、フィラーの
ような粒状物を含まないノンフィラー充填材7によって
封止されている。The parent chip 1 is formed to have a larger outer shape in plan view than the child chip 2. A bonding area of the child chip 2 is set in an area inside the active surface 11 of the parent chip 1, and a plurality of external connection pads (not shown) are formed on the outermost area around the bonding area. It is arranged so as to be exposed from the surface protective film thus formed. The external connection pad is
It is connected to a lead frame 5 via a bonding wire 4. The child chip 2 is the active surface 11 of the parent chip 1
Are connected face-down, and are connected at predetermined intervals by a plurality of bumps 6 provided between the active surfaces 11 and 21 facing each other, and are electrically connected to each other. Then, between the active surface 11 of the parent chip 1 and the active surface 21 of the child chip 2, for example,
The main material is a synthetic resin such as an epoxy resin, and is sealed by a non-filler filler 7 which does not contain a granular material such as a filler.
【0009】したがって、親チップおよび子チップ間を
フィラーが混入された充填材で封止した半導体装置とは
異なり、この半導体装置に熱膨張などによる応力が生じ
ても、ノンフィラー充填材7に亀裂などの破損を生じる
おそれがない。また、親チップ1の活性表面11および
子チップ2の活性表面21が傷つけられるおそれがな
く、親チップ1および子チップ2の性能劣化を招くおそ
れがない。ゆえに、この半導体装置の品質を良好に保つ
ことができる。Therefore, unlike a semiconductor device in which a space between a parent chip and a child chip is sealed with a filler mixed with a filler, even if stress is generated in the semiconductor device due to thermal expansion or the like, a crack is generated in the non-filler filler 7. There is no risk of damage such as damage. Further, there is no possibility that the active surface 11 of the parent chip 1 and the active surface 21 of the child chip 2 are damaged, and there is no possibility that the performance of the parent chip 1 and the child chip 2 is deteriorated. Therefore, good quality of the semiconductor device can be maintained.
【0010】以上、この発明の一実施形態について説明
したが、この発明は、他の形態で実施することもでき
る。たとえば、上述の実施形態では、チップ・オン・チ
ップ構造を取り上げたが、この発明は、半導体チップの
表面をリードフレームなどの配線基板に対向させて接合
するフリップ・チップ・ボンディング構造にも適用する
ことができる。その他、特許請求の範囲に記載された事
項の範囲で、種々の設計変更を施すことが可能である。Although the embodiment of the present invention has been described above, the present invention can be embodied in other forms. For example, in the above-described embodiment, the chip-on-chip structure has been described, but the present invention is also applied to a flip-chip bonding structure in which the surface of a semiconductor chip is bonded to a wiring board such as a lead frame so as to face the same. be able to. In addition, various design changes can be made within the scope of the matters described in the claims.
【図1】この発明の一実施形態に係る半導体装置の構成
を示す図解的な断面図である。FIG. 1 is an illustrative sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.
【図2】従来のチップ・オン・チップ構造の半導体装置
の構成を示す図解的な断面図である。FIG. 2 is an illustrative sectional view showing a configuration of a conventional semiconductor device having a chip-on-chip structure.
1 親チップ(固体装置) 11 活性表面(固体装置の表面) 2 子チップ(半導体チップ) 21 活性表面(半導体チップの活性表面) 3 パッケージ 4 ボンディングワイヤ 5 リードフレーム 6 バンプ 7 ノンフィラー充填材 Reference Signs List 1 parent chip (solid device) 11 active surface (surface of solid device) 2 child chip (semiconductor chip) 21 active surface (active surface of semiconductor chip) 3 package 4 bonding wire 5 lead frame 6 bump 7 non-filler filler
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 25/18 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 25/18
Claims (1)
性表面を対向させたフェースダウン状態で接合した構造
を有する半導体装置であって、 前記固体装置の表面と前記半導体チップの活性表面との
間が、ノンフィラー充填材で封止されていることを特徴
とする半導体装置。1. A semiconductor device having a structure in which a semiconductor chip is joined to a surface of a solid-state device in a face-down state with its active surface facing the semiconductor device, wherein the solid-state device and the active surface of the semiconductor chip are connected to each other. A semiconductor device, wherein the space is sealed with a non-filler filler.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000102481A JP4405033B2 (en) | 2000-04-04 | 2000-04-04 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000102481A JP4405033B2 (en) | 2000-04-04 | 2000-04-04 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001291803A true JP2001291803A (en) | 2001-10-19 |
JP4405033B2 JP4405033B2 (en) | 2010-01-27 |
Family
ID=18616354
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000102481A Expired - Fee Related JP4405033B2 (en) | 2000-04-04 | 2000-04-04 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4405033B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015176958A (en) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
US9824993B2 (en) | 2015-07-28 | 2017-11-21 | Shinko Electric Industries Co., Ltd. | Packaging structure |
WO2023228811A1 (en) * | 2022-05-25 | 2023-11-30 | ヌヴォトンテクノロジージャパン株式会社 | Semiconductor device |
-
2000
- 2000-04-04 JP JP2000102481A patent/JP4405033B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015176958A (en) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
US9721935B2 (en) | 2014-03-14 | 2017-08-01 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US10128223B2 (en) | 2014-03-14 | 2018-11-13 | Toshiba Memory Corporation | Semiconductor device and manufacturing method thereof |
US9824993B2 (en) | 2015-07-28 | 2017-11-21 | Shinko Electric Industries Co., Ltd. | Packaging structure |
WO2023228811A1 (en) * | 2022-05-25 | 2023-11-30 | ヌヴォトンテクノロジージャパン株式会社 | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP4405033B2 (en) | 2010-01-27 |
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