JP2001291774A - Anti-fuse element and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an anti-fuse element capable of selectively providing a fuse member without the interruption of any photo-lithography process and a method for manufacturing this anti-fuse element. SOLUTION: A fuse forming area 14 includes a wiring layer 13 in the other via or wiring area formed in the same process as a lower electrode 131. The fuse forming area 14 is formed as a self-aligned structure which is allowed to remain after the lamination of the lower electrode 131, a fuse film 15, and an upper electrode 16 is flattened by a CMP method. That is, the fuse formation area 14 is constituted by carrying out etching in a dimension larger than that of the other via or wiring area formed in the same process. Then, burial is sufficiently achieved only with the wiring layer 13 in the other via or wiring area, and a normal wiring layer without the fuse film 15 is constituted after flattening, and the fuse film 15 is allowed to remain at the desired part of a fuse element where the etching dimension is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the manufacture of semiconductor devices, and more particularly to an electrically programmable anti-fuse element and a method of manufacturing the same.

[0002]

2. Description of the Related Art An anti-fuse element is generally provided between conductors and is in a non-conductive state in an initial state, and can switch its part to an electrically conductive state as required. It is.

FIGS. 5A and 5B are cross-sectional views of main parts showing a conventional anti-fuse element in a wiring connection part. FIG. 6 shows a normal wiring connection part in which an anti-fuse element is not formed. FIG.

In FIG. 5A, an upper wiring layer 53 is formed on a lower wiring layer 51 via an interlayer insulating film 52. The connection hole 54 between these wiring layers has an upper wiring layer 53
The connecting member 55 made of a conductive member or a conductive plug member is embedded. The fuse film 56 is formed in a predetermined region on the lower wiring layer 51 so as to be disposed at the bottom of the connection hole 54. The fuse film 56 is a dielectric that exhibits insulation or high resistance.

The anti-fuse element AF1 is composed of the above-mentioned fuse film 56 and a pair of electrode portions formed in a predetermined region of the connecting member 55 and the lower wiring layer 51 that separate the fuse film 56. The program is performed by selectively applying a high voltage to the electrode unit. As a result, the fuse film 56 undergoes dielectric breakdown, and transitions from the non-conductive state to the conductive state. As a result, the wiring layers 51 and 53 are electrically connected.

In FIG. 5B, an upper wiring layer 53 is formed on a lower wiring layer 51 via an interlayer insulating film 52. The upper wiring layer 53 is provided in the connection hole 54 between these wiring layers.
The same or different connecting member 57 is embedded. The fuse film 58 is disposed on the top of the connection member 57, and is covered with the upper wiring layer 53.

The anti-fuse element AF2 is composed of the above-mentioned fuse film 58 and a pair of electrode portions defined by predetermined regions of the upper wiring layer 53 and the connecting member 57 which separate the fuse film 58. The program is performed by selectively applying a high voltage to the electrode unit. As a result, dielectric breakdown of the fuse film 58 is caused, and a transition is made from a non-conductive state to a conductive state. As a result, the wiring layers are electrically connected.

In FIG. 6, an upper wiring layer 53 is formed on a lower wiring layer 51 via an interlayer insulating film 52.
In the connection holes 54 between these wiring layers, a connection member 55 made of a conductive member of the upper wiring layer 53 or a conductive plug member is embedded.

If an attempt is made to coexist a configuration in which antifuse elements are provided as shown in FIG. 5A or 5B with a normal configuration having no antifuse elements as shown in FIG. A photolithography step for selectively forming (the fuse film 56 or 58) is naturally required.

[0010]

As described above, conventionally,
In order to coexist the configuration in which the anti-fuse element is provided and the normal configuration without the anti-fuse element between the same wiring layer, a photolithography step was required for the selective formation of the fuse member. Since the photolithography process for the antifuse element is performed, there is a problem in that manufacturing costs such as mask production, resist formation, and etching are increased, the number of processes is increased, and the number of days for manufacturing products is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an anti-fuse element in which a fuse member can be selectively provided without performing a photolithography process, and a method of manufacturing the same. .

[0012]

An antifuse element according to the present invention has a concave fuse forming region provided in an electrical connection region in an insulating film and a second fuse forming region formed along an inner wall of the fuse forming region. A first electrode portion, a fuse film formed along the inner wall of the first electrode portion, and a first upper wiring layer connected to a predetermined upper wiring layer formed near the center of the fuse formation region so as to be surrounded by the fuse film. And two electrode portions.

The method of manufacturing an anti-fuse element according to the present invention relates to embedding of a conductive member by a damascene method, and forms an etching region for forming a fuse in which dimensions are selectively changed from a region related to another wiring to be simultaneously processed. A step of depositing, as a first electrode, a conductive member that sufficiently buries a region related to the other wiring in the fuse-forming etching region, and further sequentially stacks a conductive member to be a fuse film and a second electrode. A step of embedding the inside of the fuse-forming etching region; and a step of flattening the fuse film only in the fuse-forming etching region.

A method of manufacturing an anti-fuse element according to a more specific embodiment of the present invention includes a step of forming a first interlayer insulating film on a semiconductor substrate and a step of forming a first interlayer insulating film on a semiconductor substrate. The first so as to have a large size
Forming a fuse forming opening region by selectively processing an interlayer insulating film; and forming a first region having a thickness such that the region related to the other wiring is filled in the fuse forming opening region. A first conductive member serving as an electrode portion, an insulating or high-resistance dielectric film serving as a fuse film, and a second conductive member serving as a second electrode portion;
Forming a laminate in which conductive members are sequentially embedded, leaving the laminate only in the fuse forming opening region, and forming a second interlayer insulating film including on the fuse forming opening region. And a step of forming a wiring layer connected to the second conductive member through selective processing of the second interlayer insulating film.

According to the antifuse element and the method of manufacturing the same of the present invention, the antifuse element is formed in a desired connection region in a self-aligned manner. That is, an opening region for fuse formation having a size larger than that of another via or wiring region formed in the same step is formed.

The opening area for forming a fuse cannot be filled with only the first conductive member serving as the first electrode portion, and is formed of an insulating or high-resistance dielectric film serving as a fuse film and a second conductive member serving as a second electrode portion. Are sequentially embedded. On the other hand, the other via and wiring regions formed in the same step are all dimensioned to be sufficiently buried with only the first conductive member serving as the first electrode portion. This allows
After the flattening step, the above-mentioned lamination remains only in the fuse forming opening region, and the others are only the embedded portions of the first conductive member.

[0017]

FIG. 1 is a sectional view showing a configuration of an anti-fuse element according to an embodiment of the present invention. An electrical connection region 12 is formed in the insulating film 11. In the lower wiring layer 13, the connection region 12 includes the fuse formation region 1.
4 are formed.

The wiring layer 13 made of, for example, an Al alloy includes a lower electrode 131. The lower electrode 131 is formed along the inner wall of the fuse formation region 14. This lower electrode 1
Fuse film 15 is formed along the inner wall of 31.
The fuse film 15 is made of, for example, α-Si (amorphous silicon). An upper electrode 16 is formed near the center of the fuse forming region 14 so as to be surrounded by the fuse film 15.
Are formed. The upper electrode 16 is connected to an upper wiring layer 17 made of, for example, an Al alloy. In addition, wiring layer 1
7 and the upper electrode 16 may be connected via a plug member different from the conductive material of the wiring layer 17.

The anti-fuse element AF is composed of the fuse film 15 and a pair of electrodes 131 and 16 separating the fuse film 15. The program selectively operates the electrodes 131 and 16
This is performed by applying a high voltage in between. As a result, the fuse film 15 undergoes dielectric breakdown, and transitions from the non-conductive state to the conductive state. As a result, the lower wiring layer 13 and the upper wiring layer 17 are electrically connected.

According to the above configuration, the fuse forming region 14
Has a self-aligned damascene structure in which the stack of the lower electrode 131, the fuse film 15, and the upper electrode 16 is planarized and remains. That is, the fuse formation region 14 is configured to have a size larger than other vias and wiring regions formed in the same process, and the above-described stack is left after planarization.

In other vias and wiring regions (not shown) formed in the same step, dimensions are set so that the above-mentioned laminate does not remain after flattening. Hereinafter, a method for manufacturing the anti-fuse element according to the present invention will be described based on this.

2 (a) and 2 (b) to 4 (a) and 4 (b)
3A to 3C are cross-sectional views illustrating a main part of a method for manufacturing an antifuse element according to the present invention in the order of steps. Each figure (a)
A region of a normal wiring connection portion where anti-fuse elements formed simultaneously are not formed is shown, and (b) shows a region where anti-fuse elements are formed.

As shown in FIGS. 2A and 2B, an oxide film 22 is deposited on a conductive region (here, a wiring layer) 21a on a semiconductor substrate or on an arbitrary insulating layer. afterwards,
An insulating film having an etching selectivity with respect to the oxide film 22, for example, a nitride film 23 is formed. Next, an opening 24a is selectively formed on the nitride film 23 by photolithography to form a connection hole. Thereafter, an oxide film 25 is deposited again on the nitride film 23 including on the opening 24a. An interlayer insulating film including the oxide film 22, the oxide film 25, and the nitride film 23 is formed.

Next, the oxide films 25 and 22 are continuously etched by using a photolithography technique. This etching includes the opening 24a of the nitride film 23 as an etching region.

As a result, in FIG. 2A, for example, a predetermined wiring groove and an etching region 261 as a via hole are formed.
a, 262a. That is, the etching region 261a of the oxide film 25 becomes a wiring groove pattern (or a simple via hole pattern may be formed).
The etched region 262a of the oxide film 22 forms a via hole through the opening 24a using the nitride film 23 as a mask, and reaches the conductive region 21a.

In FIG. 2B, an etching area 261b is formed as a predetermined fuse forming opening area. The etching area 261b is
This is a recess-shaped pattern which is wider than a and can be filled by lamination of a conductive member / fuse film / conductive member described later necessary for fuse formation.

Next, as shown in FIGS. 3A and 3B,
First conductive member 27 made of, for example, an Al alloy on oxide film 25
By CVD or Chemical Vapor Depositio
n) Deposit by method. The first conductive member 27 needs to have a thickness that can sufficiently embed the etching regions 262a and 261a. The first conductive member 27 is simultaneously formed in the etching region 261b (opening region for fuse formation).
Formed along the inner wall of the

Subsequently, a fuse film 28 is formed on the first conductive member 27. Here, the fuse film 28 uses an amorphous silicon layer, and is deposited to a predetermined thickness that can be a fuse. Thus, in FIG. 3B, the fuse film 28 is formed along the inner wall of the first conductive member 27 in the etching region 261b (opening region for fuse formation).

Further, for example, A
The second conductive member 29 made of an alloy is formed by sputtering or CV.
Formed by Method D. By the second conductive member 29, the etching region 261b (fuse forming opening region) in FIG. 3B is completely buried.

Next, as shown in FIGS. 4 (a) and 4 (b),
The second conductive member 29, the fuse film 28 and the first conductive member 27 are flattened to the level of the oxide film 25 by using a CMP (Chemical Mechanical Polishing) method.

As a result, in FIG. 4A, the first conductive member 2 embedded in the etching regions 262a and 261a is formed.
Only 7 remains. In FIG. 4B, the second conductive member 2
9. The lamination of the fuse film 28 and the first conductive member 27 remains only in the etching region 261b (fuse forming opening region). Thus, an anti-fuse element AF having the second conductive member 29 as the upper electrode and the first conductive member 27 as the lower electrode with the fuse film 28 interposed therebetween is formed.

Thereafter, by continuing the general wiring process, a desired wiring layer pattern can be formed. That is, although not shown, the next interlayer insulating film is formed on the flattened entire surface, and at least a wiring structure via a via connected to the second conductive member 29 in FIG. The following configuration is obtained. At the same time, FIG.
In (a), a wiring layer (or a plug layer of a via hole)
A wiring structure is formed via a via connected to the first conductive member 27 (not shown).

According to the method of the above embodiment, a self-aligned anti-fuse element AF is formed in a desired connection region in the interlayer insulating film at the same time as the formation of wiring by the damascene (or dual damascene) method.

That is, the depth and width of both the etching region 261a for forming the normal wiring or via and the etching region 261b for forming the fuse element AF are mainly the first.
They are separately formed in consideration of the thickness of the deposition of the conductive member 27 and the second conductive member 29.

That is, all other vias and wiring regions where antifuse elements are not formed are left as etched regions 261a that are sufficiently buried only with the first conductive member 27.

On the other hand, the etching region 261b serving as the fuse forming opening region cannot be filled with only the first conductive member 27, and the fuse film 28 and the second conductive member 29
Are made large enough to be embedded by sequential lamination.

Thus, after the flattening step, the first conductive member 27 / fuse film 28 / second conductive member 29 stack remains only in the fuse forming opening region, and the other portions are filled with the first conductive member 27. Only the part. Therefore, the fuse film can be selectively provided by a self-aligning action without going through a photolithography step of selectively patterning the fuse film.

As described above, by controlling the combinations of the thicknesses of the first conductive member 27 and the second conductive member 29 and the depths and widths of the etching regions 261a and 261b,
Both the wiring layer and the anti-fuse element can be formed simultaneously without increasing the number of masks. This also minimizes the increase in processes. In addition, adverse effects such as an increase in wiring capacitance and resistance hardly occur on the normal wiring formed at this time. As a result, with respect to a programmable device having an anti-fuse element, it is possible to reduce the manufacturing cost and shorten the delivery time without losing the reliability.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the case where the wiring and the conductive member of the fuse electrode are formed of the Al alloy by the sputtering method or the CVD method has been described.
It need not be an alloy. For example, as a method for forming the conductive member, a method such as a plating method or a method of applying a conductive paste can be used. In addition, C as a conductive member
Metals such as u, Au, Ag, W, Ti, Co, and Ni, alloys thereof, silicide materials thereof, and polysilicon can be used. That is, a member that can be used as a conductive wiring and an electrode is applicable.

[0040]

As described above, according to the anti-fuse element and the method of manufacturing the same of the present invention, a fuse forming opening region having a size larger than that of another via or wiring formed in the same step is formed. Form. The fuse forming opening region is filled with the stack for forming the anti-fuse element. On the other hand, other via and wiring regions formed in the same process have small dimensions and are sufficiently buried with a wiring member not including a fuse film. Therefore, after the flattening process, the above-mentioned stack remains only in the fuse forming opening region,
Others do not include a fuse film and are only wiring members. Thus, an anti-fuse element is formed in a self-aligned manner in a desired connection region in the interlayer insulating film.

As a result, it is possible to selectively provide a fuse member without going through a photolithography step, to reduce the manufacturing cost while maintaining the reliability, and to contribute to shortening the production time of a programmable device. The manufacturing method can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of an anti-fuse element according to an embodiment of the present invention.

FIGS. 2A and 2B are first cross-sectional views each showing a main part of a method of manufacturing an anti-fuse element according to the present invention in the order of steps. (A) shows a region of a normal wiring connection portion where anti-fuse elements formed simultaneously are not formed,
(B) shows a region where an anti-fuse element is formed.

FIGS. 3A and 3B are second cross-sectional views each showing a main part of a method of manufacturing an anti-fuse element according to the present invention in the order of steps. (A) shows a region of a normal wiring connection portion where anti-fuse elements formed simultaneously are not formed,
(B) shows a region where an anti-fuse element is formed.

FIGS. 4A and 4B are third cross-sectional views each showing a main part of a method of manufacturing an anti-fuse element according to the present invention in the order of steps. (A) shows a region of a normal wiring connection portion where anti-fuse elements formed simultaneously are not formed,
(B) shows a region where an anti-fuse element is formed.

FIGS. 5A and 5B are cross-sectional views of main parts showing a conventional anti-fuse element in a wiring connection part.

FIG. 6 is a cross-sectional view showing a normal wiring connection portion where an anti-fuse element is not formed.

[Explanation of symbols]

 11, 52: insulating film 12: connection region 13: lower wiring layer 131: lower electrode 14: fuse forming region 15, 56, 58: fuse film 16: upper electrode 17: upper wiring layer 21a: conductive region 22, 25 ... Oxide film 23... Nitride film 24 a... Opening portions 261 a, 261 b, 262 a... Etching region 27. 55, 57: Connection member AF, AF1, AF2: Anti-fuse element

Claims (6)

[Claims] A concave fuse forming region provided in an electrical connection region in an insulating film; a first electrode portion formed along an inner wall of the fuse forming region; and an inner wall of the first electrode portion. And a second electrode portion connected to a predetermined upper wiring layer formed near the center of the fuse forming region so as to be surrounded by the fuse film. Anti-fuse element. 2. The fuse forming region is a region in which a dimension is selectively changed from a region related to another wiring to be processed simultaneously with respect to embedding of a conductive member by a damascene method, and wherein the first electrode portion, 2. The anti-fuse element according to claim 1, wherein the stack of the fuse film and the second electrode portion has a planarized and self-aligned damascene structure that remains. 3. A step of forming a fuse-forming etching region having a dimension selectively changed from a region related to another wiring to be processed simultaneously with respect to embedding of a conductive member by a damascene method; A conductive member that sufficiently fills the region related to the other wiring is deposited as a first electrode, and a fuse film and a conductive member serving as a second electrode are sequentially stacked to fill the etching region for fuse formation. And a flattening step of leaving the fuse film only in the fuse-forming etching region. 4. A process of forming a first interlayer insulating film on a semiconductor substrate, and selectively processing the first interlayer insulating film so as to have a size larger than a region related to another wiring to be processed at the same time. Forming a fuse-forming opening region, and a first conductive member serving as a first electrode portion having a thickness sufficient to fill the region related to the other wiring in the fuse-forming opening region. Forming a stack in which an insulating or high-resistance dielectric film serving as a fuse film and a second conductive member serving as a second electrode portion are sequentially embedded, and leaving the stack only in the fuse forming opening region. Forming a second interlayer insulating film including over the fuse forming opening region; and forming a wiring layer connected to the second conductive member through selective processing of the second interlayer insulating film. Forming step Method for manufacturing antifuse element characterized. 5. The method according to claim 4, wherein the first conductive member forms a wiring layer having no fuse film in a region related to the other wiring. 6. The method for manufacturing an anti-fuse element according to claim 4, wherein the first conductive member forms a via having no fuse film in a region related to the another wiring.