JP2001286130A - Power-factor improving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cut down the cross loss in a main switching element and to enhance efficiency as well as to materialize downsizing of a circuit. SOLUTION: A closed circuit is composed of a MOS FET 5, an inductance 13 for resonance and a MOS FET 18 that is an auxiliary element. By way of turning the MOS FET 18 on, a capacitance 11 connected to both ends of the MOS FET 5, i.e., between the drain and sources, and the inductance 13 for resonance are resonated. The circuit is so configured as to turn the MOS FET 5 on in this resonance. Hereby, no current flows into the MOS FET 5 and the cross loss at a turn-on time of the MOS FET 5 is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called boost converter type power factor improving circuit for improving a power factor of a power supply device or the like.

[0002]

In recent years, a boost converter type power factor improving circuit called an active harmonic filter has been incorporated in order to suppress harmonics generated from a power supply device or the like. FIG. 14 shows an example of such a power factor improving circuit. In FIG. 14, reference numerals 1 and 2 denote input terminals, which supply an input voltage Vin by full-wave rectifying an AC input voltage from a commercial power supply. A full-wave rectifier 3 such as a bridge diode is connected. Input terminal 1,
2, a series circuit of an inductance 4 and a MOSFET 5 serving as a main switching element is connected between
Between both ends of the S-type FET 5, that is, between the drain and the source,
A series circuit of a diode 6 and a smoothing capacitor 7 is connected. Output terminals 8 and 9 for extracting a constant output voltage Vout are connected between both ends of the smoothing capacitor 7.

In the power factor correction circuit having the above configuration, a MOS type F
When ET5 turns on, the input voltage Vin between input terminals 1 and 2
Is applied to the inductance 4 and this inductance 4
As the inductor current flowing through
Energy is stored in the inductance 4. On the other hand, when the MOS FET 5 is turned off, the input voltage V
The energy stored in the inductance 4 is sent out from the diode 6 to the smoothing capacitor 7 on the output side together with the energy due to the in, the inductor current flowing through the inductance 4 is sloping down, and the output voltage Vout higher than the input voltage Vin is output. It is taken out from between both ends of the terminals 8 and 9. At this time, if the switching of the MOS FET 5 is controlled so that the inductor current flowing through the inductance 4 has a full-wave rectified waveform proportional to the pulsation of the input voltage Vin, for example, a power supply device connected between the output terminals 8 and 9 can be provided. This becomes equivalent to a pure resistance load for the commercial power supply, and the power factor can be improved.

By the way, in the above-mentioned conventional power factor improving circuit,
When the MOS FET 5 is switched, the cross-loss at the time of turn-off and at the time of turn-on is large due to the presence of the DC-biased current I. That is,
As shown in FIG. 15, during the off period of the MOSFET 5, the voltage VDS is applied between the drain and the source of the MOSFET 5.
Occurs, and a current ID flows between the drain and the source of the MOSFET 5 during the ON period of the MOSFET 5,
Immediately after the MOSFET 5 switches from off to on,
Immediately after switching from on to off, the current ID and the voltage VDS cross each other, and this
It becomes the loss (cross loss) of the type FET5. These problems lead to a reduction in the efficiency of the entire power factor correction circuit,
With an increase in the heat generated by the S-type FET 5, a large heat radiation area has to be taken, which makes it difficult to reduce the size of the circuit.

Therefore, the present invention solves the above problems,
It is an object of the present invention to provide a power factor improving circuit capable of reducing the cross loss of a main switching element, improving the efficiency and reducing the size of the circuit.

[0006]

According to a first aspect of the present invention, there is provided a power factor improving circuit, comprising: a full-wave rectifier connected to a series circuit of a main switching element and an inductance; A series circuit of a first diode and a smoothing capacitor is connected between both ends of the switching element, so that an inductor current flowing through the inductance has a full-wave rectified waveform proportional to an input voltage from the full-wave rectifier.
In the power factor correction circuit that controls the switching of the main switching element, a closed circuit is formed by the main switching element, the resonance inductance, and the auxiliary switching element, and by turning on the auxiliary switching element, both ends of the main switching element The resonance capacitor is configured to resonate the capacitance connected therebetween and the resonance inductance, and the main switching element is turned on during the resonance.

In this case, by controlling the switching of the main switching element, the inductor current flowing through the inductance is proportional to the full-wave rectified waveform that is proportional to the input voltage from the full-wave rectifier, thereby improving the power factor. When the auxiliary switching element is first turned on from a state where both the main switching element and the auxiliary switching element are off, the capacitance and the resonance inductance resonate, and a resonance current is returned from the capacitance to the capacitance via the resonance inductance. Therefore, if the main switching element is turned on during this resonance, no current flows into the main switching element itself, and there is no cross loss when the main switching element is turned on. As a result, the efficiency of the power factor improving circuit is improved, and the heat generation of the main switching element is reduced, so that the circuit can be easily downsized.

According to a second aspect of the present invention, in addition to the configuration described in the first aspect, when the voltage between both ends of the main switching element becomes 0 V, the main switching element is turned on. It is configured as follows.

When the capacitance is completely discharged by resonance with the resonance inductance after the auxiliary switching element is turned on, the voltage across the main switching element becomes 0V. At this time, no current flows into the main switching element, and if the main switching element is turned on, the cross loss of the main switching element can be reliably reduced.

According to a third aspect of the present invention, in addition to the configuration of the first or second aspect, the capacitance is an output capacitance parasitic to the main switching element.

With this configuration, there is no need to connect an external capacitive element between both ends of the main switching element, and the number of components mounted can be reduced.

According to a fourth aspect of the present invention, in addition to the configuration described in any one of the first to third aspects, one end of the inductance, the main switching element and the first diode are provided. And the resonance inductance is inserted and connected to the connection point (1).

In this case, when the main switching element and the auxiliary switching element are both turned off and the auxiliary switching element is turned on, an induced electromotive force is generated in the resonance inductance, and the energy stored in the resonance inductance is generated. It is sent to the smoothing capacitor on the output side.

According to a fifth aspect of the present invention, in addition to the configuration described in the fourth aspect, the power factor improving circuit further comprises a circuit provided between one end of the inductance and a connection point between the main switching element and the first diode. , A series circuit of a second diode and a capacitor for voltage clamping.

When the auxiliary switching element shifts from the on state to the off state, the voltage between both ends of the auxiliary switching element tends to increase due to the energy stored in the inductance and the resonance inductance. But,
These energies are stored in the voltage clamping capacitor via the second diode, thereby preventing the voltage across the auxiliary switching element from jumping up. Therefore, the loss at the time of turning off the auxiliary switching element is also reduced.

A power factor improving circuit according to claim 6 of the present invention is characterized in that, in addition to the configuration described in claim 5, the second diode is configured by connecting a plurality of diodes having the same characteristic in series. I do.

Thus, the recovery time of the second diode can be shortened and the flow of the reverse current can be suppressed.

According to a seventh aspect of the present invention, in addition to the configuration described in the fifth or sixth aspect, a connection point between the second diode and the capacitor for voltage clamping and the first diode are provided. And a third diode connected between the connection point of the smoothing capacitor.

In this case, when the auxiliary switching element is turned off and the charging voltage of the voltage clamping capacitor becomes larger than the value obtained by adding the forward voltage drop of the third diode to the charging voltage of the smoothing capacitor, The energy of the inductance and the resonance inductance can be sent to the smoothing capacitor without waste while the charging voltage of the voltage clamping capacitor is clamped.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a power factor improving circuit according to the present invention will be described below with reference to the accompanying drawings. The same parts as those in the conventional example are denoted by the same reference numerals, and the description of the common parts will be omitted because they are duplicated. In FIG. 1 showing the overall configuration of the circuit, the basic configuration as a boost converter is the same as that of the conventional example, and is applied between both ends of input terminals 1 and 2 to which a full-wave rectified DC input voltage Vinga is applied. Inductance 4 and MOS-type FET as main switching element
5, a series circuit of a diode 6 as a first diode and a smoothing capacitor 7 is connected between both ends of the MOS FET 5, that is, between the drain and the source. And output terminals 8 and 9 for extracting the output voltage Vout. The capacitance 11 connected between the drain and the source of the MOSFET 5 is an output capacitance that is parasitic on the MOSFET 5. Also, the same MOS
Diode connected between the drain and source of FET5
Reference numeral 12 denotes a built-in diode existing in the MOSFET 5.

In the present embodiment, in addition to the circuit configuration of the boost converter, one end of the inductance 4 not connected to the input terminal 1, the MOS FET 5 and the diode 6
Resonance inductance 13 inserted between the
A series circuit of diodes 14 and 15 as second diodes connected between both ends of the resonance inductance 13 and a voltage clamping capacitor 16;
One end is connected to the connection point between
A series circuit of a diode 17 having the other end connected to the connection point of the source of the ET 5 and the smoothing capacitor 7 and a MOSFET 18 as an auxiliary switching element, and an anode connected to the connection point of the diode 15 and the voltage clamping capacitor 16 And one end is connected to the anode of the diode 17 to stabilize the operation, and one end is connected to the diode 19 in which the cathode is connected to the connection point of the diode 6 and the smoothing capacitor 7.
A series circuit of a diode 20 and a resistor 21 having the other end connected to a connection point between the source of the S-type FET 5 and the smoothing capacitor 7 is provided. The drain of the MOS FET 18
Between the sources, a capacitance 22 corresponding to the output capacitance and a diode 23 corresponding to the built-in diode are connected as in the case of the MOS FET 5.

Next, the operation of the above configuration will be described with reference to FIGS. First, MO
When the S-type FETs 5 and 18 are both off, the input terminals 1 and
Due to the input voltage Vin applied between the two, as shown in FIG. 2, a current I1 flows through the path of the input terminal 1, the inductance 4, the resonance inductance 13, the diode 6, the smoothing capacitor 7, and the input terminal 2. Here, when the MOS-type FET 18 as the auxiliary switching element is turned on while the MOS-type FET 5 as the main switching element is turned off, the input voltage Vin applied between the input terminals 1 and 2 as shown in FIG. , Input terminal 1 → inductance 4
The current I2 flows through the path from the diode 17 to the MOS FET 18 and the input terminal 2, and energy is stored in the inductance 4.

On the other hand, since the resonance inductance 13 has stored energy by the current I1 shown in FIG. 2, the MOS type FET 5 is turned off and the MOS type FE is turned off.
At the moment when T18 is turned on, the induced electromotive force V in the direction shown in FIG.
3 occurs in the resonance inductance 13. This allows
Until all the energy of the resonance inductance 13 is released, the inertia current I3 of the resonance inductance 13 flows through the path of the resonance inductance 13 → the diode 6 → the smoothing capacitor 7 → the input terminal 2. Thereafter, when the energy due to the induced electromotive force V3 generated in the resonance inductance 13 disappears, as shown in FIG.
13 is the capacitance which is the output capacitance of the MOSFET 5
Resonating with 11, a resonance current I4 flows in a closed circuit formed by capacitance 11 → resonance inductance 13 → diode 17 → MOS type FET 18 → capacitance 11.

FIG. 6 shows a change in the current flowing through the resonance inductance 13 as viewed from the MOS FET 5 at this time. In FIG. 6, when the MOSFET 18 is turned on while the MOSFET 5 is off, the energy stored in the resonance inductance 13 is returned to the input side.
The inertia current I3 also decreases in slope (period t1). After that, when all the energy stored in the resonance inductance 13 is released, the resonance current I4 in the opposite direction increases in a substantially sinusoidal manner (period t2). In this embodiment, a control sequence in which the voltage at the connection point A between the resonance inductance 13 and the MOSFET 5 shown in FIG. 5 is 0 V, that is, at the timing B when the resonance current I4 becomes substantially maximum, Has become. Although not shown, a voltage detection circuit for detecting a voltage between both ends of the MOS FET 5 (a voltage VDS between the drain and the source) and a signal that the voltage between both ends of the MOS FET 5 has become 0 V by this voltage detection circuit. The detection is realized by a control circuit that turns on the MOSFET 5.

When the MOS FET 5 is turned on, M
FIG. 7 shows the drain-source voltage VDS and the drain current ID of the OS-type FET 5. In FIG. 7, B
Is the timing at which the MOS FET 5 is turned on. As is apparent from FIG. 7, the resonance current I4 generated by the resonance inductance 13 and the capacitance 11 until the MOSFET 5 turns on and the drain-source voltage VDS of the MOSFET 5 drops to 0V. , MOS
The current flowing into the FET 5 becomes zero, and the loss (cross loss) when the MOS FET 5 is turned on disappears.

Thereafter, when the MOSFET 5 is turned on,
Another MOS type FET 18 is turned off, and as shown in FIG. 8, the input terminal 1 → inductance 4 → diode 14 → diode 15 → voltage clamping capacitor 16 → MOS type F
The current I5 flows through the path from ET5 to the input terminal 2, and
Due to the characteristics of the resonance inductance 13, the current I6 flows even in a closed circuit formed by the resonance inductance 13 → the diode 14 → the diode 15 → the voltage clamping capacitor 16 → the resonance inductance 13, and the voltage clamping capacitor 16 is charged. . When the charging voltage between both ends of the voltage clamping capacitor 16 becomes larger than the value obtained by adding the forward voltage drop VF of the diode 19 to the charging voltage of the smoothing capacitor 7, the voltage clamping capacitor 16
And the drain-source of the MOS FET 18 is clamped. At this time, as shown in FIG. 9, the currents I5 and I6 flowing through the voltage clamping capacitor 16 are both cut off, and the diode 19 is turned on instead, and the input terminal 1 → inductance 4 → diode 14 → diode 15 → A current I7 flows through a path from the diode 19 to the smoothing capacitor 7 to the input terminal 2. FIG.
As indicated by 0, at the same time as the current I7 flows, the energy stored in the resonance inductance 13 causes the resonance inductance 13 → diode 14 → diode 15 → diode 19 → smoothing capacitor 7 → diode 12 → inductance 13 Another current I8 flows through the path, and due to these currents I7 and I8, the energy of the inductance 4 and the resonance inductance 13 is sent to the output-side smoothing capacitor 7 without waste.

That is, when the MOS FET 18 is turned off,
The voltage between the drain and the source of the MOS FET 18 tends to increase due to the energy of the inductance 4 and the resonance inductance 13. By clamping the drain-source voltage of the MOS FET 18 by the voltage clamping capacitor 16, This prevents the voltage from jumping up when the FET 18 is turned off.
At the time of turn-off. In this embodiment, two diodes 14 and 15 having the same characteristics are connected in series as the second diode.
The 15 recovery time has been accelerated to suppress the reverse current flow.

Thereafter, when the energy of the resonance inductance 13 runs out, as shown in FIG. 11, a current I9 flows through the path of the resonance inductance 13 → the MOS type FET 5 → the input terminal 2, and the energy is stored in the resonance inductance 13. At the same time, the current I7 continues to flow due to the energy stored in the inductance 4. When the current I7 stops flowing, as shown in FIG. 12, the input voltage Vin applied between the input terminals 1 and 2 causes the input terminal 1 → the inductance 4 → the resonance inductance 13 → the MOS type FET 5 → the input terminal. The current I10 flows through the path 2 and energy is stored in the inductance 4 and the resonance inductance 13.

The MOSFET 5 is then turned off,
Both the MOS FETs 5 and 18 are turned off and return to the state of FIG. At this time, the electric charge stored in the voltage clamping capacitor 16 is changed by the induced electromotive force of the inductance 4 and the resonance inductance 13 into the MOS FET 5.
Rises, the diode 19 moves from the diode 19 to the smoothing capacitor 7 to the input terminal 2 and discharges. At the same time, the capacitance 11 is charged. And
Such a series of operations is repeatedly performed. Finally,
The drain current ID and the drain-source voltage VDS of the MOS FET 5 are as shown in FIG.

As described above, in this embodiment, the full-wave rectifier 3
A series circuit of a MOSFET 5 serving as a main switching element and an inductance 4 is connected, and a series circuit of a diode 6 serving as a first diode and a smoothing capacitor 7 is connected between both ends of the MOSFET 5.
MOS type F so that the inductor current flowing through the MOSFET has a full-wave rectified waveform proportional to the input voltage Vin from the full-wave rectifier 3.
In a power factor improvement circuit that controls switching of ET5,
A closed circuit is formed by the MOS FET 5, the resonance inductance 13, and the MOS FET 18 serving as an auxiliary switching element.
The configuration is such that the capacitance 11 connected between both ends of the S-type FET 5, that is, between the drain and the source, and the resonance inductance 13 resonate, and the MOS-type FET 5 is turned on during this resonance.

In this case, the switching control of the MOS FET 5 causes the inductor current flowing through the inductance 4 to be proportional to the full-wave rectified waveform proportional to the input voltage Vin from the full-wave rectifier 3, thereby improving the power factor. Can be When the MOS FET 18 is first turned on from the state where both the MOS FET 5 and the MOS FET 18 are off, the capacitance 11 and the resonance inductance 13 resonate, and return from the capacitance 11 to the capacitance 11 via the resonance inductance 13. Since the resonance current I4 is generated, if the MOS FET 5 is turned on during this resonance, MO
No current flows into the S-type FET 5 itself, and there is no cross-loss when the MOS-type FET 5 is turned on. This improves the efficiency of the power factor correction circuit,
Since the heat generated by the MOS FET 5 is reduced, the size of the circuit can be easily reduced.

In this embodiment, when the voltage between the drain and the source of the MOS FET 5 becomes 0 V, this MO
The configuration is such that the S-type FET 5 is turned on. In this case, when the capacitance 11 is completely discharged by the resonance with the resonance inductance 13 after the MOS FET 18 is turned on, the drain-source voltage of the MOS FET 5 becomes zero.
V. At this point, no current flows into the MOSFET 5 and if the MOSFET 5 is turned on,
Cross loss of the MOS FET 5 can be reliably reduced.

Further, in this embodiment, the capacitance 11 is constituted by an output capacitance which is parasitic on the MOSFET 5, and in this case, there is no need to connect an external capacitive element between the drain and the source of the MOSFET 5; The number of components mounted can be reduced.

In this embodiment, a resonance inductance 13 is inserted and connected between one end of the inductance 4 and a connection point between the MOS FET 5 and the diode 6.
In this case, an induced electromotive force is generated in the resonance inductance 13 at the moment when the MOS FET 18 is turned on from the state where both the MOS FET 5 and the MOS FET 18 are off,
The energy stored in the resonance inductance 13 is sent to the smoothing capacitor 7 on the output side.

Further, in the present embodiment, a series circuit of diodes 14, 15 as a second diode and a voltage clamping capacitor 16 is provided between one end of the inductance 4 and a connection point of the MOS FET 5 and the diode 6. Connected. In this case, the MOS FET 5 is turned on, and at the same time, the MOS FET 18 is turned off.
Is turned off, the energy stored in the inductance 4 and the resonance inductance 13 tends to increase the drain-source voltage of the MOSFET 18. However, these energies are stored in the voltage crank capacitor 16 via the diodes 14 and 15 and
The jump of the drain-source voltage of the S-type FET 18 is prevented. Therefore, the loss at the time of turning off the MOS FET 18 is also reduced.

In this embodiment, the second diode is formed by connecting a plurality of diodes 14 and 15 having the same characteristics in series. Thus, the recovery time of the second diode can be shortened, and the flow of the reverse current can be suppressed.

Further, in this embodiment, the connection point of the diode 15 and the capacitor 16 for voltage clamping is
A diode 19, which is a third diode, is connected between the power supply and the connection point of the smoothing capacitor 7.

In this case, if the charging voltage of the voltage clamping capacitor 16 becomes larger than the value obtained by adding the forward voltage drop VF of the diode 19 from the charging voltage of the smoothing capacitor 7 when the MOS FET 18 is turned off, With the charging voltage of the voltage clamping capacitor 19 clamped,
The energy of the inductance 4 and the resonance inductance 13 can be sent to the smoothing capacitor 7 without waste.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the capacitances 11 and 22 and the diodes 12 and 23 of the MOS type FETs 5 and 18 may be external elements.

[0040]

According to the power factor improving circuit of the present invention, a full-wave rectifier is connected to a series circuit of a main switching element and an inductance, and a first diode and a smoothing element are provided between both ends of the main switching element. A power factor improving circuit that controls a switching operation of the main switching element so that a series circuit with a capacitor is connected and an inductor current flowing through the inductance has a full-wave rectified waveform proportional to an input voltage from the full-wave rectifier. A closed circuit formed by the main switching element, the resonance inductance, and the auxiliary switching element, and by turning on the auxiliary switching element, the capacitance connected between both ends of the main switching element and the resonance inductance are determined. The main switching element is turned on during the resonance. , And the to reduce the Kurosurosu of the main switching element can be downsized improved and the circuit efficiency.

According to a second aspect of the present invention, in addition to the configuration described in the first aspect, when the voltage between both ends of the main switching element becomes 0 V, the main switching element is turned on. In this case, the cross loss of the main switching element can be reliably reduced.

According to a third aspect of the present invention, in addition to the configuration of the first or second aspect, the capacitance is an output capacitance parasitic to the main switching element. Can reduce the number of mounted components.

According to a fourth aspect of the present invention, there is provided a power factor improving circuit according to any one of the first to third aspects, wherein one end of the inductance, the main switching element and the first diode are provided. And the resonance inductance is inserted and connected between the connection points of the above, and the energy stored in the resonance inductance can be sent to the output-side smoothing capacitor at the moment when the auxiliary switching element is turned on. .

According to a fifth aspect of the present invention, in addition to the configuration described in the fourth aspect, the power factor improving circuit further comprises a circuit provided between one end of the inductance and a connection point between the main switching element and the first diode. , A series circuit of the second diode and the voltage clamping capacitor is connected, and the loss when the auxiliary switching element is turned off can be reduced.

A power factor improving circuit according to a sixth aspect of the present invention is characterized in that, in addition to the configuration described in the fifth aspect, the second diode is configured by connecting a plurality of diodes having the same characteristic in series. The flow of the reverse current in the second diode can be suppressed.

According to a seventh aspect of the present invention, in addition to the configuration of the fifth or sixth aspect, the power factor improving circuit further comprises a connection point between the second diode and the capacitor for voltage clamping, and the first diode. And a third capacitor connected between the smoothing capacitor and the connection point of the smoothing capacitor. When the auxiliary switching element is turned off, energy of the inductance and the resonance inductance can be sent to the smoothing capacitor without waste. .

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of a power factor correction circuit showing one embodiment of the present invention.

FIG. 2 is a schematic explanatory diagram showing a current flow when both a main switching element and an auxiliary switching element are off.

FIG. 3 is a schematic explanatory diagram showing a current flow when the auxiliary switching element is turned on while the main switching element is turned off in the same manner.

FIG. 4 is a schematic explanatory view showing a current flow at the moment when the auxiliary switching element is turned on.

FIG. 5 is a schematic explanatory diagram showing a flow of a current after the energy of the induced electromotive force generated in the resonance inductance in FIG. 4 is lost.

FIG. 6 is a waveform diagram showing a change in a current flowing through the resonance inductance as viewed from the main switching element side.

FIG. 7 is a waveform chart showing a drain-source voltage and a drain current of the main switching element when the main switching element is turned on.

FIG. 8 is a schematic explanatory diagram showing a current flow when the main switching element is turned on and the auxiliary switching element is turned off.

FIG. 9 is a schematic explanatory view showing a flow of current after the voltage of the voltage clamping capacitor is clamped in FIG. 8;

FIG. 10 is a schematic explanatory view showing another current flow after the voltage of the voltage clamping capacitor is clamped in FIG. 8;

FIG. 11 is a schematic explanatory view showing the flow of current after the energy of the resonance inductance has disappeared in FIGS. 9 and 10;

FIG. 12 is a schematic explanatory view showing a current flow after the current I7 stops flowing in FIG. 11;

FIG. 13 is a waveform chart showing a drain current and a drain-source voltage of the main switching element.

FIG. 14 is an overall circuit diagram of a power factor correction circuit showing a conventional example.

FIG. 15 is a switching waveform of a main switching element showing a conventional example.

[Explanation of symbols]

 3 Full-wave rectifier 4 Inductance 5 MOS-type FET (main switching element) 6 Diode (first diode) 7 Smoothing capacitor 11 Capacitance 13 Resonant capacitor 14 Diode (second diode) 15 Diode (second diode) 16 Capacitor for voltage clamp 19 Diode (third diode)

Claims (7)

[Claims] 1. A series circuit of a main switching element and an inductance is connected to a full-wave rectifier, and a series circuit of a first diode and a smoothing capacitor is connected between both ends of the main switching element. In the power factor correction circuit for controlling the switching of the main switching element, the main switching element, the resonance inductance, and the auxiliary switching are controlled so that the flowing inductor current has a full-wave rectified waveform proportional to the input voltage from the full-wave rectification unit. By forming a closed circuit with the element and turning on the auxiliary switching element, the capacitance connected between both ends of the main switching element and the resonance inductance resonate, and the main switching element is turned on during this resonance. A power factor improving circuit characterized in that the power factor improving circuit comprises: 2. The power factor improving circuit according to claim 1, wherein the main switching element is turned on when the voltage between both ends of the main switching element becomes 0V. 3. The power factor correction circuit according to claim 1, wherein the capacitance is an output capacitance parasitic to the main switching element. 4. The resonance inductance according to claim 1, wherein the resonance inductance is inserted and connected between one end of the inductance and a connection point between the main switching element and the first diode. The power factor improving circuit according to any one of the above. 5. A series circuit of a second diode and a capacitor for voltage clamping is connected between one end of the inductance and a connection point between the main switching element and the first diode. The power factor improving circuit according to claim 4. 6. The power factor improving circuit according to claim 5, wherein the second diode is configured by connecting a plurality of diodes having the same characteristics in series. 7. A third diode is connected between a connection point between the second diode and the capacitor for voltage clamping and a connection point between the first diode and the connection point for the smoothing capacitor. 7. The power factor improving circuit according to claim 5, wherein