JP2001285235A - Synchronous data transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous data transmission system that can simultaneously transmit synchronizing signals in the case of transmitting video and audio data at the same time. SOLUTION: A master unit 1 and terminals 2a, 2b,..., 2n are interconnected by crossover wires (a) the master unit sequentially relays and transmits time- division outgoing frames through the terminals, each terminal recovers frame synchronizing signals from the outgoing frames subject to time division to recover data of the outgoing frames, (b) the final terminal receiving the outgoing frames sequentially relays and transmits incoming frames through the other terminals up to the master unit, and the master unit receiving the incoming frame sent in the step (b) executes the step (a). The incoming and outgoing frames are configured with preamble data to generate the frame synchronizing signal within a prescribed period before the data parts of the frames and the data are provided with integral data having a period of an integer multiple of the period of the frame synchronizing signal and a time slot for synchronization information to convert the data synchronizing signal into data for time division transmission.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous data transmission system, and in particular, transmits and receives periodic data between terminals via a main unit together with a synchronization signal, and reproduces the data when the terminal receives the data. The present invention relates to a data transmission method requiring a synchronization signal.

[0002]

2. Description of the Related Art Conventionally, a synchronous data transmission system of this type is known as shown in FIG.

FIG. 5 is a block diagram showing the overall configuration of a conventional synchronous data transmission system. In FIG. 1, a conventional synchronous data transmission system includes a main unit 5 for controlling exchange of signals and data such as video and audio, and terminals 6a, 6b,. 6n, and the main unit 5 and the terminals 6a, 6b,..., 6n are mutually connected via crossover wirings 7a, 7b,.

FIG. 6 shows a block diagram of a main unit and a terminal in a conventional synchronous transmission system. In the figure, a main device 5 includes a data shaping circuit 51 for assembling and separating frames described later, a control circuit 52 for sending control commands to the data shaping circuit 51 and the terminals 6a, 6b,..., 6n. A timing circuit 53 for generating operation timing of each unit, a transceiver 54 for transmitting and receiving data,
It is composed of components such as a synchronous reproduction circuit 55 for reproducing a synchronous signal sent from the final terminal 6n.

The data shaping circuit 51 of the main unit 5 is connected to a control circuit 52, a timing circuit 53 and a transceiver 54, and a synchronous reproducing circuit 55 is connected between the data shaping circuit 51 and the transceiver 54.
Are connected to the control circuit 52 via the timing circuit 53.

The terminals 6a, 6b,..., 6n are provided with a video interface circuit 61 for inputting and outputting video signals, and an audio interface circuit 62 for inputting and outputting audio signals.
A data shaping circuit 63 for assembling and separating frames to be described later; a control circuit 64 for sending a control command to the data shaping circuit 63 and the main device 5; a timing circuit 65 for creating operation timing of each unit; First and second transceivers 66a and 66b for performing the operation, a terminal detection circuit 67 for detecting whether or not the terminal is connected downstream from the own terminal, and a first for reproducing a synchronization signal sent from the main device 5. It comprises a synchronous reproducing circuit 68 and a second synchronous reproducing circuit 69 for reproducing a synchronous signal sent from the final terminal 6n.

The data shaping circuits 63 of the terminals 6a, 6b,..., 6n include a video interface circuit 61, an audio interface circuit 62, a control circuit 64, a timing circuit 65, and first and second transceivers 66a, 66b.
And the first transceiver 66a is connected to the timing circuit 65 via the first synchronous reproduction circuit 68,
The timing circuit 65 includes a video interface circuit 61, an audio interface circuit 62, and a control circuit 6.
4 is connected. Also, the second transceiver 66b
Is connected to a terminal detection circuit 67 and a second synchronous reproduction circuit 69, and the terminal detection circuit 67 is connected to the control circuit 64, and the second synchronous reproduction circuit 69 is connected to the timing circuit 69, respectively.

FIG. 7 is a timing chart showing the structure of a frame in the conventional synchronous data transmission system.
In the figure, the downstream frame S50 is transmitted to the main unit 5 (FIG. 5).
), 6n (see FIG. 5)
The uplink frame S51 is a signal transmitted from the terminals 6a, 6b,..., 6n to the main device 5. Here, both the down frame S50 and the up frame S51 are composed of a preamble, a start flag, data, an end flag, and idle, and the cycle T is always constant. Further, the data of the downstream frame S50 and the data of the upstream frame S51 are both a destination address, a source address, a control command,
It is composed of first and second video data 1 and 2, first and second audio data 1 and 2, other data, and a CRC (cyclic redundancy check code).

FIG. 8A is a schematic diagram of data transmission in a conventional synchronous data transmission system, and FIG.
FIG. 2 shows a block diagram of a data shaping circuit in FIG. In these figures, each terminal 6a, 6b,.
, 70n, and the second register 7a.
, 71n and a multiplexer 72
, 72n. here,
The first registers 70a, 70b,..., 70n have a function of sequentially relaying and transmitting each terminal from the last terminal 6n that has received the downstream frame S50 to the main device 5 from the last terminal 6n. Registers 71a, 71b,.
, 71n have a function of temporarily taking in the upstream frame S51, inserting the own terminal data into the upstream frame S51 and transmitting the data, and furthermore, multiplexers 72a, 72b,.
, 72n have a function of transmitting the upstream frame S51 by switching the first and second registers.

The first register 70a of the terminal 6a is connected to the multiplexer 72a in the terminal 6a and the multiplexer 72b of the downstream terminal 6b adjacent to the terminal 6a. It is connected to the main unit 5 via a multiplexer 72a in 6a.
Also, the first register 70b of the terminal 6b stores
And the second register 71b is connected to a multiplexer (not shown) of a downstream terminal (not shown) adjacent to the terminal 6b, and the second register 71b is connected to the multiplexer 72b in the own terminal 6b. It is connected to the first register 70a of the upstream terminal 6a adjacent to 6b. Further, the first register 70n of the terminal 6n is connected to the multiplexer 72n in the terminal 6n, and the second register 71n is connected to the multiplexer 72 in the terminal 6n.
n on the upstream side adjacent to this terminal 6n (n
-1) (not shown) is connected to the first register 60 (n-1) (not shown).

Next, data transmission of the downstream frame S50 and the upstream frame S51 will be described. First, as shown in FIG. 8 (a), the downstream frame S50 is transmitted from the main device 5 and has a crossover wire 7a between the main device 5 and the terminal 6a, a crossover wire 7b between the terminal 6a and the terminal 6b, and a terminal 6b. Terminal 6
The signal is transmitted to the final terminal 6n via a crossover wiring (not shown) between terminals downstream of b and a crossover wiring 7n between the terminal 6 (n-1) (not shown) and the final terminal 6n. The data of the downstream frame S50 is stored in each of the terminals 6a, 6
No processing is performed in b,..., 6n. If the terminal detection circuit 67 (see FIG. 6) detects that another terminal is connected to the downstream side from the own terminal, the terminal is relayed as it is.

On the other hand, the upstream frame S51 is shown in FIG.
As shown in the figure, the terminal 6n is transmitted from the final terminal 6n, the crossover wiring 7n between the final terminal 6n and the terminal 6 (n-1), and the terminal 6 (n
-1) and the crossover wiring 7 between the terminal 6 (n-2) (not shown)
(N-1) (not shown) and terminal 6 (n-2) and terminal 6
(N-2) via a crossover wiring between terminals on the upstream side,
The data is transmitted to the main device 5. During this time, each terminal 6a, 6b,
, 6n, first registers 70a, 7
, 70n, and the terminal having the transmission data has the second registers 71a, 71b,.
The transmission data stored in the n.
By switching at 2b,..., 72n, the destination address, source address, and control data in the upstream frame S51 are rewritten. In this case, rewriting of control data is possible only when another terminal is not rewriting, and the same terminal cannot rewrite continuously in the next cycle. When a time slot is assigned, video, audio, and other data are rewritten.

In the synchronous data transmission system configured as described above, transmission of the downstream frame S50 is performed as follows. That is, in the main device 5, the video data, the audio data, and the control data are loaded on the downstream frame S50 by the data shaping circuit 51 at the timing generated by the timing circuit 53, and are transmitted from the transceiver 54 to the terminal via the crossover wiring 7a. 6a.

In the terminal 6a, the data transmitted from the crossover wiring 7a is transmitted to the first transceiver 66a of the terminal 6a.
At the second transceiver 66
b to the terminal 6b via the crossover wiring 7b. Here, a synchronization signal is reproduced in a first synchronization reproduction circuit 68 from a reception signal received by the first transceiver 66a, and a timing circuit 65 is reproduced based on the reproduced synchronization signal.
To work. Further, in the data shaping circuit 63, only the data addressed to the terminal itself is extracted from the received signal received by the first transceiver 66a, the video data is sent to the video input / output interface circuit 61, and the audio data is sent to the audio input / output interface circuit. At 62, the control data is output to the control circuit 64, respectively. The video input / output interface circuit 61 outputs a video signal, and the audio input / output interface circuit 62 outputs an audio signal. Hereinafter, the same operation is performed from the terminal 6b to the final terminal 6n.

Next, transmission of the upstream frame S51 is performed as follows. That is, the final terminal 6n generates a timing in the timing circuit 65 based on the synchronization signal reproduced by the first synchronous reproduction circuit 68, thereby operating the data shaping circuit 63 to configure the upstream frame S51. . Then, the upstream frame S51 is transmitted from the first transceiver 66a and transmitted to the terminal 6 (n-1) via the crossover wiring 7n. At this time, if there is control data such as a destination address, a source address, and a control command, the control data is loaded on the upstream frame S51. If the time slot is allocated to the own terminal, the video data and the audio data are loaded on the upstream frame S51 similarly to the control data.

Here, in the terminal 6 (n-1), the timing is generated by the timing circuit 65 based on the synchronization signal received by the second transceiver 66b and reproduced by the second synchronization reproduction circuit 69. In the data shaping circuit 63, the upstream frame S51 is formed, and the first transceiver 66a
The signal is output to the crossover wiring 7 (n-2). At this time, if there is control data, it is put on the upstream frame S51. If there is no write data, the data is output from the first transceiver 66a to the crossover wiring 7 (n-2) as it is. Hereinafter, the same operation is performed from the terminal 6 (n−2) to the main device 5. In the main unit 5, the video data,
Only the audio data is looped back and placed on the downstream frame S50.

[0017]

However, in such a conventional data transmission system, a synchronizing signal such as video and audio is transmitted using a frame period for synchronizing the main unit and each terminal. In order to handle a synchronization signal with a long cycle or a plurality of synchronization signals, a method such as frequency division has been adopted, but in this case, which part is the start point of synchronization Is difficult to determine.

The present invention has been made in order to solve such a problem. An area for storing synchronization data is provided in a frame, and the synchronization signal is transmitted as data. It is an object of the present invention to provide a synchronous data transmission method capable of transmitting data at the same time.

[0019]

In order to achieve the above object, a synchronous data transmission system according to the present invention uses digitized video, audio, and other periodic data together with a data synchronization signal and a frame synchronization signal. This is a synchronous data transmission system that transmits and receives between terminals via the main unit in a time-division multiplexing manner and requires a synchronization signal for reproduction when receiving at the terminal. (A) The time-divided downlink frame from the main unit is sequentially relay-transmitted to the terminal at a fixed period, and each terminal reproduces the frame synchronization signal from the received time-divided downlink frame, thereby converting the data of the downlink frame. (B) relay the terminal from the last terminal that has received the downstream frame to the main unit in order from the terminal to the main unit, and each terminal once captures the upstream frame and If the time slot is assigned to the own terminal, the data of the own terminal is inserted into the upstream frame and transmitted, and the main apparatus that receives the upstream frame transmitted in step (b) executes step (a), The upstream and downstream frames are configured by prefixing the data with a preamble for generating a frame synchronization signal within a certain period, and together with the aggregate data having a period that is an integral multiple of the period of the frame synchronization signal in the data. By providing a time slot for synchronization information for converting the data synchronization signal into data for time division transmission, a plurality of data synchronization signals different from the cycle of the frame synchronization signal can be transmitted.

According to the synchronous data transmission system of the present invention,
Synchronous signals such as video and audio are transmitted in a frame with a fixed period, replaced by data called synchronization information in downstream frames, and the playback side extracts necessary synchronization data from the received synchronization information and , A plurality of data synchronization signals can be transmitted simultaneously at a time.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment to which a synchronous data transmission system according to the present invention is applied will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the synchronous data transmission system according to the present invention. In FIG. 1, a synchronous data transmission system according to the present invention includes a main device 1 for controlling exchange of signals and data such as video and audio, and
Terminals 2a, 2b,... For inputting and outputting signals such as voices
2n, the main device 1 and the terminals 2a, 2b,.
.., 2n are mutually connected via the crossover wirings 3a, 3b,..., 3n.

FIG. 2 is a block diagram showing a main unit and a terminal in the synchronous data transmission system according to the present invention. In FIG. 1, a main device 1 includes a data shaping circuit 11 for assembling and separating frames to be described later, and a data shaping circuit 11.
, 2n, a control circuit 12 for transmitting operation commands to each terminal 2a, 2b,..., 2n, a timing circuit 13 for generating operation timing of each section, a transceiver 14 for transmitting and receiving data, and a final terminal 2n. And a synchronous reproduction circuit 15 for reproducing a synchronous signal.

The data shaping circuit 11 of the main device 1 is connected to a control circuit 12, a timing circuit 13 and a transceiver 14, and a synchronous reproduction circuit 15 is connected between the data shaping circuit 11 and the transceiver 14.
Are connected to the control circuit 12 via the timing circuit 13.

The terminals 2a, 2b,..., 2n are provided with a video interface circuit 21 for inputting and outputting video signals, and an audio interface circuit 22 for inputting and outputting audio signals.
A data shaping circuit 23 for assembling and separating frames to be described later; a control circuit 24 for sending control commands to the data shaping circuit 23 and the main device 1; a timing circuit 25 for generating operation timing of each unit; First and second transceivers 26a and 26b for performing the operation, a terminal detection circuit 27 for detecting whether or not the terminal is connected downstream from the own terminal, and a first for reproducing a synchronization signal sent from the main device 1. It comprises a synchronous reproducing circuit 28 and a second synchronous reproducing circuit 29 for reproducing a synchronous signal sent from the last terminal 2n.

The data shaping circuits 23 of the terminals 2a, 2b,..., 2n include a video interface circuit 21, an audio interface circuit 22, a control circuit 24, a timing circuit 25, and first and second transceivers 26a, 26b.
, And the first transceiver 26a is connected to the timing circuit 25 via the first synchronous reproduction circuit 28,
The timing circuit 25 includes a video interface circuit 21, an audio interface circuit 22, and a control circuit 2.
4 is connected. Also, the second transceiver 26b
Are connected to a terminal detection circuit 27 and a second synchronous reproduction circuit 29, and the terminal detection circuit 27 is connected to the control circuit 24, and the second synchronous reproduction circuit 29 is connected to the timing circuit 29, respectively.

FIG. 3 is a timing chart showing the structure of a frame in the synchronous data transmission system of the present invention. In the figure, the downstream frame S10 is the main device 1
(See FIG. 1) to terminals 2a, 2b,.
), And transmitted in the upstream frame S11.
Are signals transmitted from the terminals 2a, 2b,..., 2n to the main device 1.

The down frame S10 and the up frame S
11 is composed of a preamble, a start flag, data, an end flag, and an idle.
Both are always constant. Also, the downstream frame S10
And the data S16 of the upstream frame S11 include synchronization information S17, transmission destination address, transmission source address, control command, first and second video data 1, 2, first and second audio data 1, 2. Other data and C
And RC. Here, the downstream frame S10
The preamble S18 for generating frame synchronization signals S19a and S19b (see FIG. 2) within a fixed period T is both arranged in the data S16 of the upstream frame S11.

The synchronization information S17 is composed of first and second video data synchronization signals S17a and S17b and first and second audio data synchronization signals S17c and S17d. S17d is converted into data, and is inserted into the time slot S20 of the synchronization information S17 for time division transmission provided in the data together with the aggregate data (data constituting the downstream frame S10 and the upstream frame S11). Here, the aggregate data has a cycle T that is an integral multiple (three in the embodiment of FIG. 3) of the cycle T of the frame synchronization signals S19a and S19b.

FIG. 4A is a schematic diagram of data transmission in the synchronous data transmission system of the present invention, and FIG.
FIG. 2 shows a block diagram of a data shaping circuit in FIG. In these figures, each terminal 2a, 2b,.
2n, the data shaping circuit 23 includes first registers 30a, 30b,.
, 31n, and a multiplexer 32
, 32b,..., 32n. here,
The first registers 30a, 30b,..., 30n have a function of sequentially transmitting the upstream frame S11 from the last terminal 2n that has received the downstream frame S10 to the main device 1 by relaying the terminals, and the second register 30a. 31a, 31b,...
31n has a function of temporarily taking in the upstream frame S11, inserting the own terminal data into the upstream frame S11 and transmitting the data, and furthermore, multiplexers 32a, 32b,.
32n has a function of transmitting the upstream frame S11 by switching the first and second registers.

The first register 30a of the terminal 2a is connected to the multiplexer 32a in the terminal 2a and the multiplexer 32b of the terminal 2b on the downstream side adjacent to the terminal 2a. It is connected to the main device 1 via a multiplexer 32a in 2a.
Also, the first register 30b of the terminal 2b stores
Of the terminal 2b and a multiplexer (not shown) of a downstream terminal (not shown) adjacent to the terminal 2b. The second register 31b is connected to the multiplexer 32b in the terminal 2b by itself. It is connected to the first register 30a of the terminal 2a on the upstream side adjacent to the terminal 2b. Further, the first register 30n of the terminal 2n is connected to the multiplexer 32n in the terminal 2n, and the second register 31n is connected to the multiplexer 32 in the terminal 2n.
n, the upstream terminal 2 (n
-1) (not shown) is connected to the first register 20 (n-1) (not shown).

Next, data transmission of the downstream frame S10 and the upstream frame S11 will be described. First, as shown in FIG. 4 (a), the downstream frame S10 is transmitted from the main device 1 and has a crossover wire 3a between the main device 1 and the terminal 2a, a crossover wire 3b between the terminal 2a and the terminal 2b, and a terminal 2b. Crossover wiring (not shown) between terminals (not shown) downstream of terminal 2b, terminal 2 (n-1) (not shown), and final terminal 2
It is transmitted to the final terminal 2n via the crossover wiring 3n between n. Note that the data of the downstream frame S10 is not processed in each of the terminals 2a, 2b,..., 2n, and that a terminal other than the own terminal 2a is connected downstream by the terminal detection circuit 27. If detected, it is relayed as it is.

On the other hand, the upstream frame S11 is shown in FIG.
As shown in the figure, the terminal 2n is transmitted from the final terminal 2n, the crossover wiring 3n between the final terminal 2n and the terminal 2 (n-1), and the terminal 2 (n
-1) and the crossover wiring 3 between the terminal 2 (n-2) (not shown)
(N-1) (not shown) and terminal 2 (n-2) and terminal 2
(N-2) via a crossover wiring between terminals on the upstream side,
The data is transmitted to the main device 1. During this time, each terminal 2a, 2b,
.., 2n, first registers 30a, 3
0b,..., 30n, and there are transmission data in the terminals, the second registers 31a, 31b,.
The transmission data stored in n
By switching at 2b,..., 32n, the destination address, source address, and control data in the upstream frame S11 are rewritten. In this case, rewriting of control data is possible only when another terminal is not rewriting, and the same terminal cannot rewrite continuously in the next cycle. When a time slot is assigned, video, audio, and other data are rewritten.

In the synchronous data transmission system of the present invention thus configured, the transmission of the downstream frame S10 is performed as follows. That is, in the main device 1, periodic data S12a and S14a, such as folded digital video and audio, are converted into data synchronization signals S13a and S13a.
At the timing created by the timing circuit 13 together with 15a and the frame synchronization signal S19a, the data shaping circuit 11 puts it on the downstream frame S10 and transmits it from the transceiver 14 to the terminal 2a via the crossover wiring 3a.

In the terminal 2a, the data transmitted from the crossover wiring 3a is transmitted to the first transceiver 26a of the terminal 2a.
At the second transceiver 26
b to the terminal 2b via the crossover wiring 3b. Here, a synchronization signal is reproduced in a first synchronization reproduction circuit 28 from a reception signal received by the first transceiver 26a, and a timing circuit 25 is reproduced based on the reproduced synchronization signal.
To work. Further, the data shaping circuit 23 extracts only data addressed to the terminal itself from the received signal received by the transceiver 26a, and converts the video data S12a and the video synchronization signal S13a into the video data and the synchronization information S1.
7 from the time slot S20, and the audio data S1 to the video input / output interface circuit 21.
4a and the audio synchronization signal S15a are respectively extracted from the time slot S20 of the audio data and the synchronization information S17, and are output to the audio input / output interface circuit 22 and the control data are output to the control circuit 24, respectively. Then, the video input / output interface circuit 21 outputs a video signal, and the audio input / output interface circuit 22 outputs an audio signal. Hereinafter, the same operation is performed from the terminal 2b to the last terminal 2n.

Next, transmission of the upstream frame S11 is performed as follows. That is, the final terminal 2n generates timing in the timing circuit 25 based on the synchronization signal reproduced in the first synchronous reproduction circuit 28, thereby operating the data shaping circuit 23 to configure the upstream frame S11. . Then, the upstream frame S11 is transmitted from the first transceiver 26a, and transmitted to the terminal 2 (n-1) via the crossover wiring 3n. At this time, if there is control data such as a transmission destination address, a transmission source address, and a control command, the control data is placed in an upstream frame. For the video and audio data, if the time slot is allocated to the terminal itself, the video data S12b and the video synchronization signal S13b are received from the video interface circuit 21, and the video data S14b and the video synchronization signal are received from the audio interface circuit 22. The signal S15b is received, inserted into each time slot of video data, audio data, and synchronization information, and put on an upstream frame in the same manner as control data.

On the other hand, in the terminal 2 (n-1), the timing is generated by the timing circuit 25 based on the synchronization signal received by the second transceiver 26b and reproduced by the second synchronization reproduction circuit 29, In the shaping circuit 23, the upstream frame S11 is formed, and the first transceiver 26a
The signal is output to the crossover wiring 3 (n-2). At this time, if there is control data, it is put on the upstream frame. If there is no write data, the first transceiver 26a
The signal is output to the crossover wiring 3 (n−2). Hereinafter, terminal 2
The same operation is performed from (n−2) to the main device 1.
In the main apparatus 1, only the video data and the audio data are looped back and put on the downstream frame S10.

[0038]

As is apparent from the above description, according to the synchronous data transmission system of the present invention, a synchronous signal such as video and audio is transmitted in a frame having a constant period, and is referred to as synchronous information in a downstream frame. The data is transmitted by replacing it with the data. On the reproduction side, necessary synchronization data is extracted from the received synchronization information and can be converted into a synchronization signal such as video and audio, so that a plurality of data synchronization signals can be transmitted simultaneously at a time. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of a synchronous data transmission system according to the present invention.

FIG. 2 is a block diagram of a main device and a terminal in the synchronous data transmission system of the present invention.

FIG. 3 shows an uplink in the synchronous data transmission system of the present invention;
6 is a timing chart showing a configuration of a downlink frame.

FIG. 4A is a schematic diagram of a synchronous data transmission system of the present invention, and FIG. 4B is a block diagram of a data shaping circuit in the synchronous data transmission system of the present invention.

FIG. 5 is a block diagram showing an overall configuration in a conventional synchronous data transmission system.

FIG. 6 is a block diagram of a main device and a terminal in a conventional synchronous data transmission method.

FIG. 7 is a timing chart showing a configuration of an upstream frame and a downstream frame in conventional synchronous data transmission.

8A is a schematic diagram of a conventional synchronous data transmission system, and FIG. 8B is a block diagram of a data shaping circuit in the conventional synchronous data transmission system.

[Explanation of symbols]

 1 Main device 2a, 2b, 2n Terminal 3a, 3b, 3n Crossover wiring S10・ ・ ・ ・ ・ ・ ・ ・ ・ Down frame S11 ・ ・ ・ ・ ・ ・ Up frame S12a, S12b ・ ・ ・ ・ ・ ・ Video data S13a, S13b ・ ・ ・ ・ ・ ・ Video synchronization signal S14a , S14b Voice data S15a, S15b Voice synchronization signal S16 Time slot S17a to S17d Data synchronization signal S18 Preamble

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C020 AA02 AA07 AA09 BA09 5K028 AA11 CC02 CC05 CC06 EE03 EE05 EE07 KK01 KK22 LL12 MM04 MM12 MM16 NN01 RR02 SS02 SS12 5K047 AA01 BB05 CC02 DD01 DD12 HH01 MMH

Claims (1)

[Claims] 1. Data having periodicity such as digitized video and audio (S12a, S12b, S14a, S14
b) with the data synchronization signals (S13a, S13b, S15).
a, S15b), a frame synchronization signal (S19a, S19)
b) together with the terminals (2a, 2b,...) via the main device (1).
.. 2n) is a synchronous data transmission system in which transmission and reception are performed in a time-division multiplexing manner and a synchronization signal for reproduction is required when receiving at the terminal, and a crossover wiring between the main device and the terminal (3a, 3b, ...
3n), and (a) a time-divided downstream frame (S1
0) is sequentially relayed to the terminal at a fixed period (T), and the data of the downlink frame is reproduced by reproducing the frame synchronization signal from the time-divided downlink frame received at each terminal, (b) From the last terminal (2n) that has received the downstream frame, the upstream frame (S11) is relayed and transmitted to the main unit in sequence through the terminals, and each terminal fetches the upstream frame once, and receives a time slot (S1) in the upstream frame.
If (6) is assigned to the own terminal, the data of the own terminal is inserted into the upstream frame and transmitted, and the main device that has received the upstream frame transmitted in step (b) executes step (a) The upstream and downstream frames are configured by preceding the data with a preamble (S18) for generating the frame synchronization signal within the fixed period. On the other hand, by providing a time slot (S20) of synchronization information (S17) for converting the data synchronization signals (S17a to S17d) into data and transmitting the data in a time-division manner together with the aggregated data having an integral multiple cycle, A synchronous data transmission method, wherein a plurality of data synchronization signals different from the signal period can be transmitted.