JP2001284769A - Circuit-pattern formation method and wiring board formed thereby - Google Patents

Circuit-pattern formation method and wiring board formed thereby

Info

Publication number
JP2001284769A
JP2001284769A JP2000091728A JP2000091728A JP2001284769A JP 2001284769 A JP2001284769 A JP 2001284769A JP 2000091728 A JP2000091728 A JP 2000091728A JP 2000091728 A JP2000091728 A JP 2000091728A JP 2001284769 A JP2001284769 A JP 2001284769A
Authority
JP
Japan
Prior art keywords
circuit
powder
forming
chargeable
circuit pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000091728A
Other languages
Japanese (ja)
Other versions
JP4543490B2 (en
Inventor
Akihiko Kamata
明彦 鎌田
Takayuki Hamanaka
孝之 浜中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2000091728A priority Critical patent/JP4543490B2/en
Publication of JP2001284769A publication Critical patent/JP2001284769A/en
Application granted granted Critical
Publication of JP4543490B2 publication Critical patent/JP4543490B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a circuit-pattern formation method in which the resolution of a circuit pattern formed by an electrophotographic method is high and in which the circuit pattern displays a good electric characteristic, and to provide a wiring board which is formed by the method. SOLUTION: The circuit-pattern formation method is constituted of a charging process in which the surface of a photoreceptor 12 is charged by a corona charger 11. The formation method is constituted of an exposure process in which the surface of the photoreceptor 12 is irradiated with a laser beam 13 so as to form a latent-image pattern. The formation method is constituted of a developing process in which a chargeable powder 15 for circuit formation is electrostatically attracted to the latent-image pattern on the surface of the photoreceptor 12 by a feed means 14. The formation method is constituted of a transfer process in which the chargeable powder 15 for circuit formation developed on the latent-image pattern is transferred onto a ceramic green sheet 16. The formation method is constituted of a fixing process in which the chargeable powder 15 for circuit formation transferred onto the green sheet 16 is fixed, and in which the circuit pattern is formed on the green sheet 16.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、回路パターン形成
方法及びそれによって形成された配線基板に関し、特に
セラミックグリーンシート上に回路パターンを形成する
にあたって電子写真法により印刷を行なう回路パターン
形成方法及びそれによって形成された配線基板に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a circuit pattern and a wiring board formed by the method, and more particularly, to a method for forming a circuit pattern on a ceramic green sheet by electrophotographic printing and a method for forming the circuit pattern. And a wiring board formed by the method.

【0002】[0002]

【従来の技術】静電力を利用して回路形成用荷電性粉末
を誘電体層上に所望の回路パターンとして形成する回路
パターン形成方法と、この回路パターン形成方法に使用
される回路形成用荷電性粉末とが、例えば、特開平4−
236484号公報に開示されている。回路形成用荷電
性粉末(帯電性粒子)は、導電性金属粉末(金属粉末)
と荷電制御剤とを熱可塑性樹脂(熱溶融性樹脂)中に均
一分散させた構造をなし、その平均粒径は10〜15μ
mである。そして、具体的な回路形成用荷電性粉末の製
造方法としては、まず、導電性金属粉末である平均粒径
が0.4μmのフレーク形状の銀粉末、熱可塑性樹脂で
あるスチレンアクリル共重合体及び荷電制御剤であるア
ゾ系金属染料をそれぞれ80:19:1の重量比で混合
し、これをニーダにより熱溶融混練する。その後、カッ
ターミルによる粗粉砕、ジェットミルによる微粉砕、及
び気流式分級を行うものである。
2. Description of the Related Art A circuit pattern forming method for forming a circuit forming chargeable powder on a dielectric layer as a desired circuit pattern using electrostatic force, and a circuit forming chargeability used in the circuit pattern forming method. The powder is, for example, disclosed in
No. 236,484. Chargeable powder for circuit formation (chargeable particles) is conductive metal powder (metal powder)
And a charge controlling agent are uniformly dispersed in a thermoplastic resin (heat-meltable resin), and the average particle size is 10 to 15 μm.
m. Then, as a specific method for producing a chargeable powder for forming a circuit, first, a flake-shaped silver powder having an average particle size of 0.4 μm as a conductive metal powder, a styrene-acryl copolymer as a thermoplastic resin, and The azo-based metal dyes serving as charge control agents are mixed at a weight ratio of 80: 19: 1, respectively, and the resulting mixture is kneaded by hot melt. Thereafter, coarse pulverization by a cutter mill, fine pulverization by a jet mill, and air flow classification are performed.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
回路形成用荷電性粉末は、導電性金属粉末、熱可塑性樹
脂、荷電制御剤の含有率が80:19:1〜90:9:
1であるため、回路形成用荷電性粉末の比重が3〜5g
/cm3にもなり、通常のOA用荷電性粉末と比較して
3倍以上の値となっている。しかも、熱可塑性樹脂の含
有量が少ないため、帯電量の制御が極めて困難である。
したがって、電子写真法によってセラミックグリーンシ
ート上に回路パターンを印刷する場合に従来の回路形成
用荷電性粉末を使用すると、回路形成用荷電性粉末とキ
ャリアとの間の静電引力のみでは現像スリーブ回転時に
キャリア表面に回路形成用荷電性粉末を保持しきれず、
回路形成用荷電性粉末が飛散してしまい回路パターンの
乱れを引き起こすといった問題があった。
However, the conventional chargeable powder for forming a circuit has a content of a conductive metal powder, a thermoplastic resin and a charge control agent of 80: 19: 1 to 90: 9:
1, the specific gravity of the chargeable powder for forming a circuit is 3 to 5 g.
/ Cm 3, which is three times or more the value of a normal chargeable powder for OA. In addition, since the content of the thermoplastic resin is small, it is extremely difficult to control the charge amount.
Therefore, when a conventional chargeable powder for forming a circuit is used when a circuit pattern is printed on a ceramic green sheet by electrophotography, the rotation of the developing sleeve is caused only by the electrostatic attraction between the chargeable powder for forming a circuit and the carrier. Sometimes the charged powder for circuit formation cannot be held on the carrier surface,
There has been a problem that the chargeable powder for forming a circuit is scattered and a circuit pattern is disturbed.

【0004】この対策としては、回路形成用荷電性粉末
の質量を低減させることが挙げられる。その1つの方法
として、回路形成用荷電性粉末を小粒径化して回路形成
用荷電性粉末の質量を低減する方法がある。しかし、通
常用いられる回路形成用荷電性粉末は、粒径が5〜10
μm程度であり、これ以上粒径を小さくすると、ファン
デルワールス力の寄与率が高くなり、静電気力でのコン
トロールが困難となる。その結果、これ以上の小粒径化
した回路形成用荷電性粉末では、カブリのない高解像度
の回路パターンを形成することが困難である。
[0004] As a countermeasure, there is a measure to reduce the mass of the chargeable powder for forming a circuit. As one of the methods, there is a method of reducing the particle size of the chargeable powder for circuit formation to reduce the mass of the chargeable powder for circuit formation. However, the commonly used chargeable powder for circuit formation has a particle size of 5-10.
When the particle size is smaller than about μm, the contribution rate of Van der Waals force increases, and it is difficult to control the electrostatic force. As a result, it is difficult to form a high-resolution circuit pattern without fog with a circuit-forming chargeable powder having a smaller particle size.

【0005】また、他の方法として、導電性金属粉末の
含有率を下げ、または熱可塑性樹脂の含有率を上げて回
路形成用荷電性粉末の質量を低減する方法がある。同一
粒径のまま熱可塑性樹脂の含有率を上げると、回路形成
用荷電性粉末の質量を低減できる上に回路形成用荷電性
粉末の帯電量も向上できるため、回路形成用荷電性粉末
の飛散は防止できる。しかし、その回路形成用荷電性粉
末では導電性金属粉末の粒径が小さくなり、熱可塑性樹
脂からなる被膜の膜厚が厚くなってしまう。つまり、セ
ラミックグリーンシートを焼成する際に熱可塑性樹脂が
分解すると導電性金属粉末間の距離が長くなってしまい
良好な電気抵抗を有する回路パターンを形成することが
困難である。
As another method, there is a method of reducing the content of the conductive metal powder or increasing the content of the thermoplastic resin to reduce the mass of the chargeable powder for forming a circuit. Increasing the content of the thermoplastic resin while maintaining the same particle size can reduce the mass of the chargeable powder for forming a circuit and also increase the charge amount of the chargeable powder for forming a circuit, so that the chargeable powder for forming a circuit is scattered. Can be prevented. However, in the chargeable powder for forming a circuit, the particle diameter of the conductive metal powder becomes small, and the film thickness of the thermoplastic resin becomes thick. In other words, when the thermoplastic resin is decomposed when the ceramic green sheet is fired, the distance between the conductive metal powders becomes long, and it is difficult to form a circuit pattern having good electric resistance.

【0006】本発明は、このような問題点を解消するた
めになされたものであり、電子写真法によって形成され
た回路パターンが高解像度で、かつ良好な電気特性を示
す回路パターン形成方法及びそれによって形成された配
線基板を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve such problems, and a circuit pattern forming method in which a circuit pattern formed by electrophotography has high resolution and good electrical characteristics, and a method thereof. It is an object to provide a wiring board formed by the method.

【0007】[0007]

【課題を解決するための手段】上述する問題点を解決す
るため、本発明の回路パターン形成方法は、感光体の表
面を帯電する帯電工程と、前記感光体に静電的な潜像パ
ターンを形成する露光工程と、前記潜像パターン上へ回
路形成用荷電性粉末を静電力により付着させる現像工程
と、前記潜像パターン上の前記回路形成用荷電性粉末を
前記セラミックグリーンシート上へ転写する転写工程
と、前記セラミックグリーンシート上へ転写された前記
回路形成用荷電性粉末を定着させる定着工程とを含む電
子写真法を用いて、前記セラミックグリーンシート上に
回路パターンを形成する回路パターン形成方法であっ
て、前記回路形成用荷電性粉末が、中空または複数の微
小孔を有する導電性金属粉末あるいは導電性金属酸化物
粉末の外周に熱可塑性樹脂を被覆したものであることを
特徴とする。
In order to solve the above-mentioned problems, a circuit pattern forming method according to the present invention comprises a charging step of charging a surface of a photoreceptor, and an electrostatic latent image pattern formed on the photoreceptor. An exposing step of forming, a developing step of electrostatically attaching the chargeable powder for circuit formation onto the latent image pattern, and transferring the chargeable powder for circuit formation on the latent image pattern onto the ceramic green sheet A circuit pattern forming method for forming a circuit pattern on the ceramic green sheet by using an electrophotographic method including a transfer step and a fixing step of fixing the chargeable powder for circuit formation transferred to the ceramic green sheet. Wherein the chargeable powder for forming a circuit is formed of a thermoplastic metal on the outer periphery of a conductive metal powder or a conductive metal oxide powder having a hollow or a plurality of micropores. Characterized in that it is obtained by coating the fat.

【0008】また、本発明の回路パターン形成方法は、
前記導電性金属粉末あるいは導電性金属酸化物粉末は、
見掛け比重が真比重の60〜90%の範囲であることを
特徴とする。
Further, the method for forming a circuit pattern according to the present invention comprises:
The conductive metal powder or conductive metal oxide powder,
The apparent specific gravity is in the range of 60 to 90% of the true specific gravity.

【0009】本発明の配線基板は、上述の回路パターン
形成方法によって、前記回路パターンが印刷された前記
セラミックグリーンシートを焼成して構成することを特
徴とする。
A wiring board according to the present invention is characterized in that the ceramic green sheet on which the circuit pattern is printed is fired by the circuit pattern forming method described above.

【0010】また、本発明の配線基板は、上述の回路パ
ターン形成方法によって、前記回路パターンが印刷され
た前記セラミックグリーンシートを積層し、焼成して構
成することを特徴とする。
Further, the wiring substrate of the present invention is characterized in that the ceramic green sheets on which the circuit patterns are printed are laminated and fired by the above-described circuit pattern forming method.

【0011】本発明の回路パターン形成方法によれば、
中空または複数の微小孔を有する導電性金属粉末あるい
は導電性金属酸化物粉末の外周に熱可塑性樹脂を被覆し
た回路形成用荷電性粉末を用いているため、導電性金属
粉末あるいは導電性金属酸化物粉末の粒径を変えること
なく回路形成用荷電性粉末の質量を低減することがで
き、その結果、回路形成用荷電性粉末の飛散を抑えたカ
ブリのない高解像度で、かつ良好な電気抵抗を示す回路
パターンを形成することができる。
According to the circuit pattern forming method of the present invention,
Uses conductive metal powder or conductive metal oxide because it uses a conductive metal powder or a conductive metal oxide powder with a hollow or multiple micropores and a conductive resin-coated chargeable powder for forming a circuit. The mass of the chargeable powder for circuit formation can be reduced without changing the particle size of the powder. The circuit pattern shown can be formed.

【0012】本発明の配線基板によれば、中空または複
数の微小孔を有する導電性金属粉末あるいは導電性金属
酸化物粉末の外周に熱可塑性樹脂を被覆した回路形成用
荷電性粉末を用いて、電子写真法によって回路パターン
をセラミックグリーンシートに印刷し、その後、それら
のセラミックグリーンシートを焼成して配線基板を形成
するため、高解像度で、かつ良好な電気抵抗の回路パタ
ーンを備えた配線基板を得ることが可能となる。
According to the wiring substrate of the present invention, a conductive metal powder or a conductive metal oxide powder having a hollow or a plurality of fine holes is coated with a thermoplastic resin on the outer periphery thereof using a chargeable powder for forming a circuit. The circuit pattern is printed on ceramic green sheets by electrophotography, and then the ceramic green sheets are fired to form a wiring board, so that a wiring board having a circuit pattern with high resolution and good electric resistance is formed. It is possible to obtain.

【0013】[0013]

【発明の実施の形態】以下、図面を参照して本発明の実
施例を説明する。図1は、本発明の回路パターン形成方
法に係る一実施例に用いる電子写真システムの構成図で
ある。セラミックグリーンシート上の回路パターン形成
方法は、コロナ帯電器11により感光体12の表面を帯
電する帯電工程、感光体12の表面にレーザ光13を照
射して所望の潜像パターン(図示せず)を形成する露光
工程、供給手段14により回路形成用荷電性粉末15を
感光体12の表面の潜像パターンに静電吸着させる現像
工程、セラミックグリーンシート16の背面から転写器
17により、セラミックグリーンシート16に回路形成
用荷電性粉末15と逆極性の電荷を与え、潜像パターン
上に現像された回路形成用荷電性粉末15をセラミック
グリーンシート16上へ転写する転写工程、フラッシュ
ランプ18の照射によりセラミックグリーンシート16
上に転写された回路形成用荷電性粉末15を定着させ、
セラミックグリーンシート16上に回路パターン(図示
せず)を形成する定着工程で構成される。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of an electrophotographic system used in an embodiment according to a circuit pattern forming method of the present invention. The circuit pattern forming method on the ceramic green sheet includes a charging step of charging the surface of the photoreceptor 12 by the corona charger 11, and irradiating the surface of the photoreceptor 12 with a laser beam 13 to obtain a desired latent image pattern (not shown). An exposure process for forming a toner image; a developing process for electrostatically adsorbing the chargeable circuit-forming powder 15 to the latent image pattern on the surface of the photoreceptor 12 by the supply means 14; A transfer step of giving a charge having a polarity opposite to that of the chargeable powder for circuit formation 15 to 16 and transferring the chargeable powder for circuit formation 15 developed on the latent image pattern onto the ceramic green sheet 16, by irradiation with a flash lamp 18 Ceramic green sheet 16
Fixing the chargeable powder 15 for circuit formation transferred onto the
The fixing step includes forming a circuit pattern (not shown) on the ceramic green sheet 16.

【0014】図2は、図1の回路パターン形成方法に用
いられる回路形成用荷電性粉末の断面図である。回路形
成用荷電性粉末15は、球状の導電性金属粉末21の外
周に、荷電制御剤22を固着させた後、熱可塑性樹脂2
3を被覆した構造をなしている。 [試料1]導電性金属粉末である真比重8.96g/c
3、平均粒径5.5μmの中空あるいは微小孔を有し
ていない従来の銅粉末、熱可塑性樹脂である比重1.1
g/cm3のスチレンアクリル系樹脂、及び荷電制御剤
であるアゾ系含金属錯体をそれぞれ90:10:0.1
の重量比で混合し、ハイブリダイゼーションに投入し4
000rpmで1分間処理した。その後、外添剤となる
シリカを付着させて、0.7μmの樹脂層厚を有する粒
径6.9μmの回路形成用荷電性粉末を得た。 [試料2〜9]真比重は8.96g/cm3と変わらな
いが、見掛け比重及び平均粒径が異なる中空を有する導
電性金属粉末である銅粉末、あるいは複数の微小孔を有
する導電性金属酸化物粉末である酸化銅粉末、及び熱可
塑性樹脂である比重1.1g/cm3のスチレンアクリ
ル系樹脂をそれぞれ表1の重量比で混合し、試料1と同
様の方法により、試料2〜6の回路形成用荷電性粉末を
得た。
FIG. 2 is a sectional view of a chargeable powder for forming a circuit used in the method of forming a circuit pattern of FIG. After the charge controlling agent 22 is fixed to the outer periphery of the spherical conductive metal powder 21, the circuit forming chargeable powder 15 is
3 is covered. [Sample 1] True specific gravity of conductive metal powder: 8.96 g / c
m 3 , a conventional copper powder having no hollow or micropores having an average particle size of 5.5 μm and a specific gravity of 1.1 which is a thermoplastic resin.
g / cm 3 of a styrene-acrylic resin and 90: 10: 0.1 of an azo metal-containing complex as a charge control agent, respectively.
And mixed for weight ratio of 4
The treatment was performed at 000 rpm for 1 minute. Thereafter, silica as an external additive was adhered to obtain a chargeable powder for circuit formation having a resin layer thickness of 0.7 μm and a particle size of 6.9 μm. [Samples 2 to 9] Although the true specific gravity remains unchanged at 8.96 g / cm 3 , copper powder which is a conductive metal powder having a hollow having different apparent specific gravity and average particle size, or a conductive metal having a plurality of micropores A copper oxide powder as an oxide powder and a styrene acrylic resin having a specific gravity of 1.1 g / cm 3 as a thermoplastic resin were mixed at a weight ratio shown in Table 1, and samples 2 to 6 were prepared in the same manner as in sample 1. Was obtained.

【0015】また、試料1よりも粒径の大きな酸化銅粉
末を用いた試料7、銅粉末は試料1と同じであるが、熱
可塑性樹脂の含有量を増大させた回路形成用荷電性粉末
の粒径の大きな試料8、及び試料1よりも粒径の小さな
銅粒子を用いて導電性金属の含有率を減少させた回路形
成用荷電性粉末の粒径の同じ試料9についても、試料1
と同様の方法により形成した。
Sample 7 using copper oxide powder having a larger particle size than Sample 1 has the same copper powder as Sample 1, except that the content of the thermoplastic resin is increased. The sample 8 having a large particle size and the sample 9 having the same particle size as the chargeable powder for forming a circuit in which the content of the conductive metal was reduced by using copper particles having a smaller particle size than the sample 1 were also used.
It was formed by the same method as described above.

【0016】なお、本実施例の見掛け比重とは、水銀ポ
ロシメータ(島津製作所社製)等の中空部分及び微小孔
を検出しない体積測定法による粉末の密度であり、真比
重とは、その中空部分及び微小孔を除外したその物質固
有の値である。
The apparent specific gravity in this embodiment is the density of a powder by a volume measurement method that does not detect a hollow portion such as a mercury porosimeter (manufactured by Shimadzu Corporation) or the like, and the true specific gravity is the hollow portion. And a value peculiar to the substance excluding micropores.

【0017】[0017]

【表1】 [Table 1]

【0018】次いで、これらの試料1〜9の回路形成用
荷電性粉末を用いて、図1に示した電子写真法により回
路パターンを印刷したセラミックグリーンシートを還元
雰囲気中で1000℃の加熱をし、セラミックグリーン
シートおよび回路パターンを焼結してセラミック基板上
に回路パターンを形成した。
Next, using the chargeable powder for circuit formation of each of the samples 1 to 9, the ceramic green sheet on which the circuit pattern was printed by the electrophotographic method shown in FIG. 1 was heated at 1000 ° C. in a reducing atmosphere. Then, the ceramic green sheet and the circuit pattern were sintered to form a circuit pattern on the ceramic substrate.

【0019】そして、上述の試料1〜9の回路形成用荷
電性粉末を用いた各回路パターンについて、印刷工程の
後、セラミックグリーンシート上における回路形成用荷
電性粉末の飛散の有無を観察し、また、焼結後のセラミ
ック基板上の回路パターンについてシート抵抗を測定し
た。その結果を表2に示す。
Then, for each circuit pattern using the chargeable powder for circuit formation of the above-mentioned samples 1 to 9, after the printing process, the presence or absence of scattering of the chargeable powder for circuit formation on the ceramic green sheet was observed. Further, the sheet resistance of the circuit pattern on the sintered ceramic substrate was measured. Table 2 shows the results.

【0020】[0020]

【表2】 [Table 2]

【0021】表2から明らかなように、従来の回路形成
用荷電性粉末である試料1では、回路形成用荷電性粉末
の飛散が生じているが、本発明の回路形成用荷電性粉末
である試料2〜5では、真比重は変わらないが見掛け比
重を変化させた銅粉末または酸化銅粉末を用いることに
より、回路形成用荷電性粉末の飛散を無くすことがで
き、さらに、これらの回路形成用荷電性粉末を用いた回
路パターンのシート抵抗は良好なものであった。
As is apparent from Table 2, in the sample 1 which is a conventional chargeable powder for forming a circuit, the chargeable powder for forming a circuit is scattered, but the chargeable powder for forming a circuit according to the present invention is used. In Samples 2 to 5, the use of copper powder or copper oxide powder whose true specific gravity does not change but whose apparent specific gravity is changed makes it possible to eliminate the scattering of the chargeable powder for forming a circuit. The sheet resistance of the circuit pattern using the chargeable powder was good.

【0022】しかしながら、見掛け比重を低減しすぎた
場合、すなわち、見掛け比重/真比重の値が60%未満
である試料6では、回路形成用荷電性粉末の飛散を抑え
られているものの、この回路形成用荷電性粉末を用いた
回路パターンのシート抵抗は良好なものではなかった。
However, when the apparent specific gravity is excessively reduced, that is, in Sample 6 in which the value of “apparent specific gravity / true specific gravity” is less than 60%, scattering of the chargeable powder for forming a circuit is suppressed. The sheet resistance of the circuit pattern using the chargeable powder for formation was not good.

【0023】また、見掛け比重/真比重の値が100%
である試料7では、この回路形成用荷電性粉末を用いた
回路パターンのシート抵抗は良好なものであったもの
の、回路形成用荷電性粉末の飛散を抑えられなかった。
Further, the value of apparent specific gravity / true specific gravity is 100%
In Sample 7, the sheet resistance of the circuit pattern using the chargeable powder for circuit formation was good, but scattering of the chargeable powder for circuit formation could not be suppressed.

【0024】さらに、試料1と同様の銅粉末を用いてい
るが熱可塑性樹脂の含有量を増大させた試料8,9で
は、試料6と同様に、回路形成用荷電性粉末の飛散を抑
えられているものの、これらの回路形成用荷電性粉末を
用いた回路パターンのシート抵抗は良好なものではなか
った。
Further, in Samples 8 and 9 in which the same copper powder as in Sample 1 was used but the content of the thermoplastic resin was increased, the scattering of the chargeable powder for forming a circuit was suppressed as in Sample 6. However, the sheet resistance of the circuit pattern using these chargeable powders for forming a circuit was not good.

【0025】上述の実施例の回路パターン形成方法によ
れば、中空を有する銅粉末、あるいは複数の微小孔を有
する酸化銅粉末の外周に熱可塑性樹脂を被覆した回路形
成用荷電性粉末を用いているため、銅粉末あるいは酸化
銅粉末の粒径を変えることなく回路形成用荷電性粉末の
質量を低減することができ、その結果、回路形成用荷電
性粉末の飛散を抑えたカブリのない高解像度で、かつ良
好な電気抵抗を示す回路パターンを形成することができ
る。
According to the method of forming a circuit pattern of the above-described embodiment, a copper powder having a hollow or a copper oxide powder having a plurality of micropores is charged with a chargeable powder for forming a circuit in which a thermoplastic resin is coated on the outer periphery. As a result, the mass of the chargeable powder for circuit formation can be reduced without changing the particle size of the copper powder or copper oxide powder, and as a result, high-resolution without fogging that suppresses the scattering of the chargeable powder for circuit formation Thus, a circuit pattern exhibiting good electrical resistance can be formed.

【0026】図3は、本発明の配線基板に係る第1の実
施例の断面図である。配線基板30は、セラミックグリ
ーンシート31を備える。そして、セラミックグリーン
シート31上に、上述の実施例の試料2〜5,7の回路
形成用荷電性粉末を使用して、電子写真法によって回路
パターン32を印刷した後、還元雰囲気中において約1
000℃で焼成する。
FIG. 3 is a sectional view of a first embodiment according to the wiring board of the present invention. The wiring board 30 includes a ceramic green sheet 31. Then, the circuit pattern 32 is printed on the ceramic green sheet 31 by electrophotography using the chargeable powders for forming circuits of the samples 2 to 5 and 7 of the above-described example, and then, about 1 mm in a reducing atmosphere.
Bake at 000 ° C.

【0027】図4は、本発明の配線基板に係る第2の実
施例の断面図である。配線基板40は、第1〜第3のセ
ラミックグリーンシート41a〜41cを備える。そし
て、第2及び第3のセラミックグリーンシート41b,
41c上に、上述の実施例の試料2〜5,7の回路形成
用荷電性粉末を使用して、電子写真法によって回路パタ
ーン42a,42bを印刷する。次いで、第1〜第3の
セラミックグリーンシート41a〜41cを積層して圧
力をかけ、一体成形した後、還元雰囲気中において約1
000℃で焼成する。
FIG. 4 is a sectional view of a second embodiment according to the wiring board of the present invention. The wiring board 40 includes first to third ceramic green sheets 41a to 41c. Then, the second and third ceramic green sheets 41b,
The circuit patterns 42a and 42b are printed on 41c by electrophotography using the chargeable powders for circuit formation of the samples 2 to 5 and 7 of the above-described embodiment. Next, after laminating the first to third ceramic green sheets 41a to 41c, applying pressure, and integrally molding, the ceramic green sheets 41a to 41c are reduced by about 1 in a reducing atmosphere.
Bake at 000 ° C.

【0028】なお、第2及び第3のセラミックグリーン
シート41b,41c上の回路パターン42a,42b
は、ビアホール43により接続されるが、このビアホー
ル43は既存の技術で形成される。例えば、導体描画装
置を用いてビアホールごとに導体を圧入していく方法な
どがある。この場合には、回路パターンを42a,42
bを電子写真法で形成した後、ビアホール43を形成す
ると粉体が描画機のノズルを傷める可能性があるため、
回路パターン42a,42bを形成する前にビアホール
43を形成しておくことが好ましい。
The circuit patterns 42a, 42b on the second and third ceramic green sheets 41b, 41c are used.
Are connected by a via hole 43, which is formed by an existing technology. For example, there is a method of press-fitting a conductor into each via hole using a conductor drawing apparatus. In this case, the circuit patterns 42a, 42
If b is formed by electrophotography and then the via hole 43 is formed, the powder may damage the nozzle of the drawing machine.
It is preferable to form the via hole 43 before forming the circuit patterns 42a and 42b.

【0029】上述の実施例の配線基板によれば、中空を
有する銅粉末、あるいは複数の微小孔を有する酸化銅粉
末の外周に熱可塑性樹脂を被覆した回路形成用荷電性粉
末を用いて、電子写真法によって回路パターンをセラミ
ックグリーンシートに印刷し、その後、それらのセラミ
ックグリーンシートを焼成して配線基板を形成するた
め、高解像度で、かつ良好な電気抵抗の回路パターンを
備えた配線基板を得ることが可能となる。
According to the wiring board of the above-described embodiment, an electronic circuit is formed by using a copper powder having a hollow or a copper oxide powder having a plurality of micropores and a chargeable circuit-forming powder in which a thermoplastic resin is coated on the outer periphery. A circuit pattern is printed on ceramic green sheets by a photographic method, and thereafter, the ceramic green sheets are fired to form a wiring board. Thus, a wiring board having a circuit pattern with high resolution and good electric resistance is obtained. It becomes possible.

【0030】[0030]

【発明の効果】本発明の回路パターン形成方法によれ
ば、中空または複数の微小孔を有する導電性金属粉末あ
るいは導電性金属酸化物粉末の外周に熱可塑性樹脂を被
覆した回路形成用荷電性粉末を用いているため、導電性
金属粉末あるいは導電性金属酸化物粉末の粒径を変える
ことなく回路形成用荷電性粉末の質量を低減することが
でき、その結果、回路形成用荷電性粉末の飛散を抑えた
カブリのない高解像度で、かつ良好な電気抵抗を示す回
路パターンを形成することができる。
According to the method of forming a circuit pattern of the present invention, a chargeable powder for forming a circuit is formed by coating a thermoplastic resin on the outer periphery of a conductive metal powder or a conductive metal oxide powder having a hollow or a plurality of fine holes. Is used, the mass of the chargeable powder for forming a circuit can be reduced without changing the particle size of the conductive metal powder or the conductive metal oxide powder, and as a result, the chargeable powder for forming a circuit is scattered. It is possible to form a circuit pattern having a high resolution with reduced fog and a good electric resistance.

【0031】本発明の配線基板によれば、中空または複
数の微小孔を有する導電性金属粉末あるいは導電性金属
酸化物粉末の外周に熱可塑性樹脂を被覆した回路形成用
荷電性粉末を用いて、電子写真法によって回路パターン
をセラミックグリーンシートに印刷し、その後、それら
のセラミックグリーンシートを焼成して配線基板を形成
するため、高解像度で、かつ良好な電気抵抗の回路パタ
ーンを備えた配線基板を得ることが可能となる。
According to the wiring board of the present invention, a conductive metal powder having a hollow or a plurality of fine holes or a conductive metal oxide powder is coated with a thermoplastic resin on the outer periphery thereof using a chargeable powder for forming a circuit. The circuit pattern is printed on ceramic green sheets by electrophotography, and then the ceramic green sheets are fired to form a wiring board, so that a wiring board having a circuit pattern with high resolution and good electric resistance is formed. It is possible to obtain.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の回路パターン形成方法に係る一実施例
に用いる電子写真システムの構成図である。
FIG. 1 is a configuration diagram of an electrophotographic system used in an embodiment according to a circuit pattern forming method of the present invention.

【図2】図1の回路パターン形成方法に用いられる回路
形成用荷電性粉末の断面図である。
FIG. 2 is a cross-sectional view of a circuit-forming chargeable powder used in the circuit pattern forming method of FIG.

【図3】本発明の配線基板に係る第1の実施例の断面図
である。
FIG. 3 is a sectional view of a first embodiment of the wiring board according to the present invention;

【図4】本発明の配線基板に係る第2の実施例の断面図
である。
FIG. 4 is a sectional view of a second embodiment according to the wiring board of the present invention.

【符号の説明】[Explanation of symbols]

12 感光体 15 回路形成用荷電性粉末 16,31,41a〜41c セラミックグリーン
シート 21 導電性金属粉末 23 熱可塑性樹脂 32,42a,42b 回路パターン
DESCRIPTION OF SYMBOLS 12 Photoreceptor 15 Chargeable powder for circuit formation 16, 31, 41a-41c Ceramic green sheet 21 Conductive metal powder 23 Thermoplastic resin 32, 42a, 42b Circuit pattern

フロントページの続き Fターム(参考) 2H005 AA06 AA15 AA29 CB01 CB10 DA09 EA10 4E351 AA07 BB01 BB24 BB29 CC16 DD01 DD31 DD52 DD56 GG01 GG09 5E343 AA02 AA23 BB24 BB59 DD72 ER33 ER35 GG08 GG11 5E346 AA15 CC32 DD11 EE23 GG04 GG06 GG09 HH26 HH32 Continued on the front page F-term (reference) 2H005 AA06 AA15 AA29 CB01 CB10 DA09 EA10 4E351 AA07 BB01 BB24 BB29 CC16 DD01 DD31 DD52 DD56 GG01 GG09 5E343 AA02 AA23 BB24 BB59 DD72 ER33 ER35 GG15 GG11 GG11 AGG03H32 GG11 GG11 5G32 GG11 GG11 5G346E

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 感光体の表面を帯電する帯電工程と、前
記感光体に静電的な潜像パターンを形成する露光工程
と、前記潜像パターン上へ回路形成用荷電性粉末を静電
力により付着させる現像工程と、前記潜像パターン上の
前記回路形成用荷電性粉末を前記セラミックグリーンシ
ート上へ転写する転写工程と、前記セラミックグリーン
シート上へ転写された前記回路形成用荷電性粉末を定着
させる定着工程とを含む回路パターン形成方法であっ
て、 前記回路形成用荷電性粉末が、中空または複数の微小孔
を有する導電性金属粉末あるいは導電性金属酸化物粉末
の外周に熱可塑性樹脂を被覆したものであることを特徴
とする回路パターン形成方法。
1. A charging step of charging a surface of a photoreceptor, an exposure step of forming an electrostatic latent image pattern on the photoreceptor, and charging a circuit-forming chargeable powder onto the latent image pattern by electrostatic force. A developing step of adhering, a transfer step of transferring the chargeable powder for circuit formation on the latent image pattern onto the ceramic green sheet, and fixing the chargeable powder for circuit formation transferred to the ceramic green sheet. And fixing step, wherein the chargeable powder for forming a circuit is coated with a thermoplastic resin on the outer periphery of a conductive metal powder or a conductive metal oxide powder having a hollow or a plurality of micropores. A circuit pattern forming method, characterized in that:
【請求項2】 前記導電性金属粉末あるいは導電性金属
酸化物粉末は、見掛け比重が真比重の60〜90%の範
囲であることを特徴とする回路パターン形成方法。
2. A circuit pattern forming method according to claim 1, wherein said conductive metal powder or conductive metal oxide powder has an apparent specific gravity in the range of 60 to 90% of a true specific gravity.
【請求項3】 請求項1あるいは請求項2に記載の回路
パターン形成方法によって、前記回路パターンが印刷さ
れた前記セラミックグリーンシートを焼成してなること
を特徴とする配線基板。
3. A wiring board, wherein the ceramic green sheet on which the circuit pattern is printed is fired by the circuit pattern forming method according to claim 1.
【請求項4】 請求項1あるいは請求項2に記載の回路
パターン形成方法によって、前記回路パターンが印刷さ
れた前記セラミックグリーンシートを積層し、焼成して
なることを特徴とする配線基板。
4. A wiring board, wherein the ceramic green sheets on which the circuit patterns are printed are laminated and fired by the circuit pattern forming method according to claim 1.
JP2000091728A 2000-03-29 2000-03-29 Circuit pattern forming method and wiring board formed thereby Expired - Lifetime JP4543490B2 (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
JP2000091728A JP4543490B2 (en) 2000-03-29 2000-03-29 Circuit pattern forming method and wiring board formed thereby

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6977130B2 (en) 2002-07-15 2005-12-20 Kabushiki Kaisha Toshiba Method of manufacturing an electronic circuit and manufacturing apparatus of an electronic circuit
US7067398B2 (en) 2004-04-13 2006-06-27 Kabushiki Kaisha Toshiba Method of producing electronic circuit and electronic circuit
US7433637B2 (en) 2004-04-08 2008-10-07 Kabsushiki Kaisha Toshiba Image forming apparatus and method of manufacturing electronic circuit using the same
US7469941B2 (en) 2004-04-13 2008-12-30 Kabushiki Kaisha Toshiba Method of producing a wiring board
US7486921B2 (en) 2003-12-26 2009-02-03 Kabushiki Kaisha Toshiba Method of producing electronic circuit, and electronic circuit substrate
US7939171B2 (en) 2003-12-26 2011-05-10 Kabushiki Kaisha Toshiba Metal-containing resin particle, metal-containing resin layer, method of forming metal-containing resin layer, and substrate for electronic circuit
US8220147B2 (en) 2003-12-26 2012-07-17 Kabushiki Kaisha Toshiba Metal-containing resin particle, resin particle, electronic circuit substrate, and method of producing electronic circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05204169A (en) * 1992-01-27 1993-08-13 Fuji Xerox Co Ltd Electrophotographic sensitive body and its production
JPH09190018A (en) * 1996-01-08 1997-07-22 Canon Inc Electrophotographic developer carrier
JPH1158833A (en) * 1997-08-19 1999-03-02 Fuji Xerox Co Ltd Method and apparatus for forming color image
JPH11251718A (en) * 1998-03-03 1999-09-17 Murata Mfg Co Ltd Chargeable powder for forming circuit and multilayered wiring board using the same
JPH11354908A (en) * 1998-06-08 1999-12-24 Murata Mfg Co Ltd Method for forming circuit pattern and multilayer wiring substrate formed by using the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05204169A (en) * 1992-01-27 1993-08-13 Fuji Xerox Co Ltd Electrophotographic sensitive body and its production
JPH09190018A (en) * 1996-01-08 1997-07-22 Canon Inc Electrophotographic developer carrier
JPH1158833A (en) * 1997-08-19 1999-03-02 Fuji Xerox Co Ltd Method and apparatus for forming color image
JPH11251718A (en) * 1998-03-03 1999-09-17 Murata Mfg Co Ltd Chargeable powder for forming circuit and multilayered wiring board using the same
JPH11354908A (en) * 1998-06-08 1999-12-24 Murata Mfg Co Ltd Method for forming circuit pattern and multilayer wiring substrate formed by using the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6977130B2 (en) 2002-07-15 2005-12-20 Kabushiki Kaisha Toshiba Method of manufacturing an electronic circuit and manufacturing apparatus of an electronic circuit
US7486921B2 (en) 2003-12-26 2009-02-03 Kabushiki Kaisha Toshiba Method of producing electronic circuit, and electronic circuit substrate
US7939171B2 (en) 2003-12-26 2011-05-10 Kabushiki Kaisha Toshiba Metal-containing resin particle, metal-containing resin layer, method of forming metal-containing resin layer, and substrate for electronic circuit
US8220147B2 (en) 2003-12-26 2012-07-17 Kabushiki Kaisha Toshiba Metal-containing resin particle, resin particle, electronic circuit substrate, and method of producing electronic circuit
US7433637B2 (en) 2004-04-08 2008-10-07 Kabsushiki Kaisha Toshiba Image forming apparatus and method of manufacturing electronic circuit using the same
US7877871B2 (en) 2004-04-08 2011-02-01 Kabushiki Kaisha Toshiba Method of manufacturing an electronic circuit formed on a substrate
US7067398B2 (en) 2004-04-13 2006-06-27 Kabushiki Kaisha Toshiba Method of producing electronic circuit and electronic circuit
US7469941B2 (en) 2004-04-13 2008-12-30 Kabushiki Kaisha Toshiba Method of producing a wiring board

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