JP2001284543A - Memory device and its manufacturing method - Google Patents

Memory device and its manufacturing method

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Publication number
JP2001284543A
JP2001284543A JP2000095753A JP2000095753A JP2001284543A JP 2001284543 A JP2001284543 A JP 2001284543A JP 2000095753 A JP2000095753 A JP 2000095753A JP 2000095753 A JP2000095753 A JP 2000095753A JP 2001284543 A JP2001284543 A JP 2001284543A
Authority
JP
Japan
Prior art keywords
electrode
platinum group
film
metal
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000095753A
Other languages
Japanese (ja)
Inventor
Tatsuya Hara
竜弥 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2000095753A priority Critical patent/JP2001284543A/en
Publication of JP2001284543A publication Critical patent/JP2001284543A/en
Withdrawn legal-status Critical Current

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  • Semiconductor Memories (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric memory device which allows a high-cost precious film such as platinum group being an electrode material of a ferroelectric capacitor to be thinned and the electrode height to be thickened to ensure the capacitance. SOLUTION: A metal film 107 made of other than platinum group is formed like a pedestal, a platinum group metal film 108 is formed so as to cover it and used as a first electrode, the first electrode is covered with a ferroelectric film 109, and then a conductive metal film 110 is formed as a second electrode, thus increasing the total thickness of the electrode films.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、キャパシタを有す
るメモリ装置およびその製造方法に関する。
The present invention relates to a memory device having a capacitor and a method of manufacturing the same.

【0002】[0002]

【従来の技術】半導体メモリでは微細化を行うにあた
り、キャパシタの容量確保のために材料の高誘電率化、
薄膜化および立体構造による面積拡大を行ってきた。近
年、金属酸化物からなる強誘電体を用い始めたがその性
質上、電極として酸化しにくい白金族等の貴金属を用い
る必要があった。白金族等の貴金属は加工が困難である
ため、複雑な立体構造をとることができず、容量増加の
ために第一の電極の厚みを増し、第一の電極側面を用い
ていた。
2. Description of the Related Art In miniaturization of a semiconductor memory, a material having a high dielectric constant is required to secure a capacitor capacity.
The area has been expanded by thinning and three-dimensional structure. In recent years, ferroelectrics composed of metal oxides have begun to be used, but due to their properties, it has been necessary to use a noble metal such as a platinum group which is hardly oxidized as an electrode. Since noble metals such as platinum group metals are difficult to process, a complex three-dimensional structure cannot be obtained, and the thickness of the first electrode is increased to increase the capacity, and the side surface of the first electrode is used.

【0003】[0003]

【発明が解決しようとする課題】白金族等の貴金属は高
価であるため、製造原価低減のためには、可能な限り、
薄くする必要があるが、第一の電極の厚みはキャパシタ
容量確保のために側面積を増加させるために逆に厚くす
る必要があった。
Since noble metals such as platinum group metals are expensive, in order to reduce production costs,
Although it is necessary to reduce the thickness, the thickness of the first electrode needs to be increased to increase the side area in order to secure the capacitor capacity.

【0004】本発明は白金族等の貴金属を厚くすること
なく、大きな側面積をもった第一の電極により、キャパ
シタ容量を増加することを目的とする。
An object of the present invention is to increase the capacitance of a capacitor by using a first electrode having a large side area without increasing the thickness of a noble metal such as a platinum group metal.

【0005】[0005]

【課題を解決するための手段】本発明はキャパシタ第一
の電極が台座状の白金族等の貴金属以外の導電体あるい
は絶縁体とその表面を覆う白金族等の貴金属からなる特
徴を持つ。第一の電極の厚みは白金族等の貴金属の膜厚
と台座状の白金族等の貴金属以外の導電体あるいは絶縁
体の厚みの和となる。そのため、台座状導電体あるいは
絶縁体の厚みを厚くすることにより白金族等の貴金属の
厚みを薄くすることが可能となる。
The present invention is characterized in that the first electrode of the capacitor is made of a pedestal-shaped conductor or insulator other than a noble metal such as platinum group and a noble metal such as platinum group covering the surface thereof. The thickness of the first electrode is the sum of the thickness of the noble metal such as the platinum group and the thickness of the pedestal-shaped conductor or insulator other than the noble metal such as the platinum group. Therefore, it is possible to reduce the thickness of a noble metal such as a platinum group by increasing the thickness of the pedestal conductor or the insulator.

【0006】白金族等の貴金属以外の導電体は例として
タングステン、チタン、モリブデン等やそれらの導電性
化合物タングステンシリサイド、チタンナイトライド等
や複数の金属からなる合金であるチタンタングステン等
がある。絶縁体の例としてはシリコン酸化膜、シリコン
窒化膜、チタン酸化膜等がある。
Examples of conductors other than noble metals such as platinum group metals include tungsten, titanium, molybdenum and the like, conductive compounds thereof such as tungsten silicide, titanium nitride, and titanium tungsten which is an alloy composed of a plurality of metals. Examples of the insulator include a silicon oxide film, a silicon nitride film, and a titanium oxide film.

【0007】これらの膜厚は白金族等の貴金属を製造原
価低減のために薄く出来る膜厚となる。そのような膜厚
は100nm以上である。さらに好ましい膜厚は150nm〜300n
mである。
[0007] These film thicknesses are such that noble metals such as platinum group metals can be made thinner in order to reduce manufacturing costs. Such a film thickness is 100 nm or more. More preferred film thickness is 150 nm to 300 n
m.

【0008】[0008]

【発明の実施の形態】以下、実施例により本発明を詳述
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to examples.

【0009】図1は本発明の第一の実施例を示す断面図
である。
FIG. 1 is a sectional view showing a first embodiment of the present invention.

【0010】図1(a) Si基板101上に素子分離領域102、
ソースドレイン領域103、ゲート酸化膜104、MOSトラン
ジスタゲート電極105を形成し、その後、絶縁膜106を成
膜する。
FIG. 1A shows an element isolation region 102 on a Si substrate 101.
A source / drain region 103, a gate oxide film 104, and a MOS transistor gate electrode 105 are formed, and thereafter, an insulating film 106 is formed.

【0011】図1(b)次に白金族以外の金属膜、例えばチ
タン、あるいはチタンタングステンのような合金膜107
を成膜したのち該金属膜をフォトリソおよびエッチング
により台形状に加工する。
FIG. 1 (b) Next, a metal film other than the platinum group, for example, an alloy film 107 such as titanium or titanium tungsten.
Is formed, and the metal film is processed into a trapezoidal shape by photolithography and etching.

【0012】図1(c)次に白金族金属、例えば白金、イリ
ジウム等の金属108を成膜し、フォトリソおよびエッチ
ングにより金属膜107を覆う形のパターンを形成する。
1C. Next, a platinum group metal, for example, a metal 108 such as platinum or iridium is formed into a film, and a pattern covering the metal film 107 is formed by photolithography and etching.

【0013】図1(d)次に強誘電体108およびキャパシタ
第二の電極となる金属膜109を成膜し、フォトリソ お
よびエッチングによりキャパシタを形成する。
FIG. 1 (d) Next, a ferroelectric 108 and a metal film 109 to be a capacitor second electrode are formed, and a capacitor is formed by photolithography and etching.

【0014】以上をもって本発明の第一の実施例とす
る。
The above is the first embodiment of the present invention.

【0015】図2は本発明の第二の実施例を示す断面図
である。第一の実施例の白金族以外の金属膜107の代わ
りに絶縁膜207を成膜、加工する。絶縁膜はシリコン酸
化膜、あるいはシリコン窒化膜、チタン酸化膜等により
形成する。
FIG. 2 is a sectional view showing a second embodiment of the present invention. An insulating film 207 is formed and processed instead of the metal film 107 other than the platinum group metal of the first embodiment. The insulating film is formed of a silicon oxide film, a silicon nitride film, a titanium oxide film, or the like.

【0016】[0016]

【発明の効果】本発明によれば、白金族金属膜の膜厚と
下部白金族以外の金属あるいは絶縁膜の膜厚の両者の和
が第一の電極厚みとなり、白金族の成膜膜厚を薄くし
て、キャパシタ面積を大きくできる。
According to the present invention, the sum of the thickness of the platinum group metal film and the thickness of the metal or insulating film other than the lower platinum group is the first electrode thickness. And the area of the capacitor can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第一の実施例の主要工程断面図。FIG. 1 is a sectional view of a main process of a first embodiment of the present invention.

【図2】本発明の第二の実施例の主要断面図。FIG. 2 is a main sectional view of a second embodiment of the present invention.

【図3】従来例。FIG. 3 shows a conventional example.

【符号の説明】[Explanation of symbols]

101 シリコン基板 102 素子分離領域 103 ソースドレイン領域 104 ゲート酸化膜 105 MOSトランジスタゲート電極 106 絶縁膜 107 白金族等の貴金属以外の金属膜 108 白金族金属からなるキャパシタ第一の電極 109 強誘電体膜 110 キャパシタ第二の電極 201 シリコン基板 202 素子分離領域 203 ソースドレイン領域 204 ゲート酸化膜 205 MOSトランジスタゲート電極 206 絶縁膜 207 絶縁膜 208 白金族金属からなるキャパシタ第一の電極 209 強誘電体膜 210 キャパシタ第二の電極 301 シリコン基板 302 素子分離領域 303 ソースドレイン領域 304 ゲート酸化膜 305 MOSトランジスタゲート電極 306 絶縁膜 308 白金族金属からなるキャパシタ第一の電極 309 強誘電体膜 310 キャパシタ第二の電極 101 silicon substrate 102 device isolation region 103 source / drain region 104 gate oxide film 105 MOS transistor gate electrode 106 insulating film 107 metal film other than noble metals such as platinum group 108 capacitor first electrode made of platinum group metal 109 ferroelectric film 110 Capacitor second electrode 201 Silicon substrate 202 Element isolation region 203 Source drain region 204 Gate oxide film 205 MOS transistor gate electrode 206 Insulation film 207 Insulation film 208 Capacitor first electrode made of platinum group metal 209 Ferroelectric film 210 Capacitor second Second electrode 301 Silicon substrate 302 Device isolation region 303 Source drain region 304 Gate oxide film 305 MOS transistor gate electrode 306 Insulation film 308 Capacitor first electrode made of platinum group metal 309 Ferroelectric film 310 Capacitor second electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】基板上に形成されており、白金族等の貴金
属以外の導電体からなる台座状パターンとそれをおおう
白金族等の貴金属からなる第一の電極から形成されてい
るキャパシタを有するメモリ装置。
1. A pedestal-shaped pattern formed on a substrate and made of a conductor other than a noble metal such as a platinum group, and a capacitor formed of a first electrode made of a noble metal such as a platinum group and covering the pedestal pattern. Memory device.
【請求項2】基板上に形成されており、白金族等の貴金
属以外の金属が絶縁体からなる台座状のパターンとそれ
をおおう白金族等の貴金属からなる第一の電極と強誘電
体と第二の電極をからなるキャパシタを有するメモリ装
置。
2. A pedestal-shaped pattern formed on a substrate and made of an insulator made of a metal other than a noble metal such as a platinum group, and a first electrode made of a noble metal such as a platinum group covering the first pattern and a ferroelectric. A memory device having a capacitor comprising a second electrode.
【請求項3】前記導電体あるいは絶縁体を所定の大きさ
の台座状パターンをフォトリソおよびエッチングで形成
する工程と、そのパターンを覆う形で白金族等の貴金属
を成膜し、第一の電極パターンをフォトリソおよびエッ
チングで形成する工程を備えていることを特徴とするメ
モリ装置の製造方法。
3. A step of forming said conductor or insulator into a pedestal pattern of a predetermined size by photolithography and etching, and forming a noble metal such as platinum group so as to cover said pattern. A method for manufacturing a memory device, comprising a step of forming a pattern by photolithography and etching.
JP2000095753A 2000-03-30 2000-03-30 Memory device and its manufacturing method Withdrawn JP2001284543A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000095753A JP2001284543A (en) 2000-03-30 2000-03-30 Memory device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000095753A JP2001284543A (en) 2000-03-30 2000-03-30 Memory device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2001284543A true JP2001284543A (en) 2001-10-12

Family

ID=18610610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000095753A Withdrawn JP2001284543A (en) 2000-03-30 2000-03-30 Memory device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2001284543A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008117371A1 (en) * 2007-03-23 2008-10-02 Fujitsu Limited Resistance storage element and non-volatile semiconductor storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008117371A1 (en) * 2007-03-23 2008-10-02 Fujitsu Limited Resistance storage element and non-volatile semiconductor storage device
JP5345052B2 (en) * 2007-03-23 2013-11-20 富士通株式会社 Resistance memory element and nonvolatile semiconductor memory device

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