JP2001284531A - Clock changer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock changer which executes the control for gradually increasing the frequency of a clock applied a high current consumption type semiconductor device and the control for gradually decreasing the clock frequency in testing the semiconductor device which has a high clock frequency in a regular operation and consumes a high current in the regular operation. SOLUTION: The clock changer is composed of a clock generator for generating clocks covering all frequencies required for a semiconductor device and a selector circuit for selecting and outputting the clock generated by the clock generator. Further, the clock changer comprises a synchronizing circuit for generating a switching control signal synchronized with each clock, and a gate circuit constituting the selector circuit is controlled according to the switching control signal synchronized with each clock obtained by the synchronizing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching device suitable for use in testing a semiconductor device which consumes a large amount of current due to its high operating speed.

[0002]

2. Description of the Related Art A semiconductor device having a CMOS structure is an FET.
Since the switch element constituted by the above-mentioned operation turns on and off in synchronization with the clock, a relatively large current is consumed every time the FET is inverted from the on state to the off state and from the off state to the on state. Therefore, it has a characteristic that the current consumption increases in proportion to the frequency of the operation clock. For this reason, there is a semiconductor device having a particularly high operation speed, for example, a device whose clock frequency reaches about 500 MHz to 2 GHz consumes an extremely large current (for example, 40 to 50 amps).

In such a high-current-consuming semiconductor device, if the semiconductor device is started in an operation mode that consumes a large current from the beginning of the start, the load on the power supply circuit is large. A mechanism is provided in which an operation is started with a clock, the frequency of the clock is increased stepwise with the passage of time, and finally the operation is performed with a steady operation clock. FIG. 4 shows an example. Reference numeral 10 shown in FIG. 4 indicates a large current consumption type semiconductor device. A frequency switching circuit 11 is provided inside the large current consumption type semiconductor device 10. A clock of, for example, 200 MHz is externally input to the frequency switching circuit 11 through a clock input terminal CLK.

The frequency switching circuit 11 is initially set to a through state at the time of start-up, and supplies the input 200 MHz clock to the load circuit 12 as it is. As time elapses, the clocks are switched in the order of, for example, 400 MHz and 800 MHz. The frequency is converted, and the circuit 12 is finally stabilized in a state where a clock of 800 MHz is applied to the circuit 12. When stopping the operation, the frequency switching circuit 11 lowers the frequency in the order of 400 MHz and 200 MHz from the output state of the 800 MHz clock, and gradually reduces the current consumption to stop the operation.

When testing this large current consumption type semiconductor device 10, it is generally unknown at the start of the test whether or not the frequency switching circuit 11 operates normally. And it is necessary to switch the clock frequency externally and apply it. FIG.
FIG. 1 shows an example of a clock switching device that can be considered in the related art. Reference numeral 20 indicates the entire clock switching device. The clock switching device 20 selects a clock generation unit 21 that generates clocks of all frequencies required by the large current consumption type semiconductor device 10 and one of clocks of each frequency generated by the clock generation unit 21. Selection circuit 22
And a controller 23 for controlling the switching state of the selection circuit 22.
And can be configured by:

The clock generator 21 generates a clock 1 having a frequency 1/16 that of the original clock PC input to the input terminal 24.
A 1/16 frequency divider 21A that outputs / 16PC, and a clock 1 / 2PC having a frequency of, for example, 1/2 the original clock PC
And a through circuit 21C that outputs the original clock PC as it is. The selection circuit 22 includes a plurality of gate circuits 22A, 22B,
22C, and the gate circuits 22A, 2C.
One of 2B and 22C is controlled to be open by an open / close control signal output from the controller 23, and the clocks 1 / 16PC and 1 / 2P generated by the clock generator 21.
C, PC, and the clock input terminal CLK of the large current consumption type semiconductor device 10 through the driver DR.
Is applied to

When the frequency of the original clock PC is, for example, 1 GHz, the 1/2 frequency divider 21B outputs a clock of 500 MHz, and the 1/16 frequency divider 21C outputs a clock of 62.5 MHz. Therefore, in order to bring the large current consumption type semiconductor device 10 into an operating state prior to the start of the test, the gate circuit 22A is first opened and a clock of 62.5 MHz is applied to the clock CLK of the large current consumption type semiconductor device 10. . At a time (about several seconds) at which a time at which the operation is considered to be stable at a clock frequency of 62.5 MHz, the gate circuit 22A is closed, and the gate circuit 22B is opened instead. Next, the gate circuit 22B is closed, the gate circuit 22C is opened, and a clock PC having a maximum frequency of 1 GHz is applied to the clock input terminal CLK.

[0008]

In the clock switching device 20 shown in FIG. 5, each gate circuit 22 is controlled by the controller 23.
A, 22B, 22C, the opening / closing control signals XA, XB,
XC is each clock signal 1 / 16PC, 1 / 2PC, PC
, There is a possibility that a pulse in which a part of the clock is cut off may occur. That is, as shown in FIG. 6, each clock PC, 1 / 2PC, 1 / 16P
Assuming that the open / close control signals XB and XC are inverted at time T1 with respect to C, a pulse P1 having a narrow pulse width is obtained by removing a part of the pulse width τ of the original clock PC having the highest frequency as shown in FIG. 6F. I do.

Also, as shown in FIG. 7, 1 / 16PC is H
Assuming that the open / close control signal XC falls to L logic in the logic state and the open / close control signal XB rises to H logic instead.
As shown in FIG. 7E, the clock output from gate circuit 22 is clock 1/2, immediately after the fall of 1 / 16PC.
PC is output, and also in this case, a negative pulse P2 having a narrow pulse width is output. When a pulse P1 or P2 having a pulse width shorter than the pulse width τ of the original clock PC having the highest frequency is applied to the semiconductor device 10, there are cases where the state of the FET inside the semiconductor device 10 is inverted and which is not inverted. However, there is a possibility that the operating state may be changed to a completely different state.

[0010] In addition, when the state without the clock has passed for a prescribed time, for example, about 1 µs or more as shown in FIG. 6G,
Since the current value that has begun to flow returns to a state of zero, if the original clock PC having the highest speed is applied from that state, for example, it is dangerous because the current consumption rapidly increases. An object of the present invention is to generate a pulse P1 or P2 having a pulse width narrower than a predetermined pulse width τ as shown in FIGS. 6 and 7, or a phenomenon in which a clock-free state continues for a predetermined time or more. It is an object of the present invention to provide a clock switching circuit that does not cause any problem.

[0011]

According to a first aspect of the present invention, there is provided a clock generator for generating clocks of all frequencies necessary for a semiconductor device, and one of clocks of respective frequencies generated by the clock generator. A clock switching circuit comprising a plurality of gate circuits for selecting and taking out one of the gate circuits and a controller for supplying an opening / closing control signal to the plurality of gate circuits; A clock switching device including a plurality of synchronization circuits for synchronizing a conversion point of a control signal with a rising or falling timing of a clock of each frequency is proposed.

According to a second aspect of the present invention, in the clock switching device according to the first aspect, an open / close control signal is supplied to a gate circuit that controls open / close of a lowest frequency clock among a plurality of synchronization circuits constituting a controller. At the preceding stage of each of the other synchronization circuits except for the given synchronization circuit, it detects that the open / close control signal output by the low frequency side synchronization circuit has been inverted to the state of controlling the closing and sends it to its own synchronization circuit. A clock switching device having a configuration provided with a prohibition gate for applying a switching command signal is proposed.

[0013]

According to the configuration of the clock switching circuit proposed in claim 1 of the present invention, each synchronization circuit transmits a control signal synchronized with each of clocks 1 / 16PC, 1 / 2PC, and PC having different frequencies. Each gate circuit 22 to output
Since A, 22B, and 22C are controlled to open and close by a control signal synchronized with the clock controlled by the self, the pulse P1 having a narrow pulse width, which is a part of the clock controlled by the self, is output. It is possible to avoid a phenomenon in which a clock of another frequency is output near the end timing of a clock of a certain frequency and a negative pulse P2 having a narrow pulse width is generated.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a clock switching device proposed in claim 1 of the present invention. Parts corresponding to those in FIG. 5 are denoted by the same reference numerals. That is, 20 shown in FIG. 1 indicates the entire clock switching device. As described with reference to FIG. 5, the clock switching device includes a clock generator 21 that outputs a clock having all frequencies required by the large current consuming semiconductor device 10, and a clock of each frequency output by the clock generator 21. And a controller 23 for supplying a control signal to the selection circuit 22.

The configuration characteristic of the present invention exists in the controller 23. The controller 23, which is a feature of the present invention, controls the switching command signals XA, XB, XC input to the controller 23 to open / close control signals XAO, XB synchronized with each clock cycle.
Synchronizing circuits SYNC1 and SYNC for converting into O and XCO
2 and SYNC3. This synchronization circuit
For example, a D-type flip-flop can be configured by cascading two stages. Further, according to the present invention, the open / close control signal XA is supplied to the gate circuit 22A for selecting the clock having the lowest frequency.
A prohibition gate G1 is provided at the preceding stage of each of the other synchronization circuits SYNC2 and SYNC3 except for the synchronization circuit SYNC1 that provides O.
G2 is provided. These forbidden gates G1 and G2
Is connected to one of the input terminals,
1 and a signal which detects that the gate circuits 22A and 22B of the clock signal line having a lower frequency than the clock signal line to which G2 is connected are closed.

The open / close control signals XAO, XBO, XCO are taken out from, for example, the normal phase output terminal of a D-type flip-flop constituting each of the synchronizing circuits SYNC1 to SYNC3, and these open / close control signals XAO, XBO, XCO are applied to each gate circuit 22A. , 22B and 22C. Further, detection signals / XAO and / XBO which become H logic in a state where these gate circuits 22A and 22B are closed are taken out from the inverted phase output terminal, and the detection signals / XAO and / XBO are disabled by the prohibition gate G.
1 and G2.

Therefore, these prohibition gates G1 and G2 are controlled to open when the gate circuit 22A or 22B of the path having a frequency lower than that of the own path is controlled to be closed, and switched in this state. The command signal XA or XC is applied to the synchronization circuit SYNC1 or SYNC3. Each of the clock input terminals of the D-type flip-flops constituting each of the synchronization circuits SYNC1 to SYNC3 has a synchronization circuit SYNC.
In C1, a clock having the lowest frequency (in this embodiment, a case where the frequency divider 21A is a quarter frequency divider for simplicity of explanation) is applied with 1 / 4PC, and a synchronization circuit SYN
In C2, a clock 1 / 2PC obtained as a frequency-divided output of the 1/2 frequency divider 21B is applied, and an original clock PC is applied to the synchronization circuit SYNC3.

The clock 1 having the lowest frequency using FIG.
From the state where / 4PC is being output, 1 of the original clock PC
The operation in the case of switching to the clock 1/2 PC of the frequency of / 2 will be described. FIG. 2A shows the waveform of the original clock PC. FIG. 2B shows the clock 1/1 output from the frequency divider 21B.
FIG. 2C shows the waveform of the clock 1 / 4PC output from the frequency divider 21A. In FIG. 2, the rising timing and falling timing of these clocks PC, 1 / 2PC, and 1 / 4PC are drawn so as to match, but in reality, these clocks PC, 1 / 2PC, and 1 / 4PC A phase difference is given due to a variation in the delay time of each signal path, and the rising and falling timings do not always match.

FIG. 2D shows a case where the switching command signal XA is changed to H logic at the timing T1. Switching command signal X
When A is inverted to the H logic, the preceding D-type flip-flop constituting the synchronizing circuit SYNC1 outputs H at the rising timing of the clock 1 / 4PC supplied immediately thereafter.
Read logic. Since the next flip-flop reads the output value of the preceding flip-flop at the next rising timing of the clock 1 / 4PC, the clock 1 / 4P
A delay of time 8τ of one cycle of C is given and the timing T
2, an open / close control signal XAO (FIG. 2E) is output. When the open / close control signal XAO rises to the H logic, the gate circuit 22A is controlled to be open, and a clock 1 / 4PC is output through the gate circuit 22A. Here, the timing at which the gate circuit 22A is opened is the clock 1 / 4PC
Coincides with the rising timing.

When the gate circuit 22A is outputting the clock 1 / 4PC, the switching command signal XA is output at the timing T3.
Is lowered to the L logic, and instead, the switching command signal XB is raised to the H logic as shown in FIG. 2G, in this state, the detection signal / XAO is maintained at the L logic as shown in FIG. 2H. Therefore, the prohibition gate G1 is still kept closed. Clock 1 / 4P from timing T3
When the rising edge of C is given to the synchronization circuit SYNC1 twice, the opening / closing control signal XA output from the synchronization circuit SYNC1
O (FIG. 2E) falls to L logic, and the gate circuit 22A is controlled to a closed state.

At the same time, since the detection signal / XAO (FIG. 2H) rises to H logic, the inhibit gate G1 is opened, and H logic is applied to the input of the synchronization circuit SYNC2. From the timing T4 when the detection signal / XAO rises to the H logic, the rising of the clock 1 / 2PC is synchronized with the synchronization circuit S
When given to YNC2 twice, the synchronization circuit SYNC2 inverts the open / close control signal XBO to H logic. Due to this inversion, the gate circuit 22B is controlled to be in an open state, and becomes a state of outputting a clock 1 / 2PC (FIG. 2J).

Even when the switching command signal XB is inverted to L logic and the switching command signal XC is inverted to H logic, the prohibition gate G2 is opened by detecting that the gate circuit 22B is closed,
The gate circuit 22C is controlled to be open after a lapse of one cycle of the delay of the original clock PC from that timing.
When switching from the low-frequency clock to the high-frequency clock in this way, the prohibition gates G1 and G2 detect that the gate circuits 22A and 22B that control the opening and closing of the low-frequency clock are closed, and their own synchronization circuits. SYN
The switching command signal XB or XC is applied to C2 and SYNC3, and the gate circuit 22B or 22C is controlled to be in an open state with a delay of the synchronization circuit SYNC2 and SYNC3 from the timing of this application. Can be avoided from occurring (see FIG. 7) in which a high-frequency clock is output close to immediately after.

FIG. 3 shows an operation state when switching from a high frequency to a low frequency. As shown in FIG. 3D, in a state where the original clock PC is output from the gate circuit 22C, the switching command signal XC falls to L logic at timing T5, and the switching command signal XB rises to H logic instead. When the rising edge of the original clock PC is input twice to the synchronization circuit SYNC3 after the timing T5,
Opening / closing control signal XC output from synchronization circuit SYNC3
O (FIG. 3G) is inverted to L logic. As a result, the gate circuit 22C is controlled to be closed, and the state in which the original clock PC is output disappears.

On the other hand, when the switching command signal XB is inverted to the H logic, in this case, if the inhibition gate G1 has already been opened, the clock 1 / 2PC will be synchronized with the synchronization circuit immediately after the switching command signal XB is inverted to the H logic. Applied to SYNC2. The rising edge of the clock 1 / 2PC is synchronized with the synchronization circuit SYN.
When the signal is input to C2 twice, the synchronization circuit SYNC2 operates as shown in FIG.
As shown in H, the switching control signal XBO of H logic is output. When the open / close control signal XBO is inverted to the H logic, the gate circuit 22B is controlled to be open, and the clock 1 / 2PC is output from the gate circuit 22B (FIG. 3).
I).

When switching from the high frequency to the low frequency in this manner, the synchronization circuits SYNC1, SYNC2,
Due to the existence of the delay time of the SYNC3, the timing at which the gate circuit 22B for controlling the opening and closing of the low frequency clock is opened is controlled by the gate circuit 22C for opening and closing the high frequency clock.
Is delayed from the closed timing by a time 4τ corresponding to one cycle of the clock 1 / 2PC, so that the high-frequency clock PC and the low-frequency clock 1 / 2PC are not output close to each other. As a result, the phenomenon that a pulse having a narrow pulse width is generated is avoided.

[0026]

As described above, according to the present invention, the gate circuits 22A, 22B, and 2 constituting the selection circuit 22 are provided.
2C is clock 1 / 4P controlled by its own
C, 1 / 2PC, rises in synchronization with each of PC,
Falling synchronized switching control signals XAO, XBO, X
Since the opening and closing are controlled by the CO, the phenomenon that the pulse P1 having a narrow pulse width is generated by being opened or closed in the middle of the pulse is avoided.

The gate circuit 2 is synchronized with each clock.
2A to 22C are controlled to open and close, and a synchronization circuit SYNC1
To SYNC3, the post-switching clock is output, and immediately after the pre-switching clock, the post-switching clock approaches and is output, resulting in a negative pulse P2 (see FIG. 7) having a narrow pulse width. The output phenomenon is also avoided.
Further, the period of no signal at the time of switching is limited to the period of one cycle of the clock after switching, and the period of no signal does not continue over this period. In particular, when the clock frequency is switched in the rising direction, the no-signal time gradually changes as the clock frequency is switched to the higher frequency. Well aligned.

When the clock frequency is controlled to decrease, the non-signal time tends to gradually increase each time the clock frequency is switched to a lower frequency. As a result, an effect is obtained that is well matched to the control operation for gradually reducing the current consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of a clock switching device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of FIG. 1 as in FIG. 2;

FIG. 4 is a block diagram illustrating an example of a structure of a large current consumption type semiconductor device.

FIG. 5 is a block diagram for explaining a conventional technique.

FIG. 6 is a timing chart for explaining the drawbacks of the conventional technique.

FIG. 7 is a timing chart for explaining another drawback of the conventional technique.

[Explanation of symbols]

 Reference Signs List 20 clock switching device 21 clock generation unit 22 selection circuit 23 controller 22A to 22C gate circuit SYNC1 to SYNC3 synchronization circuit G1, G2 inhibit gate XA to XC switch command signal XAO to XCO open / close control signal PC original clock 1 / 2PC original clock Clock of 1/2 frequency of 1 / 4PC Clock of 1/4 frequency of original clock

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 5/00 H03K 5/00 X 17/00 F term (Reference) 2G032 AA01 AB01 AE07 AG07 5B079 BA03 BB04 BC02 DD03 DD13 DD17 5F038 DT02 DT07 DT08 EZ20 5J055 AX11 AX40 AX66 BX03 CX00 DX01 EZ00 EZ25 EZ31 GX01 GX04 9A001 BB06 JJ45 KK37 LL05

Claims (2)

[Claims] 1. A. First Embodiment B. a clock generation unit that generates clocks of all frequencies necessary for the semiconductor device; B. a plurality of gate circuits for selecting and taking out one of the clocks of each frequency generated by the clock generation unit; B. a clock switching circuit including a controller that supplies an opening / closing control signal to the plurality of gate circuits; A clock switching device, wherein the controller comprises a plurality of synchronization circuits for synchronizing a conversion point of an open / close control signal applied to the plurality of gate circuits with a rising or falling timing of a clock of each frequency. . 2. A clock switching device according to claim 1, further comprising: a synchronization circuit that supplies an opening / closing control signal to a gate circuit that controls opening / closing of a lowest frequency clock among the plurality of synchronization circuits constituting the controller. Detects that the open / close control signal output by the low-frequency-side synchronization circuit has been inverted to a state that controls closing, and applies a switching command signal to its own synchronization circuit at the previous stage of each of the other synchronization circuits. A clock switching device characterized by having a prohibition gate provided.