JP2001274548A - Manufacturing method of ceramic wiring substrate - Google Patents

Manufacturing method of ceramic wiring substrate

Info

Publication number
JP2001274548A
JP2001274548A JP2000087164A JP2000087164A JP2001274548A JP 2001274548 A JP2001274548 A JP 2001274548A JP 2000087164 A JP2000087164 A JP 2000087164A JP 2000087164 A JP2000087164 A JP 2000087164A JP 2001274548 A JP2001274548 A JP 2001274548A
Authority
JP
Japan
Prior art keywords
via conductor
metallized via
conductor
plating film
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000087164A
Other languages
Japanese (ja)
Inventor
Morizo Nakajima
執蔵 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000087164A priority Critical patent/JP2001274548A/en
Publication of JP2001274548A publication Critical patent/JP2001274548A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To prevent breaking or peeling of a thin-film wiring conductor 3. SOLUTION: A metallized via conductor 2 is provided with a vacancy 4 having the maximum opening diameter of 20 μm or over, and a depth of 10 μm or over on its edge plane is derived to the main plane of a ceramic substrate 1 which is almost flat plate shaped. At the same time, an edge plane of the metallized via conductor 2 is coated with an electroless plated film 5 of 5-10-μm thick, after which the top plane of the electroless plated film 5 is polished mechanically along the main plane of the ceramic substrate 1 to be made level with the main plane of the ceramic substrate 1. Then, the main plane of the ceramic substrate 1 is coated with a thin-film wiring conductor 3 which is to be connected to the metallized via conductor 2. The vacancy 4 formed on the edge plane of the metallized via conductor 2 is filled partly with the electroless plated film 5 and its maximum opening diameter becomes under 20 μm, or its depth becomes under 10 μm. Accordingly, breaking and peeling of the thin-film wiring conductor 3 can be prevented and also the metallized via conductor 2 can be connected well with the thin-film wiring conductor 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、セラミック基体の
主面にメタライズビア導体を導出させるとともに、この
主面に薄膜配線導体を被着形成して成るセラミック配線
基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic wiring board in which metallized via conductors are led out to the main surface of a ceramic base and thin-film wiring conductors are formed on the main surface.

【0002】[0002]

【従来の技術】従来、高密度配線が可能なセラミック配
線基板として略平板状のセラミック基体の主面にメタラ
イズビア導体を導出させるとともに、この主面に薄膜配
線導体を被着形成して成るセラミック配線基板が知られ
ている。このセラミック配線基板によれば、配線導体を
薄膜形成技術で形成するので微細配線が可能であるとと
もに、メタライズビア導体により配線の立体化やセラッ
ミク基体の表裏両主面間の導通が可能である。このよう
なセラミック配線基板は、主面にメタライズビア導体が
導出した略平板状のセラミック基体を準備するととも
に、このセラミック基体の主面に金属薄膜をスパッタリ
ング法等の薄膜形成技術を採用して被着させ、しかる
後、この金属薄膜をフォトリソグラフィー技術を採用し
て所望のパターンにエッチングすることによって製作さ
れる。
2. Description of the Related Art Conventionally, as a ceramic wiring substrate capable of high-density wiring, a metallized via conductor is led out on a main surface of a substantially flat ceramic base, and a thin film wiring conductor is adhered and formed on the main surface. Wiring boards are known. According to this ceramic wiring board, since the wiring conductor is formed by the thin film forming technique, fine wiring is possible, and the metallized via conductor enables three-dimensional wiring and conduction between the front and back main surfaces of the ceramic substrate. Such a ceramic wiring board is prepared by preparing a substantially flat ceramic base on which a metallized via conductor is led out on the main surface and applying a thin metal film on the main surface of the ceramic base by using a thin film forming technique such as a sputtering method. Thereafter, the metal thin film is manufactured by etching the metal thin film into a desired pattern by using a photolithography technique.

【0003】なお、このようなセラミック配線基板にお
いては、薄膜配線導体を正確に形成するためにセラミッ
ク基体の主面およびメタライズビア導体の端面が平滑か
つ平坦であることが要求される。そしてそのため、通常
であれば、金属薄膜を被着させる前にセラミック基体の
主面およびメタライズビア導体の露出面を機械的研磨法
により同時に研磨している。
In such a ceramic wiring board, the main surface of the ceramic base and the end surface of the metallized via conductor are required to be smooth and flat in order to accurately form the thin film wiring conductor. Therefore, usually, the main surface of the ceramic base and the exposed surface of the metallized via conductor are simultaneously polished by a mechanical polishing method before the metal thin film is applied.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、一般的
にメタライズビア導体の内部には、メタライズビア導体
の製作過程において最大径が30μm程度以下の空孔が形
成される。そして、メタライズビア導体の端面を機械的
研磨法によって研磨すると、研磨によってこの空孔がメ
タライズビア導体の端面に露出して最大開口径が30μm
程度で、深さが15μm程度の凹部が形成されることがあ
る。このようなメタライズビア導体の端面に露出した空
孔は、その最大開口径が20μm以上で、かつその深さが
10μm以上である場合には、その上に薄膜配線導体が被
着形成されると、この薄膜配線導体に断線や剥離を発生
させやすくなる。そこで、例えば特開平3−80596号公
報には研磨されたメタライズビア導体の端面に電解めっ
き膜をセラミック基体の主面から全体的に突出する厚み
に被着させた後、この電解めっき膜の突出した部分を研
磨除去して平面とする方法が開示されている。しかしな
がら、メタライズビア導体の端面に電解めっき膜を被着
させた場合、メタライズビア導体の端面に開口する空孔
の内部には電解めっきの電界が届きにくいのでこの空孔
内には電解めっき膜が被着せずにそのため電解めっき膜
の下に空孔が残ってしまう。このように電解めっき膜の
下に空孔が残ると、例えば薄膜形成工程等において熱が
印加された場合に空孔内の水分等が気化膨張してめっき
膜にボイドや剥がれを発生させやすいという問題点を有
していた。また、電解めっき膜をセラミック基体の主面
から全体的に突出する厚みに被着させるためには、電解
めっき膜の厚みを少なくとも10μmを超える極めて厚い
ものとする必要があり、そのため電解めっき膜内に発生
する応力が極めて大きなものとなり電解めっき膜が外力
等により剥離しやすくなるという問題点を有していた。
さらに、少なくとも10μmを超える厚い電解めっき膜の
形成に長時間を要するので生産性が極めて低いという問
題点を有していた。
However, in general, holes having a maximum diameter of about 30 μm or less are formed in the metallized via conductor during the manufacturing process of the metallized via conductor. Then, when the end face of the metallized via conductor is polished by a mechanical polishing method, these holes are exposed on the end face of the metallized via conductor and the maximum opening diameter is 30 μm.
In some cases, a recess having a depth of about 15 μm may be formed. The hole exposed at the end face of such a metallized via conductor has a maximum opening diameter of 20 μm or more and a depth of
When the thickness is 10 μm or more, when a thin film wiring conductor is formed on the thin film wiring conductor, the thin film wiring conductor is liable to be disconnected or peeled. Therefore, for example, in Japanese Patent Application Laid-Open No. 3-80596, after an electrolytic plating film is applied to the end face of a polished metallized via conductor so as to project from the main surface of the ceramic substrate as a whole, A method is disclosed in which a portion which has been polished and removed is made flat. However, when the electrolytic plating film is applied to the end face of the metallized via conductor, the electrolytic plating electric field does not easily reach the inside of the hole opened on the end face of the metallized via conductor. Without this, pores remain under the electrolytic plating film. When holes are left under the electrolytic plating film in this way, for example, when heat is applied in a thin film forming step or the like, moisture or the like in the holes is likely to vaporize and expand to cause voids or peeling in the plating film. Had problems. Further, in order to apply the electrolytic plating film to a thickness projecting entirely from the main surface of the ceramic base, the thickness of the electrolytic plating film needs to be extremely thick exceeding at least 10 μm. The problem is that the stress generated in the electroplating film becomes extremely large and the electrolytic plating film is easily peeled off by external force or the like.
Further, there is a problem that productivity is extremely low because it takes a long time to form a thick electrolytic plating film exceeding at least 10 μm.

【0005】本発明は、かかる従来の問題点に鑑み案出
されたものであり、その目的は、メタライズビア導体の
端面に接続された薄膜配線導体に断線や剥離が発生する
ことがなく、メタライズビア導体と薄膜配線導体との接
続を良好に行うことが可能な、生産性の高いセラミック
配線基板の製造方法を提供することにある。
The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to prevent a thin film wiring conductor connected to an end face of a metallized via conductor from being disconnected or peeled off without causing metallization. It is an object of the present invention to provide a method of manufacturing a ceramic wiring board with high productivity, which enables good connection between a via conductor and a thin film wiring conductor.

【0006】[0006]

【課題を解決するための手段】本発明のセラミック配線
基板の製造方法は、略平板状のセラミック基体の主面
に、端面に最大開口径が20μm以上かつ深さが10μm以
上の空孔を有するメタライズビア導体を導出させるとと
もに端面に厚みが5〜10μmの無電解めっき膜を被着さ
せた後、無電解めっき膜を主面に沿って機械的に研磨し
て、この無電解めっき膜の頂面を主面と同一面とし、し
かる後、メタライズビア導体に接続させる薄膜配線導体
を主面に被着させることを特徴とするものである。
According to the method of manufacturing a ceramic wiring board of the present invention, a substantially flat ceramic base has, on its main surface, a hole having a maximum opening diameter of 20 μm or more and a depth of 10 μm or more at an end face. After the metallized via conductor is led out and an electroless plating film having a thickness of 5 to 10 μm is applied to the end face, the electroless plating film is mechanically polished along the main surface to form a top of the electroless plating film. The surface is the same as the main surface, and thereafter, a thin film wiring conductor to be connected to the metallized via conductor is attached to the main surface.

【0007】本発明のセラミック配線基板の製造方法に
よれば、最大開口径が20μm以上で、かつ深さが10μm
以上の空孔が形成されたメタライズビア導体の端面に無
電解めっき膜を被着させることから、メタライズビア導
体の端面に形成された最大開口径が20μm以上で、かつ
深さが10μm以上の空孔内に無電解めっき膜を良好に密
着させることができる。また、メタライズビア導体の端
面に被着させる無電解めっき膜は、その厚みが5〜10μ
mであることからメタライズビア導体の端面に形成され
た最大開口径が20μm以上で、かつ深さが10μm以上の
空孔を部分的に埋めて空孔の大きさを十分に小さいもの
とすることができる。さらに、無電解めっき膜の厚みが
5〜10μmであることから無電解めっき膜内に発生する
応力が小さいとともに無電解めっき膜の形成に長時間を
要しない。また、メタライズビア導体の端面に厚みが5
〜10μmの無電解めっき膜を被着させた後、この無電解
めっき膜の頂面をセラミック基体の主面と同一面となる
ように機械的に研磨し、その上にメタライズビア導体と
接続させる薄膜配線導体を被着させることから、メタラ
イズビア導体と薄膜配線導体とを良好に接続させること
ができる。
According to the method for manufacturing a ceramic wiring board of the present invention, the maximum opening diameter is 20 μm or more and the depth is 10 μm.
Since the electroless plating film is applied to the end face of the metallized via conductor in which the above holes are formed, the maximum opening diameter formed in the end face of the metallized via conductor is 20 μm or more and the depth is 10 μm or more. The electroless plating film can be satisfactorily adhered to the hole. In addition, the thickness of the electroless plating film deposited on the end face of the metallized via conductor is 5 to 10 μm.
m, the size of the hole should be sufficiently small by partially filling the hole with a maximum opening diameter of 20 μm or more and a depth of 10 μm or more formed at the end face of the metallized via conductor. Can be. Further, since the thickness of the electroless plating film is 5 to 10 μm, the stress generated in the electroless plating film is small and the formation of the electroless plating film does not require a long time. In addition, a thickness of 5 mm is applied to the end face of the metallized via conductor.
After depositing an electroless plating film of about 10 μm, the top surface of the electroless plating film is mechanically polished so as to be flush with the main surface of the ceramic substrate, and is connected to a metallized via conductor thereon. Since the thin film wiring conductor is attached, the metallized via conductor and the thin film wiring conductor can be connected well.

【0008】[0008]

【発明の実施の形態】次に、本発明を添付の図面を基に
説明する。図1〜図5は、本発明の製造方法の実施の形
態の一例を示す工程毎の断面図であり、1はセラミック
基体、2はメタライズビア導体、3は薄膜配線導体であ
る。
Next, the present invention will be described with reference to the accompanying drawings. FIGS. 1 to 5 are cross-sectional views showing steps of an example of a manufacturing method according to the present invention, wherein 1 is a ceramic substrate, 2 is a metallized via conductor, and 3 is a thin film wiring conductor.

【0009】先ず、図1に断面図で示すように、上下両
主面間を貫通する複数のメタライズビア導体2が配設さ
れた略四角平板状のセラミック基体1を準備する。
First, as shown in the sectional view of FIG. 1, a substantially square plate-shaped ceramic substrate 1 having a plurality of metallized via conductors 2 penetrating between upper and lower main surfaces is prepared.

【0010】セラミック基体1は、例えば窒化アルミニ
ウム質焼結体や酸化アルミニウム質焼結体・炭化珪素質
焼結体・窒化珪素質焼結体・ムライト質焼結体・ガラス
セラミックス等のセラミックス材料から成り、例えば窒
化アルミニウム質焼結体から成る場合であれば、窒化ア
ルミニウム・酸化イットリウム・酸化カルシウム等の原
料粉末に適当な有機バインダーおよび溶剤を添加混合し
て泥漿状となすとともに、これを従来周知のドクターブ
レード法やカレンダーロール法を採用してシート状とな
すことにより複数枚のセラミックグリーンシートを得、
これらに適当な打ち抜き加工や切断加工を施すとともに
上下に積層してセラミックグリーンシート積層体とな
し、最後にこのセラミックグリーンシート積層体を還元
雰囲気中、約1700℃の温度で焼成することによって製作
され、通常であれば、その上下両主面が中心線平均粗さ
RaでRa>0.1μmの粗面となっている。
The ceramic base 1 is made of a ceramic material such as an aluminum nitride sintered body, an aluminum oxide sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, and a glass ceramic. For example, in the case of a sintered body made of aluminum nitride, an appropriate organic binder and a solvent are added to a raw material powder such as aluminum nitride, yttrium oxide, and calcium oxide to form a slurry, which is conventionally known. By using the doctor blade method and the calendar roll method to form a sheet, a plurality of ceramic green sheets are obtained,
It is manufactured by subjecting them to appropriate punching and cutting processes and laminating them vertically to form a ceramic green sheet laminate, and finally firing this ceramic green sheet laminate at a temperature of about 1700 ° C in a reducing atmosphere. Usually, the upper and lower main surfaces are rough surfaces having a center line average roughness Ra of Ra> 0.1 μm.

【0011】また、セラミック基体1の上下主面間を貫
通するメタライズビア導体2は、タングステンやモリブ
デン・銅・銀等の金属粉末メタライズから成り、セラミ
ック基体1の上下両主面間の電気的な導通をとる導電路
として機能する。このようなメタライズビア導体2は、
セラミック基体1用のセラミックグリーンシートにメタ
ライズビア導体2を配設するための貫通孔を穿孔すると
ともに、この貫通孔内にメタライズビア導体2用の金属
ペーストを充填し、これをセラミックグリーンシートの
積層体とともに焼成することによってセラミック基体1
の上下両主面間を貫通するようにして配設され、通常で
あれば、その内部に最大径が30μm程度の空孔4が複数
形成されている。
The metallized via conductor 2 penetrating between the upper and lower main surfaces of the ceramic substrate 1 is made of metal powder of metal such as tungsten, molybdenum, copper, silver or the like, and is electrically connected between the upper and lower main surfaces of the ceramic substrate 1. It functions as a conductive path for conducting. Such a metallized via conductor 2
A through hole for arranging the metallized via conductor 2 is formed in the ceramic green sheet for the ceramic substrate 1, and a metal paste for the metallized via conductor 2 is filled in the through hole. By firing together with the body, the ceramic substrate 1
In this case, a plurality of holes 4 having a maximum diameter of about 30 μm are formed therein.

【0012】なお、セラミックグリーンシートへの貫通
孔の穿孔は、例えば打ち抜き金型による穿孔やレーザー
ビームによる穿孔が採用される。また、メタライズビア
導体2用の金属ペーストは、タングステン等の金属粉末
に適当な有機バインダーおよび溶剤を添加混合して適当
な粘度に調整することによって製作される。そして、メ
タライズビア導体2用の金属ペーストをセラミックグリ
ーンシートに設けた貫通孔内に充填するには、例えばセ
ラミックグリーンシートに設けた貫通孔に対応した貫通
孔を有する金属マスクをセラミックグリーンシート上に
載置し、このマスク上に金属ペーストを供給するととも
にスキージを摺動させ、スキージの摺動圧力により金属
ペーストをセラミックグリーンシートの貫通孔内に押し
出す方法が採用される。このような打ち抜きや充填は各
セラミックグリーンシート毎に行われてもよいし、複数
枚のセラミックグリーンシートを積層した後に行われて
もよい。
For the perforation of the through holes in the ceramic green sheet, for example, perforation by a punching die or perforation by a laser beam is employed. The metal paste for the metallized via conductor 2 is manufactured by adding and mixing an appropriate organic binder and a solvent to a metal powder such as tungsten and adjusting the viscosity to an appropriate viscosity. To fill the metal paste for the metallized via conductor 2 into the through-holes provided in the ceramic green sheet, for example, a metal mask having a through-hole corresponding to the through-hole provided in the ceramic green sheet is placed on the ceramic green sheet. A method is employed in which the metal paste is placed on the mask, the metal paste is supplied, and the squeegee is slid, and the metal paste is extruded into the through holes of the ceramic green sheet by the sliding pressure of the squeegee. Such punching and filling may be performed for each ceramic green sheet, or may be performed after laminating a plurality of ceramic green sheets.

【0013】次に、図2に断面図で示すように、セラミ
ック基体1の上下両主面を機械的研磨によりその中心線
平均粗さRaが0.05μm以下の平滑な面となるように研
磨する。このとき、研磨によりメタライズビア導体2の
空孔4が露出してメタライズビア導体2の端面に最大開
口径が20μm程度以上で深さが10μm程度以上の凹部が
形成される。なお、このような研磨には例えばラッピン
グマシーンや平面研削盤が用いられる。
Next, as shown in the sectional view of FIG. 2, the upper and lower main surfaces of the ceramic substrate 1 are polished by mechanical polishing so that the center line average roughness Ra becomes a smooth surface of 0.05 μm or less. . At this time, the holes 4 of the metallized via conductor 2 are exposed by polishing, and a concave portion having a maximum opening diameter of about 20 μm or more and a depth of about 10 μm or more is formed on the end face of the metallized via conductor 2. For such polishing, for example, a lapping machine or a surface grinder is used.

【0014】そして次に、図3に要部拡大断面図で示す
ように、メタライズビア導体2の端面に例えば無電解ニ
ッケル−ホウ素めっき膜や無電解ニッケル−リンめっき
膜等の無電解めっき膜5をその厚みが5〜10μmとなる
ように被着させる。このとき、無電解めっき膜5は、被
めっき物の形状にかかわらず略均一の厚みに被着される
性質を有するので、メタライズビア導体2の端面に形成
された最大開口径が20μm以上、深さが10μm以上の空
孔4の内部にこの空孔4を部分的に埋めるように良好に
被着される。また、無電解めっき膜5は、その厚みが5
〜10μmと薄いことから無電解めっき膜5を形成する際
に無電解めっき膜5内に発生する応力が極めて大きなも
のとなることはないので無電解めっき膜5に剥離が発生
しにくい。さらに、無電解めっき膜5は、その厚みが5
〜10μmと薄いことから無電解めっき膜5を被着させる
のに長時間を要することがないのでセラミック配線基板
の生産性が大きく低下することはない。なお、メタライ
ズビア導体2の端面に無電解めっき膜5を5〜10μmの
厚みに被着させるには、例えば、無電解めっき膜5がニ
ッケル−ホウ素めっき膜から成る場合であれば、例えば
ニッケル供給源である硫酸ニッケルと、還元剤であるジ
メチルアミンボランとを主成分とし、錯化剤として酢酸
・マロン酸・コハク酸・プロピオン酸またはこれらのナ
トリウム塩のうちいずれか2〜3種類と、pH調整剤と
して塩化アンモニウムと、安定剤としてチオ二酢酸また
は酢酸鉛とを添加混合して製作しためっき液を用いる。
このめっき液中にメタライズビア導体2が配設されたセ
ラミック基体1をpHが5〜7程度、液温が55〜65℃程
度の条件で30〜60分程度浸漬することにより、メタライ
ズビア導体2の端面に無電解めっき膜5を5〜10μmの
厚みに被着させることができる。
Next, as shown in an enlarged sectional view of a main part in FIG. 3, an electroless plating film 5 such as an electroless nickel-boron plating film or an electroless nickel-phosphorus plating film is formed on the end face of the metallized via conductor 2. Is applied so that its thickness is 5 to 10 μm. At this time, since the electroless plating film 5 has a property of being applied to a substantially uniform thickness regardless of the shape of the object to be plated, the maximum opening diameter formed on the end face of the metallized via conductor 2 is 20 μm or more, The hole 4 having a thickness of 10 μm or more is satisfactorily adhered so as to partially fill the hole 4. The electroless plating film 5 has a thickness of 5 mm.
Since the thickness is as small as 10 μm, the stress generated in the electroless plating film 5 when the electroless plating film 5 is formed does not become extremely large, so that the electroless plating film 5 hardly peels. Further, the electroless plating film 5 has a thickness of 5 mm.
Since it is as thin as 10 μm, it does not take a long time to apply the electroless plating film 5, so that the productivity of the ceramic wiring substrate is not greatly reduced. In order to apply the electroless plating film 5 to the end face of the metallized via conductor 2 to a thickness of 5 to 10 μm, for example, if the electroless plating film 5 is made of a nickel-boron plating film, for example, nickel supply Nickel sulfate as a source and dimethylamine borane as a reducing agent as main components, and as a complexing agent, 2 to 3 kinds of acetic acid / malonic acid / succinic acid / propionic acid or a sodium salt thereof; A plating solution prepared by adding and mixing ammonium chloride as a regulator and thiodiacetic acid or lead acetate as a stabilizer is used.
The metallized via conductor 2 is immersed in the plating solution for about 30 to 60 minutes at a pH of about 5 to 7 and a solution temperature of about 55 to 65 ° C. for about 30 to 60 minutes. The electroless plating film 5 can be applied to the end surface of the substrate with a thickness of 5 to 10 μm.

【0015】次に、図4に要部拡大断面図で示すよう
に、メタライズビア導体2の端面に被着させた無電解め
っき膜5のうち、セラミック基体1主面からの突出した
部分をセラミック基体1の主面に沿って研磨してその頂
面がセラミック基体1の主面と同一面となるように研磨
する。これにより無電解めっき膜5の一部がセラミック
基体1主面から突出することが解消されるとともに、空
所4が最大開口径が20μm未満、または深さが10μm未
満の小さなものとなる。なお、このような研磨にはラッ
ピングマシーンや平面研削盤等が用いられる。
Next, as shown in an enlarged sectional view of a main part in FIG. 4, a portion of the electroless plating film 5 adhered to the end face of the metallized via conductor 2 protruding from the main surface of the ceramic base 1 is made of ceramic. Polishing is performed along the main surface of the base 1 so that the top surface is flush with the main surface of the ceramic base 1. As a result, a part of the electroless plating film 5 is prevented from protruding from the main surface of the ceramic base 1, and the cavity 4 has a small maximum opening diameter of less than 20 μm or a depth of less than 10 μm. Note that a lapping machine, a surface grinder, or the like is used for such polishing.

【0016】そして最後に、図5に要部拡大断面図で示
すように、セラミック基体1の主面に薄膜配線導体3を
メタライズビア導体2に接続されるようにして被着形成
する。この場合、メタライズビア導体2の端面に形成さ
れた、最大開口径が20μm以上で、かつ深さが10μm以
上の空孔4は無電解めっき膜5で部分的に充填されてそ
の最大開口径が20μm未満、またはその深さが10μm未
満となっているとともに、無電解めっき膜5の頂面がセ
ラミック基体1の主面と同一面となっているので、この
上に形成される薄膜配線導体3に断線や剥離等が発生す
ることはなく、メタライズビア導体2と薄膜配線導体3
とが極めて良好に接続される。
Finally, as shown in an enlarged sectional view of the main part in FIG. 5, a thin film wiring conductor 3 is formed on the main surface of the ceramic base 1 so as to be connected to the metallized via conductor 2. In this case, holes 4 having a maximum opening diameter of 20 μm or more and a depth of 10 μm or more formed on the end face of metallized via conductor 2 are partially filled with electroless plating film 5 so that the maximum opening diameter is reduced. Since the depth is less than 20 μm or less than 10 μm and the top surface of the electroless plating film 5 is the same as the main surface of the ceramic substrate 1, the thin film wiring conductor 3 No disconnection or peeling occurs in the metallized via conductor 2 and the thin film wiring conductor 3.
Are connected very well.

【0017】なお、セラミック基体1の主面にメタライ
ズビア導体2に接続させるように被着形成される薄膜配
線導体3は、例えばセラミック基体1側から密着層とバ
リア層と主導体層とを積層した多層薄膜で形成されてお
り、密着層としてはチタンやクロム・タンタル・ニオブ
・ニクロム・窒化タンタル等が、バリア層としては白金
やモリブデン・パラジウム・ロジウム・ルテニウム・チ
タン−タングステン合金等が、主導体層としては、銅や
金等が使用され、例えば密着層としてチタンを、バリア
層として白金を、主導体層として金を用いる場合であれ
ば、厚みが100〜2000オングストローム程度のチタン層
と、厚みが500〜10000オングストローム程度の白金層
と、厚みが1000〜50000オングストローム程度の金層と
をセラミック基体1の主面にスパッタリング法やイオン
プレーティング法,蒸着法等の公知の薄膜成形技術を採
用することによって被着させるとともに、これらを公知
のフォトリソグラフィー技術を用いて所定のパターンに
エッチングすることによって形成される。
The thin-film wiring conductor 3 formed on the main surface of the ceramic substrate 1 so as to be connected to the metallized via conductor 2 is formed by, for example, laminating an adhesion layer, a barrier layer, and a main conductor layer from the ceramic substrate 1 side. Titanium, chromium, tantalum, niobium, nichrome, tantalum nitride, etc., as the adhesion layer, and platinum, molybdenum, palladium, rhodium, ruthenium, titanium-tungsten alloy, etc. as the barrier layer. As the body layer, copper or gold or the like is used, for example, titanium as the adhesion layer, platinum as the barrier layer, if using gold as the main conductor layer, a titanium layer having a thickness of about 100 to 2,000 angstroms, A platinum layer having a thickness of about 500 to 10,000 angstroms and a gold layer having a thickness of about 1,000 to 50,000 angstroms are formed on the main surface of the ceramic substrate 1. Ttaringu method or an ion plating method, together with the depositing by employing known thin film forming technique deposition method, is formed by etching a predetermined pattern using these known photolithography technique.

【0018】かくして、本発明のセラミック配線基板の
製造方法によれば、薄膜配線導体3に断線や剥離がな
く、メタライズビア導体2と薄膜配線導体3とが良好に
接続されたセラミック配線基板を生産性高く製造するこ
とができる。
Thus, according to the method for manufacturing a ceramic wiring board of the present invention, a ceramic wiring board in which the metallized via conductors 2 and the thin film wiring conductors 3 are well connected without disconnection or peeling of the thin film wiring conductors 3 is produced. It can be manufactured with high efficiency.

【0019】[0019]

【発明の効果】本発明のセラミック配線基板の製造方法
によれば、最大開口径が20μm以上で、かつ深さが10μ
m以上の空孔が形成されたメタライズビア導体の端面に
厚みが5〜10μmの無電解めっき膜を被着させることか
ら、メタライズビア導体の端面に形成された最大開口径
が20μm以上で、かつ深さが10μm以上の空孔内に無電
解めっき膜を良好に密着させてこの空孔を部分的に埋
め、これを無電解めっき膜の頂面がセラミック基体の主
面と同一面となるように研磨することにより空孔を最大
開口径が20μm未満、または深さが10μm未満の小さい
ものとすることができ、この上にメタライズビア導体と
接続させる薄膜配線導体を被着させることから、メタラ
イズビア導体と薄膜配線導体とを良好に接続させること
ができる。また、メタライズビア導体の端面に被着され
る無電解めっき膜は、その厚みが5〜10μmと薄いこと
から、無電解めっき膜に大きな応力が発生して剥離する
ことはないとともに、その形成に長時間を要することも
ない。従って、本発明によれば、薄膜配線導体に断線や
剥離が発生することがなく、メタライズビア導体と薄膜
配線導体とが良好に接続されたセラミック配線基板を生
産性高く製造することができる。
According to the method for manufacturing a ceramic wiring board of the present invention, the maximum opening diameter is 20 μm or more and the depth is 10 μm.
Since a thickness of 5 to 10 μm of the electroless plating film is applied to the end face of the metallized via conductor in which holes of m or more are formed, the maximum opening diameter formed on the end face of the metallized via conductor is 20 μm or more, and The electroless plating film is satisfactorily adhered to the holes having a depth of 10 μm or more to partially fill the holes, and the top surface of the electroless plating film is flush with the main surface of the ceramic substrate. By polishing, the maximum opening diameter can be reduced to less than 20 μm or the depth can be reduced to less than 10 μm, and the thin film wiring conductor to be connected to the metallized via conductor is deposited thereon, so that metallization is performed. The via conductor and the thin-film wiring conductor can be connected well. In addition, since the electroless plating film applied to the end face of the metallized via conductor has a small thickness of 5 to 10 μm, the electroless plating film does not peel off due to generation of a large stress. It doesn't take long. Therefore, according to the present invention, a ceramic wiring board in which the metallized via conductor and the thin film wiring conductor are well connected can be manufactured with high productivity without causing disconnection or peeling of the thin film wiring conductor.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のセラミック配線基板の製造方法の実施
の形態の一例を説明するための断面図である。
FIG. 1 is a cross-sectional view for explaining an example of an embodiment of a method for manufacturing a ceramic wiring board of the present invention.

【図2】本発明のセラミック配線基板の製造方法の実施
の形態の一例を説明するための断面図である。
FIG. 2 is a cross-sectional view for explaining an example of an embodiment of a method for manufacturing a ceramic wiring board according to the present invention.

【図3】本発明のセラミック配線基板の製造方法の実施
の形態の一例を説明するための要部拡大断面図である。
FIG. 3 is an enlarged sectional view of a main part for explaining an example of an embodiment of a method for manufacturing a ceramic wiring board of the present invention.

【図4】本発明のセラミック配線基板の製造方法の実施
の形態の一例を説明するための要部拡大断面図である。
FIG. 4 is an enlarged sectional view of a main part for describing an example of an embodiment of a method for manufacturing a ceramic wiring board of the present invention.

【図5】本発明のセラミック配線基板の製造方法の実施
の形態の一例を説明するための要部拡大断面図である。
FIG. 5 is an enlarged sectional view of a main part for explaining an example of an embodiment of a method for manufacturing a ceramic wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・セラミック基体 2・・・・・メタライズビア導体 3・・・・・薄膜配線導体 4・・・・・空孔 5・・・・・無電解めっき膜 1 Ceramic substrate 2 Metallized via conductor 3 Thin film wiring conductor 4 Hole 5 Electroless plating film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 略平板状のセラミック基体の主面に、端
面に最大開口径が20μm以上かつ深さが10μm以上
の空孔を有するメタライズビア導体を導出させるととも
に前記端面に厚みが5〜10μmの無電解めっき膜を被
着させた後、前記無電解めっき膜を前記主面に沿って機
械的に研磨して、該無電解めっき膜の頂面を前記主面と
同一面とし、しかる後、前記メタライズビア導体に接続
させる薄膜配線導体を前記主面に被着させることを特徴
とするセラミック配線基板の製造方法。
1. A metallized via conductor having a hole having a maximum opening diameter of not less than 20 μm and a depth of not less than 10 μm at an end face is derived from a main surface of a substantially flat ceramic base, and the end face has a thickness of 5 to 10 μm. After the electroless plating film is applied, the electroless plating film is mechanically polished along the main surface so that the top surface of the electroless plating film is flush with the main surface. A method of manufacturing a ceramic wiring board, comprising: attaching a thin film wiring conductor to be connected to the metallized via conductor to the main surface.
JP2000087164A 2000-03-27 2000-03-27 Manufacturing method of ceramic wiring substrate Pending JP2001274548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000087164A JP2001274548A (en) 2000-03-27 2000-03-27 Manufacturing method of ceramic wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000087164A JP2001274548A (en) 2000-03-27 2000-03-27 Manufacturing method of ceramic wiring substrate

Publications (1)

Publication Number Publication Date
JP2001274548A true JP2001274548A (en) 2001-10-05

Family

ID=18603215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000087164A Pending JP2001274548A (en) 2000-03-27 2000-03-27 Manufacturing method of ceramic wiring substrate

Country Status (1)

Country Link
JP (1) JP2001274548A (en)

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Publication number Priority date Publication date Assignee Title
WO2016068248A1 (en) * 2014-10-29 2016-05-06 京セラ株式会社 Circuit board and electronic device provided with same
JPWO2016068248A1 (en) * 2014-10-29 2017-08-03 京セラ株式会社 Circuit board and electronic device having the same
CN107112291A (en) * 2014-10-29 2017-08-29 京瓷株式会社 Circuit substrate and the electronic installation for possessing it
EP3200224A4 (en) * 2014-10-29 2018-02-14 Kyocera Corporation Circuit board and electronic device provided with same
US10147662B2 (en) 2014-10-29 2018-12-04 Kyocera Corporation Circuit board and electronic device provided with same
US10507514B2 (en) 2015-09-16 2019-12-17 Arconic Inc. Rivet feeding apparatus
WO2020138221A1 (en) * 2018-12-26 2020-07-02 京セラ株式会社 Wiring substrate, electronic device, and electronic module
CN113228259A (en) * 2018-12-26 2021-08-06 京瓷株式会社 Wiring substrate, electronic device, and electronic module
JPWO2020138221A1 (en) * 2018-12-26 2021-11-04 京セラ株式会社 Wiring boards, electronic devices and electronic modules
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US11735507B2 (en) 2018-12-26 2023-08-22 Kyocera Corporation Wiring substrate, electronic device, and electronic module
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