JP2001274307A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2001274307A
JP2001274307A JP2000088812A JP2000088812A JP2001274307A JP 2001274307 A JP2001274307 A JP 2001274307A JP 2000088812 A JP2000088812 A JP 2000088812A JP 2000088812 A JP2000088812 A JP 2000088812A JP 2001274307 A JP2001274307 A JP 2001274307A
Authority
JP
Japan
Prior art keywords
semiconductor chip
resist
plating
lead frame
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000088812A
Other languages
Japanese (ja)
Inventor
Kenji Ishimatsu
憲治 石松
Zenichi Ishikawa
善一 石川
Kenji Katsuki
謙治 香月
Hisashi Yasunaga
尚志 安永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP2000088812A priority Critical patent/JP2001274307A/en
Publication of JP2001274307A publication Critical patent/JP2001274307A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device in which a masking jig is eliminated, and a partial plating of a lead frame is performed with superior productivity and further with profile precision even if a partial plating portion is fine, and a mounting of a semiconductor chip and an electric connection of the semiconductor chip with an inner lead are performed with superior workability and reliability, and further an adhesion of a sealing resin to the lead frame is excellent and the reliability is superior. SOLUTION: A lead frame 1 is coated with a resist 8, the resist 8 at a plating required portion of the lead frame 1 coated with the resist 8 is eliminated by a laser irradiation, a plating 9 is performed at the eliminated portion, a semiconductor chip 10 is mounted to a semiconductor chip mounted part 2, an inner lead 3 is electrically connected to the semiconductor chip 10 via a bonding wire 11, and the inside of the inner lead 3 in which the resist 8 except for the eliminated portion is still coated is sealed with a resin to manufacture a semiconductor device.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関する。
The present invention relates to a method for manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】リードフレームを用いた半導体装置はパ
ッドに半導体チップを搭載し、該半導体チップの電極と
インナーリードをボンディングワイヤーで電気的に接続
し、インナーリード、パッド、半導体チップ、及びボン
ディングワイヤーを樹脂等で封止されて製造される。
2. Description of the Related Art In a semiconductor device using a lead frame, a semiconductor chip is mounted on a pad, electrodes of the semiconductor chip are electrically connected to inner leads by bonding wires, and the inner leads, pads, semiconductor chip, and bonding wires are connected. Is sealed with a resin or the like.

【0003】前記パッドは半導体チップを信頼性高く接
着して搭載するために金、銀等の貴金属がめっきされ
る。また、インナーリードにはボンディングワイヤーと
の接続作業を容易にし、且つ接続の信頼性を高めるため
に前記貴金属がめっきされる。これらのめっきは貴金属
の無駄な使用をなくし、コスト低減を図るうえから必要
箇所のみに行われる。
The pads are plated with a noble metal such as gold or silver in order to mount the semiconductor chip with high reliability. In addition, the noble metal is plated on the inner leads in order to facilitate the connection operation with the bonding wire and to enhance the reliability of the connection. These platings are performed only on necessary portions in order to eliminate wasteful use of precious metals and reduce costs.

【0004】従来の部分めっきは、マスクを製作してマ
スキング治具とバックプレートでめっきが必要なインナ
ーリード先端部、及びパッド部以外の部分を覆い、めっ
き液をかけて、或いはめっき液中に通して前記めっき必
要箇所のみに行われる。
In the conventional partial plating, a mask is manufactured, and a masking jig and a back plate cover portions other than the tip of the inner lead and the pad which need to be plated, and apply a plating solution or apply a plating solution. The plating is performed only at the necessary portions.

【0005】[0005]

【この発明が解決しようとする課題】部分めっきは前記
のようにして行われることから、めっきを施す形状、即
ちめっき形状に対応したマスク等のマスキング治具を被
めっきリードフレームの形状や、めっき形状が変わる毎
に製作せねばならず、手間を要し、また高度の熟練技術
を要する。さらに半導体装置の小型化につれリードフレ
ームは小さくなりインナーリードに部分めっきされる領
域は微細になり前記マスクの製作は難しくなっている。
Since the partial plating is performed as described above, the shape to be plated, that is, a masking jig such as a mask corresponding to the plating shape is used to change the shape of the lead frame to be plated or the plating. It has to be manufactured every time the shape changes, it takes time and requires a high level of skill. Further, as the size of the semiconductor device is reduced, the size of the lead frame becomes smaller, and the area of the inner lead that is partially plated becomes finer.

【0006】貴金属がめっきされたパッドには半導体チ
ップが搭載され、該半導体チップの電極とインナーリー
ド先端部がボンディングワイヤーで接続され、インナー
リード以内が樹脂等で封止され半導体装置が製造され
る。該樹脂封止過程では樹脂封止成形後、封止金型から
製品の取り出しを容易にするために離型剤が樹脂中に含
まれ、リードフレームとの密着性を低下させている。ま
た、封止樹脂とリードフレームとは熱膨張の差により、
接着界面に隙間が使用経過により生じることがあり、半
導体装置の信頼性が損なわれる。
A semiconductor chip is mounted on a pad plated with a noble metal, the electrode of the semiconductor chip is connected to the tip of an inner lead by a bonding wire, and the inside of the inner lead is sealed with a resin or the like to manufacture a semiconductor device. . In the resin encapsulation process, after the resin encapsulation molding, a release agent is included in the resin to facilitate removal of the product from the encapsulation mold, thereby reducing the adhesion to the lead frame. Also, due to the difference in thermal expansion between the sealing resin and the lead frame,
A gap may be formed in the bonding interface due to the use of the semiconductor device, and the reliability of the semiconductor device is impaired.

【0007】さらに、半導体装置は小型や薄手化が最近
ますます進んでいる状況下において前記封止樹脂とリー
ドフレームの密着性の問題は解決せねばならぬ大きな課
題である。
[0007] Further, in the situation where semiconductor devices are becoming smaller and thinner, the problem of the adhesion between the sealing resin and the lead frame is a major problem to be solved.

【0008】本発明はマスク等のマスキング治具が不要
で、リードフレームの部分めっきを生産性よく、且つ、
部分めっき箇所が微細であっても形状精度よく行なえ、
半導体チップの搭載、及び半導体チップとインナーリー
ドとの電気的接続が作業性よく、且つ信頼性よく行え、
さらに封止樹脂とリードフレームの密着性がよく、信頼
性のすぐれた半導体装置を得ることを目的とする。
According to the present invention, a masking jig such as a mask is unnecessary, and partial plating of a lead frame can be performed with high productivity.
Even if the partial plating part is fine, it can be performed with good shape accuracy,
The mounting of the semiconductor chip and the electrical connection between the semiconductor chip and the inner lead can be performed with good workability and reliability,
It is another object of the present invention to obtain a semiconductor device having good adhesion between a sealing resin and a lead frame and excellent reliability.

【0009】[0009]

【課題を解決する手段】本発明の要旨は、リードフレー
ムにレジストをコーティングし、該コーティングされた
リードフレームのめっき必要箇所のレジストをレーザー
照射により除去し、前記除去箇所にめっきを施し、半導
体チップをリードフレームの半導体チップ搭載部に搭載
し、インナーリードと半導体チップの電極をボンディン
グワイヤーを介して電気的に接続し、前記除去した箇所
以外のレジストがコーティングされたままのインナーリ
ード、半導体チップ搭載部、半導体チップ、及びボンデ
ィングワイヤーを樹脂封止することを特徴とする半導体
装置の製造方法にある。
SUMMARY OF THE INVENTION The gist of the present invention is to coat a resist on a lead frame, remove the resist at a required portion of the coated lead frame by laser irradiation, apply plating to the removed portion, and form a semiconductor chip. Is mounted on the semiconductor chip mounting portion of the lead frame, and the inner lead and the electrode of the semiconductor chip are electrically connected via a bonding wire. A method for manufacturing a semiconductor device, comprising sealing a part, a semiconductor chip, and a bonding wire with a resin.

【0010】[0010]

【発明の実施の形態】次に、本発明を1実施例について
図面を参照して詳細に述べる。図面において、1はリー
ドフレームで、半導体チップを搭載するパッド2に連続
してインナーリード3が形成され、前記インナーリード
3に連ねてアウターリード4が形成されている。5はタ
イバーでインナーリード3とアウターリード4の間に形
成され樹脂封止する際、樹脂止めするものである。6は
サポートバーでパッド2の角部に接続して形成されてい
る。7はガイドホールである。これらのリードパターン
はプレス法、エッチング法、或いは、これらの併合法に
より形成される。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention; In the drawing, reference numeral 1 denotes a lead frame, an inner lead 3 is formed continuously with a pad 2 on which a semiconductor chip is mounted, and an outer lead 4 is formed continuously with the inner lead 3. Reference numeral 5 denotes a tie bar formed between the inner lead 3 and the outer lead 4 and used for resin sealing when sealing with resin. Reference numeral 6 denotes a support bar connected to the corner of the pad 2. 7 is a guide hole. These lead patterns are formed by a pressing method, an etching method, or a combination thereof.

【0011】リードフレーム1には全面にめっき液に濡
れても溶けない例えばエポキシ系、ポリイミド系等から
なるレジストがコーティングされる。該コーティングは
ロールによるコート、スプレーによるコート、フィルム
コート、或いはこれらを組み合わせてなされ、リードの
側面にもなされる。
The lead frame 1 is coated on the entire surface with a resist made of, for example, an epoxy-based or polyimide-based resist which does not dissolve even when wet with a plating solution. The coating is performed by roll coating, spray coating, film coating, or a combination thereof, and is also applied to the side surface of the lead.

【0012】レジスト8がコーティングされたリードフ
レーム1はめっき必要箇所、この実施例ではインナーリ
ード先端部3aの表面 及びパッド中央部2aの表面
に、レーザー例えばYAGレーザー、炭酸ガスレーザー
等を照射して該表面のレジスト8のみを除去する。レー
ザー照射のビームは光径を例えば0.1μm以下に調整
でき、且つ、照射した箇所のみのレジストを除去できる
ので、めっきが必要箇所のみのレジストを形状精度よく
除去できる。また、レジストがつけられたままの箇所に
はその後のめっきが付かないのでめっきマスクは不要で
ある。
The lead frame 1 coated with the resist 8 is irradiated with a laser, for example, a YAG laser, a carbon dioxide gas laser, or the like, at a portion requiring plating, in this embodiment, a surface of the inner lead tip 3a and a surface of the pad center 2a. Only the resist 8 on the surface is removed. The beam of the laser beam can be adjusted to a light diameter of, for example, 0.1 μm or less, and the resist can be removed only from the irradiated portion, so that the resist can be removed only from the portion requiring plating with high precision. Further, since the subsequent plating is not applied to the portion where the resist is still applied, a plating mask is unnecessary.

【0013】めっき必要箇所のレジスト8を除去された
リードフレーム1はめっき浴、例えば金めっき浴、銀め
っき浴、アンチモンめっき浴等に通され、または、金め
っき液、銀めっき液、或いはアンチモンめっき液等のめ
っき液を吹きかけられ、電気めっき等により貴金属がめ
っき9される。
The lead frame 1 from which the resist 8 has been removed is passed through a plating bath, for example, a gold plating bath, a silver plating bath, an antimony plating bath, or a gold plating solution, a silver plating solution, or an antimony plating solution. Noble metal is plated 9 by spraying a plating solution such as a solution.

【0014】めっき9はインナーリード先端部3a、パ
ッド中央部2aのめっき必要箇所以外にはレジスト8が
付けられているので、めっきが付かず、また、側面もれ
等を生じることなくめっき必要箇所のみに図3に示すよ
うに部分めっきされる。
Since the plating 9 is provided with a resist 8 except for the portions where the plating is required at the tip 3a of the inner lead and the center portion 2a of the pad, the plating 9 is not plated, and the plating is not required without any side leakage. Only one is partially plated as shown in FIG.

【0015】前記部分めっきはリードフレーム1に先に
Ni、Sn、Cu等の適宜な金属を下地めっきした後、
或いは下地めっきを施すことなく行える。
In the partial plating, an appropriate metal such as Ni, Sn, or Cu is first plated on the lead frame 1 as a base,
Alternatively, it can be performed without applying a base plating.

【0016】部分めっきの後、インナーリード3の先端
がパッド2に接続している部分をプレス等で切除し、パ
ッド2から分離されるとともに、パッド2の側面を形成
する。該形成したパッド2に半導体チップ10を超音波
溶接接合、或いは接着材等により接着し搭載する。
After the partial plating, the portion where the tip of the inner lead 3 is connected to the pad 2 is cut off by a press or the like, separated from the pad 2 and the side surface of the pad 2 is formed. The semiconductor chip 10 is mounted on the formed pad 2 by ultrasonic welding or bonding with an adhesive or the like.

【0017】搭載された半導体チップ10はその電極と
インナーリード3の先端部の部分めっき9した箇所とを
ボンディングワイヤー11により電気的に接続される。
該ボンディングではインナーリード3の先端部のボンデ
ィング箇所に貴金属がめっきされているので信頼性よ
く、且つ作業性よくなされる。
The mounted semiconductor chip 10 is electrically connected by a bonding wire 11 to its electrode and the portion of the tip of the inner lead 3 which is partially plated 9.
In this bonding, the noble metal is plated at the bonding portion at the tip of the inner lead 3, so that the bonding is performed with good reliability and workability.

【0018】次いで、前記レーザ照射で除去した箇所以
外にはレジスト8がついたままのインナーリード3、パ
ッド2、該パッド2に搭載された半導体チップ10、及
びボンディングワイヤー11を樹脂封止する。樹脂封止
は例えばポリイミド樹脂、エポキシ樹脂等でなされる
が、前記インナーリード3、パッド2には部分めっきし
た箇所以外にレジスト8がついているので、封止樹脂1
2に例え離型材が含まれていてもインナーリード3、パ
ッド2との界面は悪影響を受けずレジスト8と密着性よ
く前記封止樹脂12が接合し封止される。これにより半
導体装置13が製造される。
Next, the inner leads 3, the pads 2, the semiconductor chip 10 mounted on the pads 2, and the bonding wires 11 are sealed with a resin except for the portions removed by the laser irradiation. Resin sealing is performed using, for example, polyimide resin, epoxy resin, or the like.
Even if the mold release material 2 is included, the interface between the inner lead 3 and the pad 2 is not adversely affected, and the sealing resin 12 is bonded to the resist 8 with good adhesion and sealed. Thereby, the semiconductor device 13 is manufactured.

【0019】樹脂封止はこの実施例ではインナーリード
3及びパッド2の底面も樹脂内に含まれるように行って
いるが、前記インナーリード3及びパッド2の底面を樹
脂封止底面から露出するように封止してもよい。
In this embodiment, the resin sealing is performed such that the bottom surfaces of the inner leads 3 and the pads 2 are also included in the resin. However, the bottom surfaces of the inner leads 3 and the pads 2 are exposed from the resin sealing bottom surface. May be sealed.

【0020】また、この実施例ではリードフレーム1に
はリードとしてインナーリード3とアウターリード4を
形成しているが、本発明はインナーリード3だけを形成
したリードフレーム1を用いる半導体装置にも適用で
き、図6に示すようリードを半導体装置の外部に出さな
いタイプの半導体装置13にも適用できる。
In this embodiment, the inner lead 3 and the outer lead 4 are formed on the lead frame 1 as leads. However, the present invention is also applicable to a semiconductor device using the lead frame 1 on which only the inner lead 3 is formed. The present invention can also be applied to a semiconductor device 13 of a type in which leads are not exposed outside the semiconductor device as shown in FIG.

【0021】前記実施例ではレーザー照射によるリード
フレーム1のレジスト8の除去はインナーリード先端部
3aとパット中央部2aの双方を行ったが、必要に応じ
ていずれか一方を行ってもよい。
In the above embodiment, the removal of the resist 8 of the lead frame 1 by laser irradiation is performed on both the inner lead end portion 3a and the pad central portion 2a, but either one may be performed as necessary.

【0022】[0022]

【発明の効果】本発明によれば、リードフレームにレジ
ストをコーティングし、該コーティングしたリードフレ
ームのめっき必要箇所のみのレジストをレーザー照射に
より除去し、該除去箇所に貴金属をめっきし、半導体チ
ップをリードフレームの半導体チップ搭載部に搭載し、
インナーリードと半導体チップの電極をボンディングワ
イヤーを介して接続し、前記部分めっき箇所以外にはレ
ジストがコーティングされたままのインナーリード以内
を樹脂で封止して半導体装置を製造する。従って、部分
めっきはマスキング治具を製作することなく行え、ま
た、めっき必要箇所が微細であってもその部分のレジス
トは位置精度よく除去でき、貴金属を部分めっきでき
る。さらに部分めっきを施した以外の箇所にはレジスト
がついているので、封止樹脂との密着性は強く、樹脂剥
離等は発生せず信頼性にすぐれた半導体装置が得られる
等の作用効果がある。
According to the present invention, a lead frame is coated with a resist, the resist is removed from only the plating-required portions of the coated lead frame by laser irradiation, and the removed portion is plated with a noble metal to form a semiconductor chip. Mounted on the semiconductor chip mounting part of the lead frame,
The semiconductor device is manufactured by connecting the inner lead and the electrode of the semiconductor chip via a bonding wire, and sealing the resin in the inner lead except for the partially plated portion while the resist is still coated. Therefore, partial plating can be performed without manufacturing a masking jig, and even if a portion requiring plating is fine, the resist in that portion can be removed with high positional accuracy, and the noble metal can be partially plated. Further, since the resist is applied to portions other than the portions subjected to the partial plating, the adhesiveness with the sealing resin is strong, and there is an operational effect that a highly reliable semiconductor device is obtained without occurrence of resin peeling or the like. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の1実施例においてリードフレームへの
レジストのコーティングを示す図。
FIG. 1 is a diagram showing coating of a lead frame with a resist in one embodiment of the present invention.

【図2】本発明の1実施例においてリードフレームのめ
っき必要箇所のレジストをレーザ照射で除去した図。
FIG. 2 is a view showing a portion of the lead frame where plating is required removed by laser irradiation in one embodiment of the present invention.

【図3】本発明の1実施例においてリードフレームのめ
っき必要箇所に部分めっきした図。
FIG. 3 is a view showing a part of a lead frame in which plating is required in one embodiment of the present invention.

【図4】本発明の1実施例においてインナーリード先端
部、パッドを形成し半導体チップを搭載した図。
FIG. 4 is a diagram showing a state in which a tip of an inner lead and a pad are formed and a semiconductor chip is mounted in one embodiment of the present invention.

【図5】本発明の1実施例において製造した半導体装置
を示す図。
FIG. 5 is a diagram showing a semiconductor device manufactured in one embodiment of the present invention.

【図6】本発明の他の実施例による半導体装置を示す
図。
FIG. 6 is a diagram showing a semiconductor device according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 リードフレーム 2 パッド 3 インナーリード 4 アウターリード 5 タイバー 6 サポートバー 7 ガイドレール 8 レジスト 9 めっき 10 半導体チップ 11 ボンディングワイヤー 12 封止樹脂 13 半導体装置 DESCRIPTION OF SYMBOLS 1 Lead frame 2 Pad 3 Inner lead 4 Outer lead 5 Tie bar 6 Support bar 7 Guide rail 8 Resist 9 Plating 10 Semiconductor chip 11 Bonding wire 12 Sealing resin 13 Semiconductor device

───────────────────────────────────────────────────── フロントページの続き (72)発明者 安永 尚志 北九州市八幡西区小嶺2丁目10番1号 株 式会社三井ハイテック内 Fターム(参考) 4M109 AA01 BA01 CA21 FA06 FA07 5F067 AA01 DC00 DC13 DC14 DE06 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takashi Yasunaga 2-10-1 Komine, Yawatanishi-ku, Kitakyushu F-term (reference) 4M109 AA01 BA01 CA21 FA06 FA07 5F067 AA01 DC00 DC13 DC14 DE06

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 リードフレームにレジストをコーティン
グし、該コーティングされたリードフレームのめっき必
要箇所のレジストをレーザー照射により除去し、前記除
去箇所にめっきを施し、半導体チップをリードフレーム
の半導体チップ搭載部に搭載し、インナーリードと半導
体チップの電極をボンディングワイヤーを介して電気的
に接続し、前記除去した箇所以外のレジストがコーティ
ングされたままのインナーリード、半導体チップ搭載
部、半導体チップ、及びボンディングワイヤーを樹脂封
止することを特徴とする半導体装置の製造方法。
1. A method for coating a lead frame with a resist, removing the resist at a portion of the lead frame required for plating by laser irradiation, plating the removed portion, and mounting the semiconductor chip on a semiconductor chip mounting portion of the lead frame. And the inner lead and the electrode of the semiconductor chip are electrically connected via a bonding wire, and the inner lead, the semiconductor chip mounting portion, the semiconductor chip, and the bonding wire remain coated with the resist other than the removed portion. A method for manufacturing a semiconductor device, comprising:
【請求項2】 リードフレームにコーティングしたレジ
ストの前記レーザー照射による除去箇所がインナーリー
ドの先端部、半導体チップ搭載部の少なくとも一方であ
ることを特徴とする請求項1記載の半導体装置の製造方
法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein a portion of the resist coated on the lead frame removed by the laser irradiation is at least one of a tip portion of an inner lead and a semiconductor chip mounting portion.
JP2000088812A 2000-03-28 2000-03-28 Method for manufacturing semiconductor device Pending JP2001274307A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000088812A JP2001274307A (en) 2000-03-28 2000-03-28 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000088812A JP2001274307A (en) 2000-03-28 2000-03-28 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2001274307A true JP2001274307A (en) 2001-10-05

Family

ID=18604638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000088812A Pending JP2001274307A (en) 2000-03-28 2000-03-28 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2001274307A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180410A (en) * 2005-12-28 2007-07-12 Mitsui High Tec Inc Method of manufacturing lead frame and lead frame manufactured using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180410A (en) * 2005-12-28 2007-07-12 Mitsui High Tec Inc Method of manufacturing lead frame and lead frame manufactured using the same

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