JP2001274258A - Pair transistor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce dispersion of characteristics due to a manufacture process in a pair transistor circuit having two pair transistors A and B having almost the same characteristics. SOLUTION: A transistors A and B are constituted of four partial transistors a1 to a4 and transistors b1 to b4, which are connected in parallel and whose sizes are almost equal. The transistors a1 and a2 are arranged on the outer side of an upper stage, the transistors b1 and b2 are arranged on the outer side of a lower stage, and the transistors a3 and a4 are arranged on the inner side. Dummy transistors, having almost the same dimensions are formed on the outer side of the transistors A and B constituting a pair transistor circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a paired transistor circuit including two transistors having substantially the same characteristics, and more particularly to a method of arranging the same.

[0002]

2. Description of the Related Art As semiconductor circuits, semiconductor devices having the same characteristics are often used in pairs. The semiconductor element to be paired now will be temporarily described as a MOSFET. For example, in the differential amplifier circuit shown in FIG. 3, when two pair transistors 1 having substantially the same characteristics are AMOSFETs and BMOSFETs, the AMOSFETs 2 and BMOSFET3 are connected with a common source. 4 and 5 are the gates of A and B MOSFETs 2 and 3, respectively. If the potential of the input V ₁ of the gate 4 of the AMOSFET ₂ is higher than that of the gate 5 of the BMOSFET 3, the potential of the output becomes the ground potential, and conversely, the potential of the input V ₁ of the gate 4 of the AMOSFET 2 becomes that of the gate 5 of the BMOSFET 3. if lower than V _2, the output potential is higher. As a method for arranging such pair transistor circuits, the following method is generally used.

[0003] AMOSFET and BMOSFET have respective sizes.
Two equal partial transistors a₁MOSFET and a_TwoMOSFET
 , B₁MOSFET and b_TwoComposed of MOSFETs,
They are arranged in two rows and two rows of kanji tags. FIG.
It is a top view which shows the electrode arrangement of an example. Upper left a₁M
OSFET 12, upper right b₁MOSFET 13 is placed on the lower left_TwoM
OSFET 14, lower right_TwoMOSFET 15 each other
Place in difference. a₁D, a_TwoD is a₁MOSFET 1
2, a_TwoA drain electrode of MOSFET 15;₁S, a_TwoS
Is a₁MOSFET 12, a_TwoSource voltage of MOSFET 15
It is a pole. 11 is an activity in which current switching is performed.
Sex region. Each source electrode and drain in the active region 11
Not shown on the surface layer of the semiconductor substrate
An impurity region of the opposite conductivity type is formed. b₁D, b _TwoD,
b₁S, b_TwoThe same applies to S.

Then, a ₁ MOSFET 12 and a ₂ MOSFET 15
Drain electrode is connected to the drain wiring 7, and
The drain electrodes of the b ₁ MOSFET 13 and the b ₂ MOSFET 14 are connected to the drain wiring 8. a ₁ MOSFET 12, a ₂ M
The source electrodes of the OSFET 15, b ₁ MOSFET 13 and b ₂ MOSFET 14 are connected to the source line 6. 4 is a ₁ MOSFET
And a ₂ are gate wirings of MOSFET ₂ , and 5 is b ₁ MOSFET 13
And b ₂ MOSFET 14. It can be easily understood that the a ₁ MOSFET and the a ₂ MOSFET and the b ₁ MOSFET and the b ₂ MOSFET may be replaced with each other.

[0005]

In the differential amplifier circuit shown in FIG. 3, when the output operating point is set to the middle of the power supply voltage, the gate 5 as the non-inverting input terminal and the gate as the inverting input terminal are used. The potential difference between the four (hereinafter referred to as an offset voltage) depends on the characteristic variation of the MOS type semiconductor elements of the transistor circuit used for the input stage and the current mirror circuit used for the load, ie, the MOSFETs 2 and 3. The characteristic variations of the MOSFETs 2 and 3 are mainly caused by manufacturing variations of the MOSFETs 2 and 3.

The manufacturing variations of the MOSFETs 2 and 3 are as follows.
It occurs during the manufacturing process and includes, for example, asymmetry due to a shadow effect at the time of ion implantation. other,
For example, with respect to a gate electrode made of a polycrystalline silicon film, a wiring, and a wiring made of an Al-Si alloy, an Al-Si-Cu alloy, etc., a processing shape is changed due to a difference in the degree of density of a pattern which occurs during etching, particularly dry etching. In addition, there is also a phenomenon that a change occurs in dimensions, such as a dimensional variation due to a so-called loading effect or the like.

An object of the present invention is to provide a pair transistor circuit which can reduce the variation in characteristics of a MOS type semiconductor element due to a manufacturing process, for example, which causes the above-mentioned offset voltage.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a pair transistor circuit having two pair transistors A and B having substantially the same characteristics.
When the transistors are composed of four partial transistors, a _{1 to} a ₄ transistors, and b _{1 to} b ₄ transistors, which are connected in parallel and are substantially equal in size, and four are arranged at equal intervals in upper and lower two stages, A ₁ and a ₂ transistors are arranged outside the upper stage, b ₁ and b ₂ transistors are arranged inside the upper stage, b ₃ and b ₄ transistors are arranged outside the lower stage, and a ₃ and a ₄ transistors are arranged inside the lower stage. And

The loading effect that causes the variation in the characteristics of the pair transistor circuit is mainly caused by the density of the pattern between the outer part and the inner part of the element. What is necessary is just to include a part and an inner part. Therefore, according to the above, the dimensional variation due to the loading effect or the like is reduced, and the characteristic variation is also suppressed.

Particularly, the A and B transistors are MOSFETs
, The source regions of the a-transistor and the b-transistor of adjacent partial transistors in the same stage are common and / or the drain regions of the inner b ₁ , b ₂ , a ₃ and a ₄ transistors are common. By doing so, there is an advantage that the element area of the pair transistor circuit can be reduced.

By connecting all the source electrodes, a pair transistor circuit having a common source can be realized. The same can be said for a pair transistor circuit having a common drain. Further, on both outer sides of the respective four portions transistors disposed in upper and lower, a, b partial transistor and may be placed about the same size of the partial transistors (c ₁ to c ₄ transistors).

In this case, since the a and b partial transistors are both disposed inside, the dimensional variation due to the loading effect or the like is further reduced, and the characteristic variation is also suppressed. The c _{1 to} c ₄ transistors are MO
In the case of the SFET, if the drain regions of the adjacent c-transistor and a-transistor and the c-transistor and the b-transistor in the same stage are made common, there is an advantage that the element area of the pair transistor circuit can be reduced. The potential can be stabilized by short-circuiting the source electrode and the gate electrode of the c _{1 to} c ₄ transistors and connecting them to a power supply or grounding.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. [Example 1] FIG. 1 is an electrode arrangement diagram of a pair transistor circuit showing a first embodiment of the present invention, which is seen through a protective film and an insulating film. For example, the input-stage pair transistor circuit 1 of the differential amplifier circuit of FIG. 3 corresponds to the pair transistor circuit of the present embodiment.

In FIG. 1, a pair MOSFET is replaced with an AMOSF.
ET, when the BMOSFET, AMOSFET is the same size as a four equally divided portions MOSFET a ₁ MOSFET 32, a
₂ consists of _{MOSFET 35, a 3 MOSFET 37,} a 4 MOSFET 38. Similarly, the BMOSFETs are b ₁ MOSFETs 33 and b ₂ MOSFETs 3 which are partial MOSFETs divided into four equal parts.
4, consisting of _{b 3 MOSFET 36, b 4 MOSFET} 39. Reference numeral 31 denotes an active region where current switching is performed.

The a ₁ MOSFET 32 has a drain electrode a ₁ D, a source electrode a ₁ b ₁ S, and a gate electrode therebetween. a
₂ MOSFET 35 has a drain electrode a ₂ D and a source electrode a ₂ b
Having the ₂ S and between the gate electrode. b ₁ MOSFET 33
Has a drain electrode b ₁ b ₂ D, a source electrode a ₁ b ₁ S, and a gate electrode therebetween. The b ₂ MOSFET 33 includes a drain electrode b ₁ b ₂ D, a source electrode a ₂ b ₂ S, and a gate electrode therebetween. Below the source electrode and the drain electrode in the active region 31, a source region and a drain region of a conductivity type opposite to that of the semiconductor substrate are formed, but are omitted in the drawing. A small square in each electrode represents a contact hole.

The source electrodes a ₁ b ₁ S are a ₁ MOSFET 32 and b
₁ Shared with MOSFET 33. Source electrode a ₂ b ₂ S
Is shared by the a ₂ MOSFET 35 and the b ₂ MOSFET 34. The drain electrodes b ₁ b ₂ D are b ₁ MOSFET 33 and b ₂ MOS
Shared with the FET 34. Thus, the element area of the pair transistor circuit can be reduced. The same applies to the lower stage. The AMOSFET and the BMOSFET are configured to be rotationally symmetric about the center.

Reference numeral 24 denotes a ₁ MOSFET 3 constituting the AMOSFET.
2, a ₂ MOSFET 35, a ₃ MOSFET 37, a ₄ MOSFET 38
This is the gate wiring connecting the gate electrodes of FIG. Similarly, reference numeral 25 denotes a b ₁ MOSFET 33 and a b ₂ MOSFET which constitute a BMOSFET.
34, a gate wiring connecting the gate electrodes of the b ₃ MOSFET 36 and the b ₄ MOSFET 39. 27 is a ₁ MOSFET 32, a ₂ MOSFET 35, a ₃ MOSFET 3
7, a ₄ is a drain wiring connecting the drain electrode of the MOSFET 38. Similarly, reference numeral 28 denotes b which constitutes the BMOSFET.
₁ MOSFET 33, b ₂ MOSFET 34, b ₃ MOSFET 36, b ₄
This is a drain wiring connecting the drain electrode of the MOSFET 39.

Reference numeral 26 denotes a source wiring connecting source electrodes of all the partial MOSFETs. Source wiring 2
6, drain wirings 27 and 28 and gate wirings 24 and 25
Are separated from each other by an insulating film (not shown). With such an arrangement, the outer a ₁ MOSFET 32, a ₂
The electrodes of the MOSFET 35, b ₃ MOSFET 36, b ₄ MOSFET 39 are connected to the inner b ₁ MOSFET 33, b ₂ MOSFET 34, a ₃ MOSF
Although the ET 37 and the a ₄ MOSFET 38 receive a different loading effect, the AMOSFET and the BMOSFET have substantially the same effect.

Therefore, the characteristics of the two MOS semiconductor elements can be made uniform by setting the partial transistor of the BMOSFET in the upper stage and the partial transistor of the AMOSFET in the lower stage. Further, even if the a ₁ MOSFET 32 receives a characteristic change due to a large loading effect, the a ₂ MOSFET 35 and the a ₃ MOSFET
37, since there is a ₄ MOSFET 38, the influence of the entire FIG. 4
Can be suppressed as compared with the case of the arrangement.

The offset voltage of the actually fabricated pair transistor of the arrangement of FIG. 1 is about 1 mV, which is reduced to about 1/5 as compared with that of the conventional arrangement of FIG. Example 2 FIG. 2 is a plan view showing an electrode arrangement of a paired transistor according to a second embodiment of the present invention.

AMOSFET and B constituting a pair transistor
MOSFETs each have four partial transistors a _{1 to} a _1
4 MOSFET 52, 54, 57, 58, b _{1 to} b ₄ MOSFET 5
The structure of 2, 53, 56 and 59 is the same as that of the first embodiment, and the arrangement is almost the same. 51 is an active area. The difference from the first embodiment is that dummy transistors c _{1 to} c ₄ MOSFETs 60 to 63 are provided outside the partial transistors.
Is formed.

That is, the upper row is c ₁ , a ₁ , b ₁ ,
In the order of b ₂ , a ₂ , and c ₂ MOSFET, the lower row shows c ₃ , b ₃ , and a
₃ , a ₄ , b ₄ , and c ₄ MOSFETs are arranged in this order. Dummy transistors c ₁ ~c ₄ MOSFET 60~63 be a ₁ ~
a ₄ MOSFET, the same dimension as b ₁ ~b ₄ MOSFET. However, dummy transistors c _{1 to} c ₄ MOSFET 60
63 have a MOSFET structure,
It does not operate as an FET. In that sense, it is a dummy transistor.

The c ₁ MOSFET 60 comprises a source electrode c ₁ S, a drain electrode a ₁ c ₁ D, and a gate electrode therebetween. The same applies to the other c _{2 to} c ₄ MOSFETs 61 to 63. However, as shown in FIG. ₂ , c ₁ MOSFET 60 and a ₁ MOSFET 5
2 and the drain electrode a ₁ c ₁ D is shared, and a ₂ MOSFET 5
5 and the drain electrode a ₂ c ₂ D of the c ₂ MOSFET 61 are made common. Thus, the element area of the pair transistor circuit can be reduced.

The c _{1 to} c ₄ MOSFETs 60 to 63 have M
Since it does not operate as an OSFET, the source electrode and the gate electrode are short-circuited and connected to a power supply or a ground potential to prevent instability. As described in the first embodiment, the MOS type semiconductor elements at both ends are connected to the inner MO.
A loading effect different from that of the S-type semiconductor device is obtained. Therefore, a ₁ , a ₂ MOSFETs 52, 55, b ₃ , b ₄ MO
Dummy c _{1 to} c ₄ MOSFETs 6 outside the SFETs 56 and 59
By providing 0 to 63, a _{1 to} a ₄ MOSFETs 52, 55, 57, 58, and b constituting the AMOSFET and the BMOSFET are provided.
₁ ~b ₄ MOSFET 53,54,56,59 are all become the inner part transistor, it receives a substantially uniform loading effect. As a result, the AMOSFET and the BMOSFET can be a pair transistor circuit having no characteristic variation.

In the above embodiment, an example of a pair transistor circuit having a common source has been described. However, the present invention is not limited thereto, and a circuit having a common drain and a pair having a symmetric characteristic are desired. It goes without saying that it is effective for a transistor circuit.

[0026]

The present invention described above, according to the present invention is, A constituting the transistor pair circuits, the B transistors, four partial transistor equal approximately the size connected in parallel, respectively, a ₁ ~a ₄ transistor, b ₁ When these are composed of _four transistors and four are arranged at equal intervals in the upper and lower stages, a ₁ and a ₂ transistors are provided outside the upper stage,
Transistors b ₁ and b ₂ are arranged inside the transistor, transistors b ₃ and b ₄ are arranged outside the lower stage, and a ₃ and a ₄ are arranged inside the transistor.
By arranging the transistors symmetrically, A, B
Transistors can be affected by the same process variation, and the device characteristics of the paired transistors can be made uniform.

Further, by providing dummy transistors having substantially the same dimensions outside the A and B transistors forming the paired transistor circuit, the loading effect received by the partial transistors is made uniform, and the device characteristics of the paired transistors are further uniformed. Is possible.

[Brief description of the drawings]

FIG. 1 is a plan view showing an electrode arrangement according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an electrode arrangement according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a differential amplifier circuit.

FIG. 4 is an electrode arrangement diagram of a conventional pair transistor circuit.

[Explanation of symbols]

Reference Signs List 1 pair transistor circuit 2 AMOSFET 3 BMOSFET 4, 24, 44 Gate wiring of AMOSFET 5, 25, 45 Gate wiring of BMOSFET 6, 26, 46 Source wiring 7, 27, 47 Drain wiring of AMOSFET 8, 28, 48 Drain of BMOSFET Wiring 11, 31, 51 Active region 12, 32, 52 Partial transistor of AMOSFET (a ₁ M
OSFET) 13, 33, 53 BMOSFET partial transistor (b ₁ M
OSFET) 14, 34, 54 BMOSFET partial transistor (b ₂ M
OSFET) 15, 35, 55 AMOSFET partial transistor (a ₂ M
OSFET) 16, 36, 56 BMOSFET partial transistor (b ₃ M
OSFET) 17, 37, 57 AMOSFET partial transistor (b ₃ M
OSFET) 18, 38, 58 AMOSFET partial transistor (b ₄ M
OSFET) 19, 39, 59 BMOSFET partial transistor (a ₄ M
OSFET) 60 c ₁ MOSFET 61 c ₂ MOSFET 62 c ₃ MOSFET 63 c ₄ MOSFET

Claims (12)

[Claims] 1. A substantially the same properties of A, in the pair transistor circuit having a B two paired transistors, A, four parts transistors equal approximately sized B transistor connected in parallel, respectively, a ₁ ~a ₄ transistors,
b _{1 to} b ₄ transistors, and when four are arranged at equal intervals in two upper and lower stages, a ₁ , a
The _second transistor, the b _1, b ₂ transistor arranged inside the b _3, b ₄ transistors outside the lower pair transistor circuit, characterized in that placing a _3, a ₄ transistor therein. 2. The pair transistor according to claim 1, wherein the A and B transistors are MOSFETs, and the source regions of the adjacent a transistor and b transistor in the same stage have a common source region. 3. The inner b ₁ and b ₂ transistors, respectively.
_3. The pair transistor according to claim 2, wherein the drain regions of the transistors a ₃ and a ₄ are common. 4. The pair transistor according to claim 3, wherein all the source electrodes are connected. 5. The semiconductor device according to claim 1, wherein the A and B transistors are MOSFETs, and the drain regions of the adjacent a transistor and b transistor in the same stage have a common drain region.
A pair transistor as described. 6. The inner b ₁ and b ₂ transistors, respectively.
a _3, a pair transistor according to claim 5, characterized in that a common source region of a ₄ transistor. 7. The pair transistor according to claim 6, wherein all drain electrodes are connected. On both outer sides of 8. Each was placed in the upper and lower four parts transistors, and wherein placing a, partial transistor having substantially the same size as the part b transistor (c ₁ to c ₄ transistors) A pair transistor circuit according to claim 1. 9. The pair according to claim 8, wherein the c _{1 to} c ₄ transistors are MOSFETs, and the drain region of the adjacent c transistor and the a transistor and the drain region of the c transistor and the b transistor in the same stage are common. Transistor. 10. The pair transistor circuit according to claim 9, wherein the source electrode and the gate electrode of the c _{1 to} c ₄ transistors are short-circuited. 11. The pair transistor circuit according to claim 10, wherein the source electrodes of the c _{1 to} c ₄ transistors are connected to a power supply. 12. The pair transistor circuit according to claim 10, wherein the source electrodes of the c _{1 to} c ₄ transistors are grounded.