JP2001274214A - Method for evaluating semiconductor silicon wafer and method for controlling manufacturing process - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method with which only the quality of semiconductor silicon wafers can be evaluated by properly setting conditions for manufacturing MOS capacitors and conditions of TDDB measurement, when MOS capacitors are formed on a semiconductor silicon wafer and to provide a method for controlling the process of their manufacturing, by feeding back the results obtained by the evaluating method to the manufacturing process of semiconductor silicon wafers. SOLUTION: MOS capacitors are formed on the surface of a semiconductor silicon wafer and the quality of the semiconductor silicon wafer is evaluated, on the basis of the accidental defects (β mode destruction) rate of Weibull plots obtained by performing a TDDB measurement of the MOS capacitors. Also, the manufacturing process of semiconductor wafers is controlled on the basis of the accidental defects (β mode destruction) rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS (Metal Oxide Semiconductor) formed on a semiconductor silicon wafer.
r) A method for evaluating the quality of a semiconductor silicon wafer by performing TDDB measurement of a capacitor and a method for managing a manufacturing process thereof.

[0002]

2. Description of the Related Art TDDB (Time Dependent Dielectric)
Breakdown) measurement is widely known as a reliability evaluation of a gate oxide film of a MOS transistor formed using a semiconductor silicon wafer, and is particularly indispensable for the development and improvement of a thin film oxide film of 10 nm or less and reliability evaluation. Technology.

[0003] Generally, evaluation by TDDB measurement includes a process of manufacturing a large number of MOS capacitors on a wafer,
Applying a specific stress (voltage or current) to the capacitor and measuring the time until the oxide film undergoes dielectric breakdown. The reliability (life) of the MOS capacitor is determined by Weibull plotting the measurement result. To evaluate.

Here, the Weibull plot is a log scale of the stress application time t (or the charge amount Qbd leading to the dielectric breakdown), with the vertical axis representing the index W calculated from the cumulative failure rate F of the MOS capacitor having the dielectric breakdown. Is plotted on the horizontal axis. The index W is calculated by the following equation.

W = ln [ln {1 / (1-F)}]

When Weibull plotting the actual measurement results, usually, an initial failure (hereinafter sometimes referred to as α mode destruction or simply α mode) and an accidental failure (hereinafter referred to as β mode destruction or simply β mode) ) And intrinsic defects (hereinafter sometimes referred to as γ-mode destruction or simply γ-mode) indicating the limit of the material. It is determined that the longer the time is, the better the capacitor is.

However, the measurement result not only depends on the quality of the silicon wafer (the quality of the oxide film), but also naturally depends on the manufacturing conditions and the measurement conditions of the MOS capacitor for measurement. It was difficult to evaluate only the quality of the wafer.

[0008]

Conventionally, it has been practiced to form a MOS capacitor on a semiconductor silicon wafer and perform TDDB measurement to evaluate the quality of the wafer.
Since the evaluation included the influence of the DB measurement conditions, it was not to evaluate only the quality of the wafer. In addition, no detailed investigation has been performed on how these conditions affect the results of the TDDB measurement.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to appropriately set MOS capacitor fabrication conditions and TDDB measurement conditions when forming MOS capacitors on a semiconductor silicon wafer. An object of the present invention is to provide a method capable of evaluating only the quality of a wafer, and to feed back a result obtained by the evaluation method to a semiconductor silicon wafer manufacturing process to manage the manufacturing process.

[0010]

In order to solve the above-mentioned problems, the invention according to claim 1 of the present invention comprises forming a MOS capacitor on the surface of a semiconductor silicon wafer,
A method for evaluating a semiconductor silicon wafer, wherein the quality of the semiconductor silicon wafer is evaluated based on a random failure (β mode destruction) rate of a Weibull plot obtained by performing TDDB measurement of an S capacitor.

Thus, the TDDB of the MOS capacitor
Evaluating the random failure (β-mode fracture) rate obtained by the measurement eliminates the influence of the difference in growth conditions (Grown-in defect) of the silicon single crystal produced on the semiconductor silicon wafer and the difference in the processing condition. Can be used to evaluate the wafer quality.

In this case, as described in claim 2, it is preferable to judge a semiconductor silicon wafer having a random failure rate of 20% or less as a non-defective product. This is because there is a close relationship between the accidental failure rate exceeding 20% and a sudden change in wafer processing conditions.

The thickness of the oxide film when forming the MOS capacitor may be 10 to 30 nm (claim 3), and the electrode may have a thickness of 200 to 400 nm in which the dopant is diffused by a diffusion method without using ion implantation. By using an electrode formed by performing the wet etching of the polysilicon described above (claim 4), the quality of the wafer can be evaluated without being strongly affected by the manufacturing conditions of the MOS capacitor.

Further, by performing the TDDB measurement at a temperature of 25 to 150 ° C. (claim 5), the TDDB measurement can be performed at a normal room temperature (20 to 25 ° C.) without affecting the evaluation of the wafer quality.
Measurement time) can be shortened as compared to the measurement of

Further, according to a sixth aspect of the present invention, a semiconductor capacitor is formed on the surface of a semiconductor silicon wafer by forming a MOS capacitor and performing a TDDB measurement of the MOS capacitor to determine a random failure (β mode breakdown) rate of a Weibull plot. A method for managing a manufacturing process of a semiconductor silicon wafer, wherein the manufacturing process of the wafer is managed.

As described above, the TDDB of the MOS capacitor
By evaluating the random failure (β-mode destruction) rate obtained by the measurement, it is possible to evaluate the wafer quality due to the difference in the processing conditions of the semiconductor silicon wafer, and this evaluation result is fed back to the processing conditions. By
The manufacturing process of the silicon wafer can be managed.

Hereinafter, the present invention will be described in more detail. The inventor manufactured a MOS capacitor on a semiconductor silicon wafer (hereinafter, sometimes referred to as a silicon wafer or a wafer) manufactured under various manufacturing conditions,
Evaluation by TDDB measurement by Weibull plots revealed that if the α mode, β mode, and γ mode are appropriately defined, the quality of the silicon wafer can be evaluated.

Specifically, the single crystal growth conditions for producing a silicon wafer, that is, the difference in the density of Grown-in defects, which are small crystal defects introduced into a single crystal during single crystal growth, are α The present invention was completed by recognizing that the difference in processing conditions (for example, polishing conditions and cleaning conditions) of the wafer appears remarkably in the β mode.

FIG. 5 illustrates this, in which TDDB measurements were performed on three types of wafers (A, B, C) under different manufacturing conditions, and Qbd (Charge To Breakdown: the amount of charge leading to dielectric breakdown) was 5 mC each. / cm ² less than, 5mC / cm
^More 5C / cm less than ^2, 5C / cm ² or more and became the region α mode, a comparison β mode, the failure rate is defined as γ mode.

Here, the wafers (A, B, C) are obtained by changing the single crystal pulling conditions (crystal 1, crystal 2) and the cleaning conditions (cleaning 1, cleaning 2) during the polishing process. A is (crystal 1, cleaning 1), wafer B is (crystal 2, cleaning 1), wafer C is (crystal 2, cleaning 2).
It is. From the results in FIG. 5, it can be clearly understood that the difference in the crystal appears in the α mode, and the difference in the cleaning (processing conditions) appears in the β mode.

Next, in order to obtain optimum MOS fabrication conditions and TDDB measurement conditions for evaluating only the quality of the wafer, the effects of these conditions on the TDDB characteristics were investigated.

(Gate Oxidation Conditions) Regarding the TDDB characteristic, the Qbd value at which the intrinsic breakdown of the gate oxide film occurs depends on whether the wafer to be evaluated is a CZ wafer or an epitaxial wafer, as the oxidation temperature becomes higher and the dryness becomes higher. It is known that pyrogenic oxidation is higher than oxidation.

As for the oxide film thickness, as shown in FIG. 6, the Qbd value at which intrinsic destruction occurs becomes smaller as the oxide film thickness becomes smaller, and the slope becomes considerably gentle when the oxide film thickness is 10 nm or less. It was found that it was difficult to clearly distinguish between the γ mode and the β mode. Therefore, to clearly distinguish between the γ mode and the β mode, 10n
An oxide film having a thickness of not less than m is preferable. On the other hand, in consideration of the ease of sample preparation and the ease of management of the apparatus, it can be said that a dry oxidation has a maximum thickness of about 30 nm.

(Gate Electrode Forming Conditions) FIG. 7 shows the relationship between the thickness of phosphorus-doped polysilicon used as an electrode and the sheet resistance. The sheet resistance was measured at 800 ° C. in a nitrogen gas atmosphere containing 3% of oxygen after polysilicon deposition.
It was measured after annealing at 900 ° C. and 1000 ° C. for 30 minutes.

In order not to damage the polysilicon film as the phosphorus-doped electrode, it is preferable to use an ordinary gas-phase diffusion method instead of the ion implantation method when doping phosphorus. If dry etching is used when patterning the polysilicon film, wet etching is likely to occur, so that wet etching is preferably used.

From the point of electrical measurement, the smaller the sheet resistance of the electrode is, the better. However, it is confirmed that if the resistance is 50 Ω / □ or less, it does not significantly affect the measurement result. The film thickness is preferably 200 nm or more, and preferably 400 nm or less in consideration of the time required for forming an electrode.

(TDDB Measurement Conditions) FIG.
9 shows an example of stress current dependence of TDDB characteristics of a MOS capacitor having a thickness of 5 nm and a gate area of 4 mm ² . It can be seen that the sharp rise indicating the γ mode shifts to the low Qbd side as the stress current increases, and the inclination tends to be gentle. FIG. 9 shows the maximum Qbd (Qbdmax:
It shows the dependency of the longest life) on the stress current.

Qbdmax tends to decrease as the stress current increases. This indicates that while the destruction of the MOS capacitor is affected by the magnitude of the stress current, the effect can be almost neglected if the stress current is reduced to some extent. Therefore, considering from the standpoint of evaluating only wafer quality, stress current is desirably 0.01 A / cm ² or less, it is appropriate approximately 0.05 A / cm ² in consideration of the measurement time.

FIG. 10 shows an example of the results of an investigation on the influence of the measurement temperature on the TDDB measurement (25 nm oxide film thickness, gate area 4 mm ² , stress current 0.01 A / cm ² ) of an epitaxial wafer having a diameter of 200 mm. It was found that increasing the measurement temperature was only an effect of shifting the TDDB characteristic to the left, and did not affect the slope itself. Therefore, in order to shorten the measurement time, it is more preferable to increase the measurement temperature than to increase the stress current (1).
The time at 00 ° C. measurement is about 1/3 of the time at 25 ° C. measurement. However, if the temperature is too high, there is a concern that the original purpose of evaluating only the wafer quality may be adversely affected. Therefore, the temperature is preferably 150 ° C. or lower.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but the present invention is not limited to these embodiments.
FIG. 4 shows an example of a manufacturing flow of a MOS capacitor suitable for the method for evaluating a semiconductor silicon wafer of the present invention. For the purpose of evaluating only wafer quality, FIG.
As shown in the above, sacrificial oxidation and LOCOS (LOCal Oxidatio
n of Silicon) is preferably performed and the number of manufacturing steps is reduced.

In FIG. 4, first, the wafer to be evaluated is cleaned to remove contaminants on the surface (FIG. 4 (a)).
An oxide film to be a gate oxide film of the MOS capacitor is formed (FIG. 4B). In this case, an oxide film can be directly formed without performing cleaning. The oxide film thickness is preferably from 10 to 30 nm for the above-mentioned reason.

Next, a polysilicon film heavily doped with phosphorus is deposited (FIG. 4C). The phosphorus-doped polysilicon film can be deposited by, for example, supplying a source gas of polysilicon such as monosilane and supplying a phosphine (PH ₃ ) gas at the same time using a reduced pressure vapor phase growth furnace. The thickness of the polysilicon is 200 to
400 nm is appropriate.

Then, in order to form an electrode using this polysilicon film, a photoresist is applied to the surface thereof and patterning is performed (FIG. 4D). After that, the resist is used as a mask to remove the polysilicon other than the portions that will become the electrodes. At this time, if dry etching is used, the electrodes are likely to be damaged.
It is preferable to perform wet etching using an etching solution of hydrofluoric acid, nitric acid, acetic acid, and water (FIG. 4).
(E)). Finally, the MOS capacitor is obtained by removing the photoresist (FIG. 4F).

Usually, several tens to several hundreds of such MOS capacitors can be formed per wafer, so that these can be measured under arbitrarily selected TDDB measurement conditions, and a Weibull plot can be performed to determine the α mode, β mode and γ mode can be evaluated. At this time, TD
As DB measurement conditions, a measurement temperature of 25 to 150 ° C. slightly higher than room temperature, for example, 100 ° C. is selected, and a stress current of about 0.01 to 0.05 A / cm ² is selected. Highly reliable measurement is possible in time.

The Qbd value as a boundary between the α mode, the β mode, and the γ mode depends on the measurement conditions.
Less than C / cm ² (α mode), 5 mC / cm ² or more and 5 C
/ Cm ² (β mode) and 5 C / cm ² or more (γ mode). Then, if the β mode destruction rate is evaluated, it is possible to eliminate the influence of the difference in the growth condition of the silicon single crystal from which the semiconductor silicon wafer has been manufactured, and to evaluate the wafer quality due to the difference in the processing condition. In particular, by judging that the β mode destruction rate is 20% or less as a non-defective product, a sudden change in the processing conditions of the wafer, for example, abnormalities in the wafer quality due to contamination of the cleaning process or polishing process with metal contamination, etc., can be detected with high accuracy. Since it can be grasped, feedback to the wafer processing step is possible.

[0036]

[Embodiment] P-type conductivity, resistivity 10Ωc by CZ method
m, a crystal having a crystal orientation of <100> was pulled up, and a mirror-polished wafer having a diameter of 150 mm was produced by a usual processing method. The polishing conditions were the same, but the effect on the TDDB characteristics was investigated by changing the storage time in pure water after the polishing step.

The MOS capacitor is manufactured according to the manufacturing flow shown in FIG. 4. The phosphorus-doped polysilicon film is supplied with hydrogen gas at the same time as supplying monosilane polysilicon source gas using a reduced pressure vapor phase growth furnace. Deposited by supplying a phosphine (PH ₃ ) gas based on
The thickness of the polysilicon was 200 nm. The patterning of the polysilicon film was performed by wet etching using an etching solution of a mixed acid system (mixed solution of hydrofluoric acid, nitric acid, acetic acid, and water).

The conditions for measuring the TDDB characteristics are as follows: gate oxide film thickness 25 nm, electrode area 4 mm ² , stress current 0.01
A / cm ² , measurement temperature 100 ° C., α mode (5 mC
/ Cm ² ), β mode (5 mC / cm ² or more and 5 C /
cm less than ^2), and γ-mode (5C / cm ² or higher), and the results are shown in Figure 1.

The vertical axis in FIG. 1 is the γ mode destruction rate. The γ mode destruction rate (%) can be expressed by the following equation. Since the same crystal is used, the α mode is constant ( (Approximately 20% here), so that a decrease in the γ mode means an increase in the β mode.

Γ mode destruction rate (%) = 100 (%) − α
Mode destruction rate (%)-β mode destruction rate (%)

FIG. 1 shows that the γ-mode destruction rate decreases as the storage time in pure water increases,
It is estimated that the wafer quality has deteriorated due to the surface roughness of the wafer surface due to the storage in pure water and the adhesion of impurities. Therefore, assuming that the β mode destruction rate is 20% or less as a non-defective product, the storage time in pure water in the wafer manufacturing process here should be controlled to 300 minutes or less at which the γ mode destruction rate is 60% or more. Good things can be judged.

Example 2 160 lots of CZ crystals were pulled up under the same pulling conditions as in Example 1 and processed into mirror-polished wafers. At this time, the polishing conditions for each lot were the same, but the storage time in pure water after the polishing step was not particularly controlled. Then, wafers were extracted one by one from each lot, and the TDDB characteristics were evaluated under the same conditions as in Example 1. The results are shown in FIG. From FIG. 2A, it was found that a lot in which the β mode suddenly showed a large value occurred.

Therefore, the storage time in pure water after the polishing step in wafer processing was controlled within 2 hours, and 98 lots of CZ crystals were further pulled up to prepare additional wafers, and the TDDB characteristics were measured. . The result is shown in FIG.

From the results shown in FIG. 2B, by setting the storage time in pure water after the polishing step to 2 hours or less, all the β modes can be set to a good quality of 20% or less. It can be seen that the improvement has been made.

(Example 3) Diameter 2 manufactured under the same conditions
Two 00 mm silicon epitaxial wafers (epitaxial layer 10 μm) were prepared, one of them was used to fabricate a MOS capacitor under the same conditions as in Example 1, and the other was treated with hydrofluoric nitric acid (hydrofluoric acid, nitric acid, water). Liquid mixture)
After the surface state was deteriorated by etching by about 10 nm, a MOS capacitor was manufactured under the same conditions as in Example 1.

The measurement conditions of the TDDB characteristics are as follows: gate oxide film thickness 25 nm, electrode area 4 mm ² , stress current 0.01 A / cm ² , measurement temperature 25 ° C., α mode (less than 5 mC / cm ² ), β mode (5 mC / cm ² or more and less than 20 C / cm ² ) and γ mode (20 C / cm ² or more) were measured, and the measurement results are shown in FIG. 3. still,
Etched-epi in FIG. 3 indicates an epitaxial wafer that has been subjected to the etching process, and As-epi indicates an epitaxial wafer that has not been subjected to the etching process.

FIG. 3 shows that the effect of deteriorating the surface condition of the wafer surface is not so different between the α mode and the γ mode, and a remarkable difference is seen only in the β mode. That is, it was found that the processing conditions (surface quality) of the wafer can be clearly determined by evaluating the β mode of the TDDB characteristic.

[0048]

According to the present invention, the influence of the difference in the growth conditions of the silicon single crystal from which the semiconductor silicon wafer has been manufactured can be eliminated, and the wafer quality can be evaluated by the difference in the processing conditions. In addition, since the conditions for forming the MOS capacitor and the conditions for measuring the TDDB when forming the MOS capacitor on the semiconductor silicon wafer can be appropriately set, these effects are eliminated as much as possible, and only the quality of the semiconductor silicon wafer is evaluated. Can be. Furthermore, since the evaluation result can be fed back to the processing conditions, the manufacturing process of the silicon wafer can be managed.

[Brief description of the drawings]

FIG. 1 is a graph showing the relationship between the storage time of a wafer in pure water and the γ-mode destruction rate in Example 1.

FIG. 2 is a graph showing a relationship between a storage time of a wafer in pure water and a β mode destruction rate in Example 2,
(A) shows the variation between lots when the storage time is not managed, and (b) shows the variation between lots when the storage time is set to 2 hours or less.

FIG. 3 shows T of an epitaxial wafer in Example 3.
5 is a Weibull plot showing DDB characteristics.

FIG. 4 is a schematic diagram showing an example of a flow of fabricating a MOS capacitor used for TDDB measurement of the present invention.

FIG. 5 is a graph comparing TDDB characteristics of wafers having different manufacturing conditions.

FIG. 6 shows TDD when the thickness of a gate oxide film is changed.
6 is a Weibull plot showing a change in a B characteristic.

FIG. 7 is a graph showing a relationship between a thickness of a polysilicon electrode of a MOS capacitor and a sheet resistance.

FIG. 8 is a Weibull plot showing the stress current dependency of the TDDB characteristic of a MOS capacitor.

FIG. 9 is a graph showing the relationship between the maximum Qbd and the stress current in the TDDB characteristic of a MOS capacitor.

FIG. 10 is a Weibull plot showing the measured temperature dependence of TDDB characteristics for an epitaxial wafer.

[Description of Signs] 1 ... silicon wafer, 2 ... silicon oxide film,
3 ... phosphorus-doped polysilicon film, 4 ... photoresist

Claims (6)

[Claims] A MOS transistor is provided on a surface of a semiconductor silicon wafer.
Forming a capacitor and performing a TDDB measurement on the MOS capacitor to evaluate the quality of the semiconductor silicon wafer based on a random failure (β-mode destruction) rate of a Weibull plot. . 2. The method for evaluating a semiconductor silicon wafer according to claim 1, wherein the semiconductor silicon wafer having the random failure rate of 20% or less is determined as a non-defective product. 3. The method for evaluating a semiconductor silicon wafer according to claim 1, wherein an oxide film thickness when forming the MOS capacitor is 10 to 30 nm. 4. An electrode of the MOS capacitor, wherein an electrode formed by performing wet etching on polysilicon having a thickness of 200 to 400 nm in which a dopant is diffused by a diffusion method without using an ion implantation method is used. The method for evaluating a semiconductor silicon wafer according to any one of claims 1 to 3, wherein: 5. The method for evaluating a semiconductor silicon wafer according to claim 1, wherein the TDDB measurement is performed at a temperature of 25 to 150 ° C. 6. A MOS on a surface of a semiconductor silicon wafer.
Manufacturing a semiconductor silicon wafer by controlling a manufacturing process of the semiconductor silicon wafer based on a random failure (β mode destruction) rate of a Weibull plot obtained by forming a capacitor and performing a TDDB measurement of the MOS capacitor. Process management method.