JPH07321078A - Production of semiconductor wafer - Google Patents
Production of semiconductor waferInfo
- Publication number
- JPH07321078A JPH07321078A JP13647794A JP13647794A JPH07321078A JP H07321078 A JPH07321078 A JP H07321078A JP 13647794 A JP13647794 A JP 13647794A JP 13647794 A JP13647794 A JP 13647794A JP H07321078 A JPH07321078 A JP H07321078A
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- JP
- Japan
- Prior art keywords
- semiconductor wafer
- wafer
- hydrogen atmosphere
- manufacturing
- haze
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＬＳＩ等の作製に用いら
れる半導体ウェーハの製造方法、詳しくは絶縁破壊耐圧
を高めたシリコンウェーハの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor wafer used for manufacturing an LSI or the like, and more particularly to a method for manufacturing a silicon wafer having an increased dielectric breakdown voltage.
【０００２】[0002]
【従来の技術】シリコンウェーハの酸化膜の絶縁破壊特
性を改善する方法としてＨ2アニール技術が注目されて
いる。このＨ2アニール処理を行ったシリコンウェーハ
表面の形状をＡＦＭ（Ａｔｏｍｉｃ Ｆｏｒｃｅ Ｍｉ
ｃｒｏｓｃｏｐｅ：原子間力顕微鏡）により評価した。
このＡＦＭ評価では、ＣＺ（１００）ウェーハおよびＣ
Ｚ（１１１）ウェーハを用いる。詳しくは、これらのシ
リコンウェーハをＨ2雰囲気中で１１００℃×６０分間
アニールした後、大気中でＡＦＭ測定を行った。その結
果、（１００）シリコンウェーハおよび（１１１）シリ
コンウェーハの表面にはともに原子ステップ構造が確認
された。 2. Description of the Related Art The H 2 annealing technique has attracted attention as a method for improving the dielectric breakdown characteristics of an oxide film on a silicon wafer. The shape of the surface of the silicon wafer that has been subjected to this H 2 annealing treatment is determined by AFM (Atomic Force Mi).
croscope: atomic force microscope).
In this AFM evaluation, CZ (100) wafer and C
A Z (111) wafer is used. Specifically, these silicon wafers were annealed in a H 2 atmosphere at 1100 ° C. for 60 minutes, and then AFM measurement was performed in the atmosphere. As a result, atomic step structures were confirmed on the surfaces of the (100) silicon wafer and the (111) silicon wafer.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな処理を施したシリコンウェーハにあっても、発生し
たヘイズを除去するために通常の研磨処理（１μｍ〜２
０μｍの研磨）を行うと、その絶縁破壊耐圧が低くなっ
てしまっていた。これは、Ｈ2アニールの効果はシリコ
ンウェーハの極く浅い表面層のみにしか及ばないからで
あると考えられる。However, even for a silicon wafer that has been subjected to such a treatment, a normal polishing treatment (1 μm to 2 μm) is required to remove the generated haze.
When 0 μm was polished), the dielectric breakdown voltage was low. It is considered that this is because the effect of H 2 annealing extends only to the extremely shallow surface layer of the silicon wafer.
【０００４】そこで、本発明は、絶縁破壊耐圧を高めた
半導体ウェーハの製造方法を提供することを、その目的
としている。Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor wafer having an increased dielectric breakdown voltage.
【０００５】[0005]
【課題を解決するための手段】本発明は、半導体ウェー
ハをＨ2雰囲気中でアニールした後、その半導体ウェー
ハの表面を微少量だけ研磨により除去した半導体ウェー
ハの製造方法である。例えば半導体ウェーハをＨ2雰囲
気中で８００〜１３００℃、好ましくは１１００℃にて
アニールする。なお、このアニール時間は５分間〜２時
間とする。また、上記研磨量は０．０１〜０．６μｍと
する。SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor wafer in which a semiconductor wafer is annealed in an H 2 atmosphere and then the surface of the semiconductor wafer is removed by polishing in a minute amount. For example, a semiconductor wafer is annealed in a H 2 atmosphere at 800 to 1300 ° C., preferably 1100 ° C. The annealing time is 5 minutes to 2 hours. The polishing amount is 0.01 to 0.6 μm.
【０００６】[0006]
【作用】本発明によれば、半導体ウェーハをＨ2（水
素）雰囲気中で熱処理すると、例えばウェーハ表面近傍
の不純物（酸素と関係していると考えられる）は外方に
拡散する等して表面近傍の欠陥の原因となるものはすべ
て取り除かれる。よって、ＯＳＦ、Ｂモード不良欠陥等
のウェーハ表面欠陥を大幅に低減することができる。ま
た、その水素処理後の半導体ウェーハの表面を微少量だ
け研磨により除去する結果、ヘイズ等に起因する耐圧の
低下を抑止することができる。According to the present invention, when a semiconductor wafer is heat-treated in an H 2 (hydrogen) atmosphere, for example, impurities (which are considered to be related to oxygen) near the surface of the wafer are diffused outward, and the surface is All sources of defects in the vicinity are removed. Therefore, wafer surface defects such as OSF and B-mode defect defects can be significantly reduced. Further, as a result of removing the surface of the semiconductor wafer after the hydrogen treatment by a very small amount by polishing, it is possible to suppress a decrease in breakdown voltage due to haze or the like.
【０００７】[0007]
【実施例】本発明の実施例を図面を参照して説明する。
ウェーハ表面をＨ2アニール処理し（１１００℃、６０
分間）、表面基準研磨装置により表面を微少量研磨した
シリコンウェーハについて、絶縁耐圧試験を行った結果
を図１に示す。図中縦軸はＢモード不良率を、横軸は研
磨量を示している。この図に示すように、０．０１〜
０．６μｍの研磨量ではＢモード不良率は良好である。
すなわち、Ｈ2アニールにより絶縁耐圧が向上し、その
効果が発揮されている。そして、この微少量研磨による
シリコンウェーハの表面粗さを図２に示す。Embodiments of the present invention will be described with reference to the drawings.
The wafer surface is annealed with H 2 (1100 ° C., 60
1), the results of a withstand voltage test of a silicon wafer whose surface has been polished in a small amount by a surface reference polishing apparatus are shown in FIG. In the figure, the vertical axis represents the B-mode defect rate, and the horizontal axis represents the polishing amount. As shown in this figure, 0.01-
With a polishing amount of 0.6 μm, the B-mode defect rate is good.
That is, the withstand voltage is improved by H 2 annealing, and the effect is exhibited. And the surface roughness of the silicon wafer by this minute amount polishing is shown in FIG.
【０００８】なお、本絶縁耐圧試験にはＰ型、比抵抗１
０Ω・ｃｍ、（１００）方位のＣＺシリコンウェーハを
使用した。すなわち、このシリコンウェーハの表面に膜
厚２５ｎｍの絶縁膜（熱酸化膜：ＳｉＯ2膜）を形成
し、さらにこの絶縁膜上に面積０．２ｃｍ2のポリシリ
コン電極を被着してＭＯＳ構造とし、この電極とシリコ
ンウェーハとの間に電圧を印加する。この印加電圧を
０．１ＭＶ／ｃｍステップで０．１秒ごとに昇圧してゆ
き、判定電流０．１ｍＡ／ｃｍ2としてその絶縁破壊耐
圧を測定する。In this breakdown voltage test, P type, specific resistance 1
A CZ silicon wafer with 0 Ω · cm and (100) orientation was used. That is, an insulating film (thermal oxide film: SiO 2 film) having a film thickness of 25 nm is formed on the surface of this silicon wafer, and a polysilicon electrode having an area of 0.2 cm 2 is further deposited on this insulating film to form a MOS structure. A voltage is applied between this electrode and the silicon wafer. The applied voltage is stepped up in 0.1 MV / cm steps every 0.1 second, and the breakdown voltage is measured with a judgment current of 0.1 mA / cm 2 .
【０００９】[0009]
【発明の効果】本発明に係る製造方法により製造された
半導体ウェーハは、その耐圧が向上し、その結果として
製造歩留まりが高くなる。The semiconductor wafer manufactured by the manufacturing method according to the present invention has improved withstand voltage, and as a result, the manufacturing yield is increased.
【図１】本発明に係る半導体ウェーハの製造方法の一実
施例を説明するための研磨量とＢモード不良率との関係
を示すグラフである。FIG. 1 is a graph showing a relationship between a polishing amount and a B-mode defect rate for explaining an example of a method for manufacturing a semiconductor wafer according to the present invention.
【図２】本発明の一実施例に係るウェーハ表面の研磨量
と表面粗さとの関係を説明するためのグラフである。FIG. 2 is a graph for explaining a relationship between a polishing amount and a surface roughness of a wafer surface according to an example of the present invention.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 岡田 千鶴子 東京都千代田区岩本町３丁目８番16号 三 菱マテリアルシリコン株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Chizuru Okada 3-8-16 Iwamotocho, Chiyoda-ku, Tokyo Sanryo Material Silicon Co., Ltd.
Claims (3)
ルした後、その半導体ウェーハの表面を微少量だけ研磨
により除去したことを特徴とする半導体ウェーハの製造
方法。1. A method of manufacturing a semiconductor wafer, which comprises annealing a semiconductor wafer in an H 2 atmosphere and then removing the surface of the semiconductor wafer by polishing a minute amount.
〜１３００℃にてアニールする請求項１に記載の半導体
ウェーハの製造方法。2. A semiconductor wafer is heated to 800 in a H 2 atmosphere.
The method for manufacturing a semiconductor wafer according to claim 1, wherein annealing is performed at 1300 ° C.
る請求項１または請求項２に記載の半導体ウェーハの製
造方法。3. The method of manufacturing a semiconductor wafer according to claim 1, wherein the polishing amount is 0.01 to 0.6 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13647794A JP3188810B2 (en) | 1994-05-26 | 1994-05-26 | Silicon wafer manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13647794A JP3188810B2 (en) | 1994-05-26 | 1994-05-26 | Silicon wafer manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07321078A true JPH07321078A (en) | 1995-12-08 |
| JP3188810B2 JP3188810B2 (en) | 2001-07-16 |
Family
ID=15176053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13647794A Expired - Fee Related JP3188810B2 (en) | 1994-05-26 | 1994-05-26 | Silicon wafer manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3188810B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020006308A (en) * | 2000-07-12 | 2002-01-19 | 박종섭 | Planarization method of semiconductor wafer |
| CN112706006A (en) * | 2020-12-31 | 2021-04-27 | 山东大学 | Processing method of ultrathin rare earth oxide laser crystal |
-
1994
- 1994-05-26 JP JP13647794A patent/JP3188810B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020006308A (en) * | 2000-07-12 | 2002-01-19 | 박종섭 | Planarization method of semiconductor wafer |
| CN112706006A (en) * | 2020-12-31 | 2021-04-27 | 山东大学 | Processing method of ultrathin rare earth oxide laser crystal |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3188810B2 (en) | 2001-07-16 |
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