JP2001268066A - Synchronization detector and synchronization detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronization detector that can detect a frame synchronization pattern with high accuracy and reduce the scale of the hardware by relaxing an arithmetic speed being a requirement in complex correlation processing. SOLUTION: Analog/digital converters 107a, 107b apply analog/digital conversion to a signal for a complex base band including frame synchronization data, a correlation filter 121 output a complex correlation between the signal sequence after the conversion and the frame synchronization pattern stored in a storage section 111, over-sampling means 122a, 122b divides the complex correlation, square means 123a, 123b obtain a square of its in-phase component signal sequence and its quadrature component signal sequence, an adder 124 sums the squares, and a generating means 108 decides the signal sequence to be the frame synchronization data when a threshold decision means 125 decides that the complex correlation of the square sum is a specified value or over so as to synchronize reception timing and a reception clock with the received frame synchronization pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile telephone device in a mobile communication system, a mobile station device such as an information terminal device having a mobile phone function and a computer function, or a base station device performing wireless communication with the mobile station device. The present invention relates to a synchronization detection device and a synchronization detection method for detecting a frame synchronization pattern.

[0002]

2. Description of the Related Art In a radio communication, when transmitting a digital signal, a transmission signal is transmitted after being formatted into an information unit called a frame. The receiving side detects the head position of the frame generated on the transmitting side, and decodes the received signal from the head position according to the format.

Here, detecting the head position of a frame is called frame synchronization. The higher the accuracy of frame synchronization on the receiving side, the better the transmission quality. In order to establish frame synchronization, the transmission signal is provided with a section for transmitting known frame synchronization data as a reference signal.

On the receiving side, after the received signal is sampled by the A / D converter, a frame synchronization pattern can be detected by calculating a correlation value between the sampled digital signal and known frame synchronization data. This method is called a correlation method.

[0005] However, such a correlation method cannot achieve frame synchronization accuracy higher than the sampling frequency of the A / D converter on the receiving side, so that sufficient transmission quality cannot be obtained. there were.

[0006] The sampling frequency of the A / D converter includes:
Since there is a certain limit speed, it is not desirable to increase the sampling frequency of the A / D converter to increase the frame synchronization accuracy.

For this reason, the conventional A / D converter has been devised as disclosed in Japanese Patent Application Laid-Open No. 7-58730 in order to realize frame synchronization accuracy with an accuracy higher than the sampling frequency of the A / D converter. . Hereinafter, a conventional example of this publication will be described with reference to FIG.

FIG. 8 is a block diagram showing a configuration of a conventional synchronization detecting device.

The synchronization detecting device shown in FIG.
1, a receiver 802, a local oscillator 803, and a phase shifter 8
04, mixers 805a and 805b, oscillator 806
, A / D converters 807a and 807b, oversampling circuits 808a and 808b, a demodulation unit 809, a complex correlator 810, and a frame synchronization pattern storage unit 811
And a control unit 812.

The operation of such a configuration will be described. The radio signal (RF signal) received by the antenna 801 is converted into an intermediate frequency signal (IF signal) in the receiver 802. The IF signal and the local oscillation signal from local oscillator 803 are mixed in mixer 805a to generate an in-phase component signal (I signal).

The local oscillation signal is phase-shifted by π / 2 in a phase shifter 804 and mixed with an IF signal in a mixer 805b to generate a quadrature component signal (Q signal).

The I signal and the Q signal are supplied to an A / D converter 807
a and 807b sample an analog signal into a digital signal based on the sampling timing of the sampled signal generated from the oscillator 806.

[0013] The sampled I and Q signals are input to oversampling circuits 808a and 808b and further refined by interpolation processing.

In the complex correlator 810, oversampling circuits 808a and 808b
A complex correlation value between the oversampled sequence of I and Q signals from I and the I and Q patterns from the frame synchronization pattern storage unit 811 is calculated.

If the complex correlation value is equal to or larger than a specified value, the received signal sequence based on the I signal and the Q signal is determined to be a frame synchronization pattern, and a synchronization signal is output to the demodulation unit 809.

FIG. 9 is a block diagram showing the configuration of the complex correlator 810. As shown in FIG.
Are a correlation filter 901 and squaring means 902a and 902
b, an adder 903, and a threshold value judging means 904.

In FIG. 9, received baseband analog signals (I signal and Q signal) are converted into A / D converters 807a and 807a.
At 7b, the analog signal is sampled into a digital signal. The sampled I signal and Q signal are input to oversampling circuits 808a and 808b, where they are further refined by interpolation processing and input to complex correlator 810.

The I and Q signal sequences input to complex correlator 810 are subjected to complex correlation with the frame synchronization pattern stored in frame synchronization pattern storage section 811 in correlation filter 901.

The correlation value in-phase component obtained by the correlation filter 901 is input to the squaring means 902a, where the square of the absolute value of the correlation value in-phase component is obtained and output.

The orthogonal component of the correlation value obtained by the correlation filter 901 is input to the squaring means 902b, where the square of the absolute value of the orthogonal component of the correlation value is obtained and output.

The values output from the squaring means 902a and 902b are added in an adder 903, whereby a time series of the square of the absolute value of the complex correlation value is output. The threshold determination unit 904 determines whether the time series of the square of the absolute value of the complex correlation value exceeds the threshold, thereby detecting the position of the frame synchronization pattern. As described above, conventionally, oversampling means 808a,
808b is provided immediately after the A / D converters 807a and 807b, and by calculating the complex correlation value of the oversampled signal, the frame synchronization pattern can be obtained with an accuracy higher than the sampling frequency of the A / D converters 807a and 807b. Has been made possible to detect.

[0022]

However, in the conventional device, each oversampling circuit 808a,
Since 808b is provided immediately after the A / D converters 807a and 807b, the subsequent complex correlator 810, that is, the correlation filter 901 and the squaring means 902 constituting the complex correlator 810 are provided.
a, 902b, adder 903 and threshold value judging means 904
Performs its function on oversampled signals.

Therefore, the oversampling circuit 808
Assuming that a and 808b perform N-fold interpolation, the correlation filter 901, the squaring means 902a and 902b, the adder 903, and the threshold value judging means 904 provide the A / D converter 807
a, an operation speed (operating speed) N times the sampling frequency fs of 807b is required. Similarly, when the transmission speed is increased, the required operation speed (operating speed) is also increased.

Therefore, when the complex correlator 810 is realized by software or hardware, the operation accuracy must be reduced in order to realize the required high operation speed. There is a problem that cannot be detected.

Further, there is a problem that the scale of hardware becomes too large to realize a high operation speed.

The present invention has been made in view of the above points, and by reducing the operation speed required for complex correlation processing, it is possible to detect a frame synchronization pattern with high accuracy and to reduce the hardware scale. An object of the present invention is to provide a synchronization detection device and a synchronization detection method that can reduce the size.

[0027]

According to the present invention, there is provided a synchronization detecting apparatus comprising: A / D conversion means for converting a signal in a complex baseband including frame synchronization data into a digital signal; and storage means for storing a frame synchronization pattern. Correlation filter means for outputting a complex correlation value between the converted signal sequence and the stored frame synchronization pattern, and increasing the number of signals per unit time outputted from the means to increase the correlation filter means. Oversampling means for finely dividing the signal sequence from, the square sum means for calculating the sum of squares of the in-phase component signal sequence and the quadrature component signal sequence output by this means, and the complex correlation value of the sum of squares output by this means A threshold value determining means for determining whether the value is equal to or greater than a prescribed value, and a position of the frame synchronization data of the received signal sequence based on the threshold value determined by the means Detecting employs a configuration that includes a generating means for generating a reception timing and the received clock synchronized thereto, a.

According to this configuration, since the oversampling unit is provided immediately after the correlation filter unit, the speed of the signal input to the correlation filter unit is reduced, and the calculation speed required for the correlation filter unit is reduced. did. That is, since the calculation speed can be reduced to the same speed as the sampling frequency of the A / D conversion means, the frame rate is N times higher than the sampling frequency of the A / D conversion means even at a lower calculation speed than before. A synchronization pattern can be detected. In addition, since the calculation speed can be lower than in the past, the hardware scale can be reduced accordingly.

The synchronization detecting apparatus according to the present invention comprises: A / D conversion means for converting a complex baseband signal including frame synchronization data into a digital signal; storage means for storing a frame synchronization pattern; Correlation filter means for outputting a complex correlation value between a sequence and the stored frame synchronization pattern; square sum means for calculating a sum of squares of the in-phase component signal sequence and the quadrature component signal sequence output by the means; Oversampling means for increasing the number of signals per unit time output by the means to refine the signal sequence from the sum of squares means, and determining whether the complex correlation value of the sum of squares output by the means is greater than or equal to a specified value Means for detecting the position of the frame synchronization data of the received signal sequence from the result of the threshold judgment outputted by the means, A configuration that includes a generating means for generating a grayed and receive clocks, the.

According to this configuration, since the oversampling unit is provided immediately after the square sum unit, the speed of the signal input to the correlation filter unit and the square sum unit is reduced.
The calculation speed required for the correlation filter means and the sum of squares means has been reduced. That is, the operation speed required for the correlation filter means and the sum of squares means can be reduced to the same speed as the sampling frequency of the A / D conversion means. The frame synchronization pattern can be detected with an accuracy of N times the sampling frequency.

The synchronization detecting apparatus according to the present invention comprises an A / D converter for converting a signal in a complex baseband including frame synchronization data into a digital signal, and a signal output per unit time by (N / K) The A /
A first oversampling unit for reducing a signal sequence from the D conversion unit, a storage unit for storing a frame synchronization pattern, and a communication between the signal sequence output from the first oversampling unit and the stored frame synchronization pattern. Correlation filter means for outputting a complex correlation value, second oversampling means for increasing the number of signals per unit time outputted by the means by K times to make the signal sequence from the correlation filter means fine, Sum-of-squares means for calculating the sum of squares of the in-phase component signal sequence and the quadrature component signal sequence to be output; threshold value determining means for determining whether or not the complex correlation value after the square sum is equal to or greater than a specified value; The position of the frame synchronization data of the received signal sequence is detected from the threshold determination result, and the reception timing and reception clock synchronized with this are generated. A configuration that includes a generation unit configured to, a.

According to this configuration, (N / K) times oversampling is performed immediately after the A / D conversion means, and K times oversampling is performed immediately after the correlation filter means. And the speed of the signal input to the correlation filter means is reduced by (1 / K) times to reduce the calculation speed required for the correlation filter means. That is, the frame synchronization pattern can be detected with an accuracy of N times the sampling frequency of the A / D converter even at a calculation speed lower than the conventional one.

The synchronization detecting device of the present invention comprises A / D conversion means for converting a signal in a complex baseband including frame synchronization data into a digital signal, and the number of signals output per unit time by (N / K) The A /
A first oversampling unit for reducing a signal sequence from the D conversion unit, a storage unit for storing a frame synchronization pattern, and a communication between the signal sequence output from the first oversampling unit and the stored frame synchronization pattern. Correlation filter means for outputting a complex correlation value, square sum means for calculating a sum of squares of the in-phase component signal sequence and the quadrature component signal sequence output by the means, and the number of signals output per unit time by K times Second oversampling means for increasing the signal sequence from the sum of squares means;
Threshold determining means for determining whether or not the complex correlation value output by this means is equal to or greater than a prescribed value; and detecting the position of frame synchronization data of the received signal sequence from the threshold determination result output by this means, and synchronizing with this. And a generation unit for generating the reception timing and the reception clock described above.

According to this structure, (N / K) times oversampling is performed immediately after the A / D conversion means, and K times oversampling is performed immediately after the square sum means passed through the correlation filter means. N times oversampling is realized and the speed of the signal input to the correlation filter means is reduced by (1/1 /
K) The calculation speed required for the correlation filter means is eased by making it twice as slow. In other words, A / D even at a lower calculation speed than before
The frame synchronization pattern can be detected with an accuracy of N times the sampling frequency of the conversion means.

[0035] The synchronization detecting apparatus of the present invention employs a configuration in which the first oversampling means has a roll-off filtering function.

According to this configuration, the effect of reducing intersymbol interference, which is a cause of deterioration of transmission quality in mobile communication, can be obtained at the same time.

The mobile station apparatus of the present invention employs a configuration including a synchronization detecting device having the same configuration as any one of the above.

According to this configuration, in the mobile station device,
The same operation and effect as any of the above can be obtained.

The base station apparatus of the present invention employs a configuration including a synchronization detecting device having the same configuration as any of the above.

According to this configuration, in the base station apparatus,
The same operation and effect as any of the above can be obtained.

According to the synchronization detection method of the present invention, a complex baseband signal including frame synchronization data is converted into a digital signal, and a complex correlation value between the converted signal sequence and a previously stored frame synchronization pattern is converted. Is calculated, the oversampling is performed to refine the complex correlation value, the sum of squares of the in-phase component signal sequence and the quadrature component signal sequence obtained by the oversampling is calculated, and the complex correlation value of the sum of squares is equal to or greater than a specified value. If there is, the signal sequence is determined as frame synchronization data, and the reception timing and the reception clock are synchronized with the reception frame synchronization pattern.

According to this method, since the oversampling is performed immediately after the correlation processing, the speed of the signal subjected to the correlation processing is reduced, and the calculation speed required for the correlation processing is reduced. That is, since the operation speed can be reduced to the same speed as the sampling frequency of the A / D conversion process, the frame rate is N times higher than the sampling frequency of the A / D conversion process even at a lower operation speed than before. A synchronization pattern can be detected.

According to the synchronization detecting method of the present invention, a complex baseband signal including frame synchronization data is converted into a digital signal, and a complex correlation value between the converted signal sequence and a previously stored frame synchronization pattern is converted. Is calculated, the sum of squares of the in-phase component signal sequence and the quadrature component signal sequence of the complex correlation value is calculated, and oversampling is performed to make the complex correlation value of the sum of squares fine.The complex correlation value obtained by this oversampling is When the signal sequence is equal to or more than the specified value, the signal sequence is determined to be frame synchronization data, and the reception timing and the reception clock are synchronized with the reception frame synchronization pattern.

According to this method, since the oversampling process is performed after the sum of squares process, the speed of the signal to be subjected to the correlation process and the sum of squares process is reduced, so that the correlation process and the sum of squares process are required. Calculation speed has been reduced. That is,
Since the calculation speed can be reduced to the same speed as the sampling frequency of the A / D conversion process, the frame synchronization pattern can be obtained with N times the accuracy of the sampling frequency of the A / D conversion process even at a lower calculation speed than before. Can be detected.

According to the synchronization detection method of the present invention, a signal in a complex baseband including frame synchronization data is converted into a digital signal, and the number of signals per unit time after the conversion is represented by (N
/ K) to perform a first oversampling to increase the number of times to make the converted signal sequence finer, and obtain a complex correlation value between the first oversampled signal sequence and a previously stored frame synchronization pattern. Performing a second oversampling to increase the number of signals per unit time in the complex correlation value by K times to make the complex correlation value finer, and to obtain an in-phase component signal sequence and a quadrature component signal obtained by the second oversampling. Calculate the sum of squares of the sequence, and when the complex correlation value after the sum of squares is equal to or greater than a specified value, determine the signal sequence as frame synchronization data, and synchronize the reception timing and the reception clock with the reception frame synchronization pattern. I tried to make it.

According to this method, (N / K) times oversampling is performed immediately after the A / D conversion processing, and K times oversampling is performed immediately after the correlation processing. The speed of the signal subjected to the correlation processing is reduced by (1 / K) times, and the calculation speed required for the correlation processing is reduced. That is, even if the calculation speed is lower than
A frame synchronization pattern can be detected with an accuracy of N times the sampling frequency of the / D conversion processing.

According to the synchronization detection method of the present invention, a signal in a complex baseband including frame synchronization data is converted into a digital signal, and the number of signals per unit time after the conversion is represented by (N
/ K) to perform a first oversampling to increase the number of times to make the converted signal sequence finer, and obtain a complex correlation value between the first oversampled signal sequence and a previously stored frame synchronization pattern. , Calculating the sum of squares of the in-phase component signal sequence and the quadrature component signal sequence of the complex correlation value, and increasing the number of signals per unit time in the complex correlation value by K times to make the complex correlation value finer. Sampling is performed, and when the complex correlation value after the second oversampling is equal to or greater than a specified value, the signal sequence is determined to be frame synchronization data, and the reception timing and the reception clock are synchronized with the reception frame synchronization pattern. I made it.

According to this method, (N / K) times oversampling is performed immediately after the A / D conversion processing, and K times oversampling is performed immediately after the sum of squares processing after the correlation processing. A double oversampling is realized, and the speed of the signal subjected to the correlation processing is reduced to (1 / K) times to reduce the operation speed required for the correlation processing. That is, the frame synchronization pattern can be detected with an accuracy of N times the sampling frequency of the A / D conversion process even at a lower calculation speed than the conventional one.

[0049]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a synchronization detecting apparatus according to Embodiment 1 of the present invention.

The synchronization detecting device shown in FIG.
1, a receiver 102, a local oscillator 103, and a phase shifter 1
04, the mixers 105a and 105b, and the oscillator 106
A / D converters 107a and 107b, reception timing / reception clock generation means 108, demodulation section 109,
Complex correlator 110 and frame synchronization pattern storage 11
1 and a control unit 112.

The complex correlator 110 includes a correlation filter 121 and oversampling means 122a and 122b.
, Squaring means 123a, 123b, adder 124,
And a threshold determination unit 125.

The operation of such a configuration will be described. The radio signal (RF signal) received by the antenna 101 is converted into an intermediate frequency signal (IF signal) by the receiver 102. The IF signal and the local oscillation signal from the local oscillator 103 are multiplied in the mixer 105a to generate an in-phase component signal (I signal).

The local oscillation signal is phase-shifted by π / 2 in the phase shifter 104 and multiplied by the IF signal in the mixer 105b to generate a quadrature component signal (Q signal). I
The signals and Q signals are sampled from analog signals into digital signals in A / D converters 107a and 107b based on the sampling timing of the sampled signal generated from oscillator 106.

The sampled I signal and Q signal are supplied to the demodulation unit 1
09 and the complex correlator 110. The input I and Q signal sequences are input to correlation filter 121. Here, a complex correlation value between the frame synchronization pattern, the I signal sequence, and the Q signal sequence stored in the frame synchronization pattern storage unit 111 is calculated according to an instruction from the control unit 112.

The calculated complex correlation value in-phase component is refined by interpolation processing in the oversampling means 122a, and the square value of its absolute value is calculated in the squaring means 123a.

The calculated other orthogonal component of the complex correlation value sequence is further refined by interpolation processing in the oversampling means 122b, and the square value of its absolute value is calculated in the squaring means 123b.

The calculated square value of the absolute value of the in-phase component of the complex correlation value and the square value of the absolute value of the quadrature component of the complex correlation value are added by the adder 124 to obtain the absolute value of the complex correlation value. Is calculated as the squared value of

If the square value of the absolute value of the complex correlation value is equal to or greater than the threshold value, the threshold value judging means 125 determines that the received signal sequence at that time is a frame synchronization pattern, and determines that the timing is the reception timing / reception time. The clock generation means 108 is notified.

Receiving timing / receiving clock generating means 1
In step 08, a reception timing and a reception clock synchronized with the received frame synchronization pattern are generated based on the timing received from the threshold determination unit 125. This makes it possible to synchronize the reception timing / reception clock with the received frame synchronization pattern.

As described above, according to the synchronization detecting apparatus of the first embodiment, after the received signal is A / D converted, oversampling is further performed, and the frame synchronization pattern is determined based on the complex correlation value of the sampling signal. Is detected, the frame synchronization pattern can be detected with higher accuracy than the sampling frequency of the A / D converters 107a and 107b.

The oversampling means 122a,
By moving 122b from immediately after the A / D converters 107a and 107b to immediately after the correlation filter 121, the speed of the signal input to the correlation filter 121 is reduced, and the operation speed required for the correlation filter 121 is reduced. Relaxed.

That is, the operation speed required for the correlation filter 121 can be reduced to the same speed as the sampling frequency of the A / D converters 107a and 107b. Vessels 107a, 107b
, The frame synchronization pattern can be detected with N times the accuracy of the sampling frequency. In addition, since the calculation speed can be lower than in the past, the hardware scale can be reduced accordingly.

(Embodiment 2) FIG. 2 is a block diagram showing a configuration of a synchronization detecting apparatus according to Embodiment 2 of the present invention. However, in the second embodiment shown in FIG. 2, portions corresponding to the respective portions of the first embodiment in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The difference between the synchronization detecting device of the second embodiment shown in FIG. 2 and that of the first embodiment is that the oversampling means 201 is composed of the adder 124 and the threshold value determining means 12.
5 is connected.

In such a configuration, the complex correlator 11
The operation after 0 will be described.

The I signal sequence and the Q signal sequence input to the complex correlator 110 are input to the correlation filter 121, and the frame synchronization pattern storage 1
A complex correlation value with the frame synchronization pattern stored in 11 is calculated.

The complex correlation in-phase component output from the correlation filter 121 is input to the squaring means 123a, and the square value of the absolute value is calculated. Further, the orthogonal component of the complex correlation value output from the correlation filter 121 is
And the square value of the absolute value is calculated.

The square value of the absolute value of the in-phase component of the complex correlation value and the square value of the absolute value of the quadrature component of the complex correlation value are added together in the adder 124 and calculated as the square value of the absolute value of the complex correlation value.

The calculated square value series of the absolute value of the complex correlation value is further refined by the oversampling means 201 and inputted to the threshold value judging means 125.

In the threshold value judging means 125, when the square value of the absolute value of the complex correlation value is equal to or larger than the threshold value,
Assuming that the received signal sequence at that time is a frame synchronization pattern, the timing is notified to the reception timing / reception clock generation means 108.

Reception timing / reception clock generation means 1
At 08, the reception timing and the reception clock are synchronized with the received frame synchronization pattern based on the timing received from the threshold determination unit 125.

That is, the second embodiment is different from the first embodiment shown in FIG.
Is moved from immediately after the correlation filter 121 to immediately after the adder 124, and the number is reduced from two to one.

Therefore, the operation is the same as that of the first embodiment, except that the squaring means 123a and 123b and the adder 124
Is required for the A / D converters 107a, 107
It can be reduced to the same speed as the sampling frequency of b.

As described above, according to the synchronization detecting apparatus of the second embodiment, after the received signal is A / D converted, oversampling is further performed, and the frame synchronization pattern is determined based on the complex correlation value of the sampled signal. Is detected, the frame synchronization pattern can be detected with higher accuracy than the sampling frequency of the A / D converters 107a and 107b.

The oversampling means 201 is set to A
By shifting from immediately after the / D converter to immediately after the squaring means 123a and 123b, the speed of the signal input to the correlation filter 121 and the squaring means 123a and 123b is reduced, and the correlation filter 121 and the squaring means 123a and 123
The calculation speed required for b has been reduced.

That is, the correlation filter 121 and the squaring means 1
The operation speed required for the A / D converters 107a and 107b can be reduced to the same speed as the sampling frequency of the A / D converters 107a and 107b. The frame synchronization pattern can be detected with an accuracy of N times the sampling frequency. In addition, since the calculation speed can be lower than in the past, the hardware scale can be reduced accordingly.

Further, in the second embodiment, the number of oversampling means 201 is one, so that the hardware scale can be reduced as compared with the first embodiment having a configuration using two.

(Embodiment 3) FIG.3 is a block diagram showing a configuration of a synchronization detecting apparatus according to Embodiment 3 of the present invention. However, in the third embodiment shown in FIG. 3, portions corresponding to the respective portions of the first embodiment in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The difference between the synchronization detecting device of the third embodiment shown in FIG. 3 and that of the first embodiment is that the synchronization detecting device is provided between the A / D converters 107a and 107b and the correlation filter 121.
/ K) The double oversampling means 301a and 301b are connected, and the oversampling means 122a and
2b is replaced by K-times oversampling means 302a, 302
b.

In such a configuration, the A / D converter 1
Operations after 07a and 107b will be described.

The I signal and Q signal sampled into digital signals by the A / D converters 107a and 107b are (N / K)
After the number of samples per unit time is refined by (N / K) times in the double oversampling means 301a and 301b, it is input to the correlation filter 121 of the complex correlator 110.

The correlation filter 121 calculates a complex correlation value with the frame synchronization pattern stored in the frame synchronization pattern storage unit 111 according to an instruction from the control unit 112.

The in-phase component of the complex correlation value output from the correlation filter 121 is a K-fold oversampling means 302a
The number of samples per unit time by K
The squared value of the absolute value is calculated by the squaring means 123a.

The orthogonal component of the complex correlation value output from the correlation filter 121
In 02b, the number of samples per unit time is reduced to K times by interpolation processing, and the square value of the absolute value is calculated in the squaring means 123b.

The square value of the absolute value of the in-phase component of the complex correlation value and the square value of the absolute value of the quadrature component of the complex correlation value are added in an adder 124, and are calculated as the square value of the absolute value of the complex correlation value.

If the square value of the absolute value of the complex correlation value is equal to or larger than the threshold value,
Assuming that the received signal sequence at that time is a frame synchronization pattern, the timing is notified to the reception timing / reception clock generation means 108.

Receiving timing / receiving clock generating means 1
At 08, the reception timing and the reception clock are synchronized with the received frame synchronization pattern based on the timing received from the threshold determination unit 125.

However, the (N / K) -times oversampling means 301a and 301b can be operated not only as oversampling means but also as a roll-off filter at the same time.

An example of the configuration of the roll-off filter is shown in FIGS. 4 and 5 and will be described. That is, FIGS. 4 and 5 are block diagrams showing the configuration of the (N / K) -fold oversampling roll-off filter.

First, in FIG. 4, the A / D converter 107
Input signals 400 from a and 107b are 1T delay units (T is one symbol time) 401a and 401 for (N / K).
b, 401c, 401d and multipliers 402a, 402b, 402 using coefficients of roll-off impulse response characteristics as coefficients.
The signal is input to the tapped delay line composed of c and 402d.

The sum of the outputs of the respective delay lines is calculated by a summer 403.
Taken at The output signal 404 of the summer 403 is obtained by adding (N / K) times oversampling processing and roll-off filtering processing to the input signal 400.

The configuration of FIG. 6 is similar to that of FIG.
01A, 401b, 401c, and 401d are 1T
5 shows the configuration of the roll-off filters 501a, 501b, 501c, and 501d in the configuration of FIG.

That is, the roll-off filters 501a to 501a
1d is a filter represented by a tapped delay line in FIG. 6, provided that the multipliers 602a, 602b, 6
02c and 602d are the coefficients of each roll-off filter 50.
The roll-off impulse response characteristic is shifted from 1a to 501d by 1N (N / K).

Each roll-off filter 501a to 501d
Is output by the multiplexing means 502 to (N / K)
A signal 404 output by performing time division multiplexing at intervals of 1T is obtained by adding (N / K) times oversampling processing and roll-off filtering processing.

The required operation speed is shown in FIG.
Is (N / K) times the sampling frequency of the A / D converters 107a and 107b. In contrast, FIG.
Then, each of the roll-off filters 501a to 501d
The sampling rate of the A / D converters 107a and 107b may be the same as that of the A / D converters 107a and 107b.
(a), a speed that is (N / K) times the sampling frequency of 107b is required.

As described above, according to the synchronization detection apparatus of the third embodiment, after the received signal is A / D converted, oversampling is further performed, and the frame synchronization pattern is determined based on the complex correlation value of these sampled signals. , So
The frame synchronization pattern can be detected with higher accuracy than the sampling frequency of the A / D converters 107a and 107b.

Also, instead of oversampling N times immediately after the A / D converters 107a and 107b,
(N / K) times oversampling is performed immediately after the D converters 107a and 107b, and K times oversampling is performed immediately after the correlation filter 121. As a result, oversampling of N times is finally realized, and the speed of the signal input to the correlation filter 121 is reduced to (1 / K) times, thereby alleviating the calculation speed required for the correlation filter 121.

As a result, the operation speed can be lower than in the conventional case, and the hardware scale can be reduced accordingly. In addition, it is possible to simultaneously realize roll-off filter processing for reducing intersymbol interference, which is a cause of deterioration of transmission quality in mobile communication.

(Embodiment 4) FIG. 7 is a block diagram showing a configuration of a synchronization detecting apparatus according to Embodiment 4 of the present invention. However, in the fourth embodiment shown in FIG. 7, portions corresponding to the respective portions of the third embodiment in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

The synchronization detector of the fourth embodiment shown in FIG. 7 is different from that of the third embodiment in that a K-times oversampling unit 701 is connected between the adder 124 and the threshold judging unit 125. I did it.

In such a configuration, the complex correlator 11
The operation after 0 will be described.

The I signal sequence and the Q signal sequence input to the complex correlator 110 are input to the correlation filter 121, and the frame synchronization pattern storage 1
A complex correlation value with the frame synchronization pattern stored in 11 is calculated.

The in-phase component of the complex correlation value output from the correlation filter 121 is input to the squaring means 123a, and the square value of its absolute value is calculated. Further, the orthogonal component of the complex correlation value output from the correlation filter 121 is
And the square value of the absolute value is calculated.

The square value of the absolute value of the in-phase component of the complex correlation value and the square value of the absolute value of the quadrature component of the complex correlation value are added in an adder 124, and are calculated as the square value of the absolute value of the complex correlation value.

The calculated squared value series of the absolute value of the complex correlation value is further reduced by K times the number of samples per unit time in K-times oversampling means 701, and input to threshold value determining means 125.

In the threshold value judging means 125, when the square value of the absolute value of the complex correlation value is not less than the threshold value,
Assuming that the received signal sequence at that time is a frame synchronization pattern, the timing is notified to the reception timing / reception clock generation means 108.

Reception timing / reception clock generation means 1
At 08, the reception timing and the reception clock are synchronized with the received frame synchronization pattern based on the timing received from the threshold determination unit 125.

However, the (N / K) times oversampling means 301a and 301b can be operated not only as oversampling means but also as a roll-off filter at the same time as in the third embodiment.

That is, the second embodiment differs from the first embodiment shown in FIG.
Is moved from immediately after the correlation filter 121 to immediately after the adder 124, and the number is reduced from two to one.

Therefore, the operation is the same as that of the first embodiment, except that the squaring means 123a and 123b and the adder 124
Is required for the A / D converters 107a, 107
It can be reduced to the same speed as the sampling frequency of b.

That is, the fourth embodiment is different from the third embodiment shown in FIG.
01 is moved from immediately after the correlation filter 121 to immediately after the adder 124, and the number is reduced from two to one.

Therefore, the operation is the same as that of the third embodiment except that the squaring means 123a and 123b and the adder 124
Is required for the A / D converters 107a, 107
The speed can be reduced to (N / K) times the sampling frequency of b.

As described above, according to the synchronization detection apparatus of the fourth embodiment, after the received signal is A / D converted, oversampling is further performed, and the frame synchronization pattern is determined based on the complex correlation value of the sampled signal. Is detected, the frame synchronization pattern can be detected with higher accuracy than the sampling frequency of the A / D converters 107a and 107b.

Also, instead of oversampling N times immediately after the A / D converters 107a and 107b,
Immediately after the D converters 107a and 107b, (N / K) times oversampling, the correlation filter 121 and the squaring means 12 are performed.
Immediately after the adder 124 passing through 3a and 123b, K-times oversampling is performed. As a result, N times oversampling is finally realized, and the correlation filter 1
21 and the speed of the signal input to the squaring means 123a and 123b are reduced by (1 / K) times so as to ease the calculation speed required for the correlation filter 121.

As a result, the operation speed can be lower than in the conventional case, and the hardware scale can be reduced accordingly. In addition, it is possible to simultaneously realize roll-off filter processing for reducing intersymbol interference, which is a cause of deterioration of transmission quality in mobile communication.

Further, in the fourth embodiment, since the number of K-times oversampling means 701 is one, the hardware scale can be reduced as compared with the third embodiment having a configuration using two.

[0118]

As described above, according to the present invention,
By alleviating the calculation speed required for the complex correlation processing, it is possible to detect a frame synchronization pattern with high accuracy and to reduce the hardware scale.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a synchronization detection device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a synchronization detection device according to a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a synchronization detection device according to a third embodiment of the present invention.

FIG. 4 shows (N) in the synchronization detection device according to the third embodiment.
/ K) Block diagram showing the configuration of double oversampling means

FIG. 5 is a block diagram showing a configuration of another (N / K) -fold oversampling means in the synchronization detection device according to the third embodiment.

FIG. 6 is a block diagram showing a configuration of a roll-off filter in the (N / K) -times oversampling means shown in FIG. 5;

FIG. 7 is a block diagram showing a configuration of a synchronization detection device according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional synchronization detection device.

FIG. 9 is a block diagram showing a configuration of a complex correlator in a conventional synchronization detection device.

[Explanation of symbols]

107a, 107b A / D converter 108 reception timing / reception clock generation unit 110 complex correlator 111 frame synchronization pattern storage unit 122a, 122b, 201 oversampling unit 123a, 123b square unit 124 adder 125 threshold value judgment unit 301a, 301b ( N / K) times oversampling means 302a, 302b, 701 K times oversampling means

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Mitsuru Uesugi 3-3-1 Tsunashimahigashi, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture F-term within Matsushita Communication Industrial Co., Ltd. 5K004 AA05 AA08 FB01 FH08 JB01 JH05 5K047 AA03 AA04 AA16 BB01 EE02 EE04 GG11 GG16 HH01 HH15 HH43 MM38 MM45 MM62 5K067 AA23 AA42 BB04 DD25 DD30 EE02 EE10 HH22 HH23 KK15

Claims (11)

[Claims] An A / D converter for converting a signal in a complex baseband including frame synchronization data into a digital signal; a storage unit for storing a frame synchronization pattern; a signal sequence after the conversion; Correlation filter means for outputting a complex correlation value between the frame synchronization pattern, and oversampling means for increasing the number of signals per unit time output from the means and reducing the signal sequence from the correlation filter means, Square sum means for calculating the sum of squares of the in-phase component signal sequence and the quadrature component signal sequence output by this means, and threshold value determination for determining whether or not the complex correlation value of the square sum output by this means is equal to or greater than a specified value Means for detecting the position of the frame synchronization data of the received signal sequence from the threshold determination result output from the means, and the reception timing and timing synchronized therewith. And a generation means for generating a reception clock. 2. A / D conversion means for converting a signal in a complex baseband including frame synchronization data into a digital signal, storage means for storing a frame synchronization pattern, the converted signal sequence and the stored Correlation filter means for outputting a complex correlation value between the frame synchronization pattern, square sum means for calculating a sum of squares of an in-phase component signal sequence and a quadrature component signal sequence output by the means, and a unit time output by the means. Oversampling means for increasing the number of signals per unit and finer the signal sequence from the sum of squares means,
A threshold determining unit that determines whether the complex correlation value of the sum of squares output by the unit is equal to or greater than a specified value, and from the threshold determination result output by the unit, detects a position of the frame synchronization data of the received signal sequence, Synchronization detecting apparatus comprising: a generation unit that generates a reception timing and a reception clock synchronized with this. 3. A / D conversion means for converting a signal in a complex baseband including frame synchronization data into a digital signal, and increasing the number of signals per unit time outputted by this means to (N / K) times. A first oversampling means for finely dividing the signal sequence from the A / D conversion means, a storage means for storing a frame synchronization pattern, a signal sequence output from the first oversampling means, and the stored frame synchronization pattern. And a second oversampling means for increasing the number of signals per unit time output by the means by K times to make the signal sequence from the correlation filter means finer. A sum-of-squares means for calculating a sum of squares of the in-phase component signal sequence and the quadrature component signal sequence output by the means; From a threshold determination means for determining whether the value is above, and a threshold determination result output from this means,
Synchronization detection apparatus comprising: a generation unit that detects a position of frame synchronization data of a reception signal sequence and generates reception timing and reception clock synchronized with the position. 4. A / D conversion means for converting a signal in a complex baseband including frame synchronization data into a digital signal, and increasing the number of signals per unit time outputted by the means to (N / K) times. A first oversampling means for finely dividing the signal sequence from the A / D conversion means, a storage means for storing a frame synchronization pattern, a signal sequence output from the first oversampling means, and the stored frame synchronization pattern. Correlation filter means for outputting a complex correlation value between, and a square sum means for calculating a sum of squares of the in-phase component signal sequence and the quadrature component signal sequence output by the means, and a signal per unit time output by the means. A second oversampling means for increasing the number by K times to make the signal sequence from the square sum means fine, and a complex correlation value output by this means being equal to or more than a prescribed value Threshold determining means for determining whether or not, and a generating means for detecting the position of the frame synchronization data of the received signal sequence from the threshold determination result output by the means, and generating a reception timing and a reception clock synchronized with the position. And a synchronization detecting device. 5. The synchronization detecting apparatus according to claim 3, wherein the first oversampling means has a roll-off filtering function. 6. A mobile station device comprising the synchronization detecting device according to claim 1. 7. A base station device comprising the synchronization detecting device according to claim 1. Description: 8. A complex baseband signal including frame synchronization data is converted into a digital signal, and a complex correlation value between the converted signal sequence and a previously stored frame synchronization pattern is calculated. Perform oversampling to make the value finer, calculate the sum of squares of the in-phase component signal sequence and the quadrature component signal sequence obtained by this oversampling, and when the complex correlation value of the sum of squares is equal to or greater than a specified value, A synchronization detection method comprising: determining a signal sequence as frame synchronization data; and synchronizing a reception timing and a reception clock with a reception frame synchronization pattern. 9. A complex baseband signal including frame synchronization data is converted into a digital signal, and a complex correlation value between the converted signal sequence and a previously stored frame synchronization pattern is determined. Calculates the sum of squares of the in-phase component signal sequence and the quadrature component signal sequence of the values, performs oversampling to refine the complex correlation value of the sum of squares, and the complex correlation value obtained by the oversampling is equal to or greater than a specified value. In this case, the signal sequence is determined to be frame synchronization data, and the reception timing and the reception clock are
Synchronization with a received frame synchronization pattern. 10. A signal in a complex baseband including frame synchronization data is converted into a digital signal, the number of signals per unit time after the conversion is increased by (N / K) times, and the converted signal sequence is converted to a digital signal. Is performed, a complex correlation value between the signal sequence after the first oversampling and a frame synchronization pattern stored in advance is obtained, and the number of signals per unit time in the complex correlation value is represented by K. Second to increase the complex correlation value by a factor of two
Oversampling is performed, and the sum of squares of the in-phase component signal sequence and the quadrature component signal sequence obtained by the second oversampling is calculated. If the complex correlation value after the square sum is equal to or greater than a specified value, the signal A synchronization detection method comprising: determining a sequence as frame synchronization data; and synchronizing a reception timing and a reception clock with a reception frame synchronization pattern. 11. A signal in a complex baseband including frame synchronization data is converted into a digital signal, the number of signals per unit time after the conversion is increased by (N / K) times, and the converted signal sequence is converted to a digital signal. Is performed, a complex correlation value between the signal sequence after the first oversampling and a previously stored frame synchronization pattern is obtained, and an in-phase component signal sequence and a quadrature component signal of the complex correlation value are obtained. The sum of squares of the series is calculated, the number of signals per unit time in the complex correlation value is increased by K times, and the second oversampling is performed to make the complex correlation value finer. The complex correlation value after the second oversampling is performed. Is greater than the specified value, the signal sequence is determined to be frame synchronization data, and the reception timing and reception clock are synchronized with the reception frame synchronization pattern. A synchronization detection method.