JP2001267544A - Solid-state image pickup device and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device which can eliminate noise in a picked up image caused by an unwanted incident light and can meet requirements of future miniaturization of pixels. SOLUTION: 1st-3rd embedded metal layers 5, 8 and 11, which surround a light-receiving part 3 on a P-type semiconductor substrate 1 three- dimensionally in a fence shape, are embedded continuously in grooves of 1st-3rd insulating films 4, 7 and 10. The whole outside of the top part of the 3rd embedded metal layer 11 is covered with a light shielding 3rd layer metal 12. The 1st-3rd embedded metal layers 5, 8 and 11 are composed of single layer films of Cu.W.TiW or composite films of Cu.W.TiW and TiN.TiW.Ti. The 3rd layer metal 12 is composed of a single layer film of Al.Al-Si.A1-Cu.Cu.W or a composite film of Al.Al-Si.Al-Cu.Cu.W and W.TiN.TiW.Ti and are formed simultaneously, when wiring metal films of a transistor are formed so as not to be connected electrically to the wiring metal films.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device and a method of manufacturing the same, and more particularly, to a solid-state imaging device capable of suppressing generation of noise due to light incident on a driving circuit and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a solid-state image pickup device, in particular, a light receiving section and a transistor for driving each light receiving section are arranged in an array, and a driving circuit is arranged around a light receiving area.
The light receiving section of a MOS (complementary metal oxide semiconductor) solid-state imaging device has a structure as shown in FIGS. Each of these CMOS solid-state imaging devices has a structure in which each of the light receiving units arranged in an array has a plurality of drive transistors. In this case, a wiring layer connected to the drive transistors and light incident on the transistors are provided. It is necessary to arrange both the light shielding metal film layer and the light shielding metal film layer in the light receiving region. CMOS solid-state imaging devices are:
Generally, it is manufactured by using a multi-layer metal process of two or more layers.
It has a structure as shown in FIG.

The CMOS type solid-state imaging device shown in FIG. 11 is provided on a substrate 21 made of a P-type semiconductor (silicon) for separating a light-receiving portion 23 made of an N-type impurity layer and a transistor for driving from the light-receiving portion 23. Forming a silicon oxide film 22;
A connection hole (not shown) for connecting to a drive transistor or a peripheral circuit is provided in the insulating film 24 formed thereon, and a single- or multi-layer metal layer having a high melting point such as W, TiN, or TiW is provided in the connection hole. After that, the first-layer metal 26 used as a wiring is formed of a single-layer film of Al, Al-Si, Al-Cu or the like, or a multilayer film of these and TiN, Ti, TiW or the like. Further, an insulating film 27 such as a silicon oxide film is formed on the first layer metal 26 and the insulating film 24, and is planarized by CMP (mechanochemical polishing) or the like. In the same manner, a connection hole (not shown) for performing
After embedding a high melting point metal layer such as iN · TiW or the like in a single layer or a multilayer, a second layer metal 29 used for light shielding (for a wiring in a transistor portion) is a single layer such as Al · Al-Si · Al-Cu. A film or a multilayer film of TiN, Ti, and TiW is formed so as to cover the entire surface except for the light receiving section 23.

Then, an insulating film 30 such as a silicon oxide film is formed, flattened by CMP or the like, and Al / Al-S
i. Al-Cu or other single-layer films or TiN, Ti, Ti
Although a third metal layer is formed by a multilayer film with W, in this example, the third metal layer is used only in the driving circuit around the light receiving area and is entirely removed on the light receiving section 23.
It is not shown in FIG. Further, the reason why the second-layer metal 29 is used for shading is that if shading is performed with the third-layer metal, the distance to the microlens 36 formed later becomes short, which is disadvantageous in terms of light collection. This is because light is shielded by a metal at a low position close to 21. Finally, a silicon oxide film or a silicon nitride film is formed as a single layer or a multilayer as the surface protection films 33 and 34 on the insulating film 30, and further, a flattening film 35 and a microlens 36 made of an acrylic material are formed. It is a CMOS solid-state imaging device.

On the other hand, the area of one pixel has been reduced with the recent increase in the definition of the pixel, and the number of wirings for driving the transistor has been reduced to one.
Since only the second-layer metal 26 is insufficient and wiring is becoming difficult, the second-layer metal 29 shown in FIG. 12 is also used for wiring, or the first-layer metal 26 and the second-layer metal 29 shown in FIG. A method of using the third-layer metal 37 for light shielding and light shielding is also adopted.

[0006]

However, FIG.
In the structure in which both the first-layer metal 26 and the second-layer metal 29 are used for wiring as shown in (1), the wiring metal film also serves as the light-shielding metal film. Even if the light is condensed at 36, if there is oblique incident light or irregularly reflected light, the light enters the drive transistor of the light receiving unit 23, and a noise component appears in the captured image. Also, in the structure shown in FIGS. 11 and 13 in which light is completely shielded when viewed from the top, since the interlayer insulating film 27 of 500 to 1000 nm exists between the respective metals 26 and 29, drive of obliquely incident light and irregularly reflected light is performed. Inevitably, the light enters the transistor for use, and as a result, a noise component appears in the captured image.

Accordingly, an object of the present invention is to completely prevent incident light on a transistor portion without increasing the number of steps in a manufacturing process, to eliminate noise in a captured image, and to reduce the size of pixels in the future. An object of the present invention is to provide a solid-state imaging device and a method of manufacturing the same.

[0008]

To achieve the above object, according to the present invention, a pixel cell including a light receiving portion and a plurality of transistors is arranged in a matrix on a semiconductor substrate of one conductivity type. A solid-state imaging device including a driving circuit for driving the plurality of transistors, wherein the solid-state imaging device has a structure in which at least two or more groove-shaped buried metal layers that surround the light-receiving unit in a fence shape are stacked. I do.

In the solid-state imaging device according to the first aspect, at least two or more groove-shaped buried metal layers that surround the light receiving portion in a fence shape are stacked. In other words, unlike the conventional light receiving unit in which the peripheral part except the upper part is simply covered two-dimensionally with the light-shielding metal film, the light receiving part has a part other than the optical path of light that is vertically incident on the light receiving part from the microlens. It is all 3 in the metal film for shading
The light is completely prevented from entering the area other than the light receiving section by the structure covered in a three-dimensional fence shape. More specifically, a buried metal layer such as a refractory metal film layer that has been conventionally used for filling the wiring connection hole is buried in a groove formed in a fence shape with a pattern surrounding the light receiving portion,
After repeating this process vertically and continuously by the number of metal layers, the last metal layer is formed with a pattern that covers all parts other than the light-receiving part, and the light-shielding of the area other than the light-receiving part is completely completed. It was done.

Forming the light-shielding pattern covering all parts other than the light-receiving portion with the last (uppermost) metal layer means that the light-shielding metal film is formed as low as possible in light of the condensing of the microlens. Not against the fact that it is better. This is because, in the case where light is shielded only by the light-shielding film except for the light-receiving portion 23 as in the related art, if the light-shielding film is formed in the upper layer as indicated by 37 in FIG. Although the amount of light that is reflected by the light-shielding film 37 and decreases the amount of incident light on the light receiving unit 23, if formed in the lower layer as shown in FIG. 1B, oblique incident light also reaches the light receiving unit 23 and the amount of incident light increases. In addition, it is necessary to form a light shielding film in a lower layer as close to the substrate 21 as possible. However, in the present invention, as shown in FIG. 1 (A), a fence-shaped metal film layer 19 formed so as to three-dimensionally surround the light receiving unit 3 for light shielding reflects obliquely incident light, and Light-shielding film
Even if the (light shielding metal layer) 12 is formed on the substantially same upper layer as the microlens 16, the amount of incident light does not decrease. Therefore,
The light condensing of the microlens 16 can be designed at a position close to the microlens 16, which has an advantage that it can cope with an increase in the aspect ratio due to future miniaturization of pixels.

In other words, according to the solid-state imaging device of the first aspect, the light incident on the transistor section other than the light receiving section is completely prevented, the generation of noise due to excessive light or oblique incident light is eliminated, and the micro lens is used. The light condensing can be designed at a higher position from the substrate, and can sufficiently cope with an increase in the aspect ratio due to future pixel miniaturization.

A solid-state imaging device according to a second aspect is characterized in that a floating gate is provided below the lowermost groove-shaped buried metal layer.

In the solid-state imaging device according to the second aspect, since the floating gate is provided below the embedded metal layer surrounding the light receiving portion in a fence shape, an embedding groove is formed in addition to the effect of the first aspect. Can be stopped on the floating gate, and the trench formation etching can be easily performed. Since the floating gate can be formed simultaneously with the formation of the gate electrode in the transistor portion, the number of steps in the manufacturing process does not increase.

According to a third aspect of the present invention, in the solid-state imaging device, a light-shielding metal layer surrounding the light receiving portion is provided between the at least two or more groove-shaped buried metal layers.

When at least two groove-shaped buried metal layers surrounding the light receiving portion in a fence shape are superimposed on a semiconductor substrate, it is difficult to align the metal layers because the widths of the metal layers are the same. However, in the solid-state imaging device according to the third aspect, a light-shielding metal layer surrounding the light receiving unit is provided between these metal layers.
By making the width of the light shielding metal layer larger than the width of the metal layer, the upper and lower metal layers can be easily aligned and continuously connected.

A solid-state imaging device according to a fourth aspect is characterized in that the groove-shaped buried metal layer and the light-shielding metal layer according to the third aspect are so large that the area surrounding the light receiving section is higher.

As described in the third aspect, when the upper and lower buried metal layers are overlapped with each other via the light shielding metal layer having a large width, the waveguide effect of the light condensed by the microlens or the like to the light receiving portion is irregularly reflected. In the solid-state imaging device according to claim 4, since the area surrounding the light-receiving portion of the buried metal layer and the light-shielding metal layer increases as the layer becomes higher, the solid-state imaging device according to claim 4 has a fence shape having a waveguide effect. These metal layers spread upward in a tapered shape. Therefore, in addition to the function and effect of the first aspect, the oblique incident light condensed by the microlens is less likely to be hindered or irregularly reflected, and the amount of light incident on the light receiving unit can be further increased.

According to a fifth aspect of the present invention, there is provided a solid-state imaging device according to the third or fourth aspect, wherein the side surface of the light-shielding metal layer has a tapered shape.

In the solid-state imaging device according to the fifth aspect, since the side surface of the light-shielding metal layer between the upper and lower buried metal layers has a tapered shape, in addition to the effect of the first aspect, a fence shape having a waveguide effect is provided. Since there is no projection at right angles on the inner peripheral surface of the metal layer, oblique incident light condensed by the microlens is less likely to be hindered or irregularly reflected, and the amount of light incident on the light receiving portion can be further increased.

According to a sixth aspect of the present invention, in the solid-state imaging device, the light-shielding metal layer is formed simultaneously with the wiring metal film of the transistor and a driving circuit for driving the transistor. It is not electrically connected to the film.

In the solid-state imaging device according to the present invention, the light shielding metal layer connecting the upper and lower embedded metal layers is formed simultaneously with the wiring metal film of the transistor and its driving circuit, that is, in the same step as the formation of the wiring metal film. Therefore, the number of steps in the manufacturing process does not increase by forming the metal layer for light shielding,
The functions and effects of claims 3 to 5 can be achieved without increasing the number of manufacturing steps.

According to a seventh aspect of the present invention, in the solid-state imaging device, a single layer film of Cu.W.TiW or a composite film of Cu.W.TiW and TiN.TiW.Ti is used as the groove-shaped buried metal layer. It is characterized by.

In the solid-state imaging device according to the seventh aspect, a general high melting point metal which is embedded in a connection hole for connecting a light receiving portion to a drive transistor or a peripheral circuit as a fence-like embedded metal layer having a waveguide effect. Cu ・ W ・ Ti
W single-layer film, or CuWTiW and TiNTiWTT
Since a composite film with i is used, a fence-shaped buried metal layer having a waveguide effect can be formed in the same step as the step of burying the high melting point metal in the connection hole, and the above-described operation can be performed without increasing the number of manufacturing steps. The effect can be achieved.

In the solid-state imaging device according to the present invention, the metal layer for light shielding may be a single-layer film of Al, Al-Si, Al-Cu, Cu, W, or Al, Al-Si, Al-Cu, Cu.・ W and W ・ Ti
It is characterized in that a composite film with N.TiW.Ti is used.

In the solid-state imaging device according to the present invention, Al.Al-Si.multidot., Which is generally used for wiring of a drive transistor or a transistor of a peripheral circuit portion, as a light shielding metal layer connecting the upper and lower embedded metal layers. Al-Cu-Cu-W single-layer film, or Al-Al-Si-Al-Cu-Cu-W and W-Ti
Since the composite film of N.TiW.Ti is used, the light-shielding metal layer can be formed in the same step as the wiring step of the transistor, and the above effects can be obtained without increasing the number of manufacturing steps.

According to a ninth aspect of the present invention, there is provided a driving circuit for driving a plurality of transistors, wherein pixel cells each including a light receiving portion and a plurality of transistors are arranged in a matrix on a semiconductor substrate of one conductivity type. The method for manufacturing a solid-state imaging device provided includes a step of removing the insulating film on the light receiving portion in a groove shape at least twice so as to surround the light receiving portion and embedding a metal layer in the groove. .

According to a ninth aspect of the present invention, there is provided a method for manufacturing a solid-state imaging device, comprising:
Since the insulating film on the light receiving portion is removed at least twice in a groove shape so as to surround the light receiving portion and the metal layer is buried in the groove,
The light-receiving part of the manufactured solid-state imaging device has a structure in which all parts other than the optical path of light that is perpendicularly incident on the light-receiving part from the microlens are three-dimensionally covered in a fence shape by a light-shielding metal film. Light is completely prevented from entering the area other than the light receiving section. Therefore, as described in claim 1, the generation of noise due to excessive light or oblique incident light can be eliminated, and the light condensing by the microlens can be designed at a higher position from the substrate, and future pixel miniaturization can be achieved. Can sufficiently cope with an increase in the aspect ratio.

According to a tenth aspect of the present invention, there is provided a method for manufacturing a solid-state imaging device, comprising:
The metal layer buried in the trench is formed simultaneously with the metal layer for a wiring connection hole of the transistor and a driving circuit for driving the transistor.

In the method of manufacturing a solid-state imaging device according to the tenth aspect, the metal layer buried in the groove is formed simultaneously with the metal layer for the transistor and the wiring connection hole of the drive circuit for driving the transistor. Since the metal layer having a waveguide effect can be formed at the same time as the metal layer for the wiring connection hole of the transistor and its driving circuit, that is, in the same process, the fence-shaped metal layer having the waveguide effect can be formed. By the formation of the above, the number of steps of the manufacturing process does not increase, and the operation and effect of claim 9 can be obtained without increasing the number of manufacturing steps.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. In the solid-state imaging device of the present invention, a pixel cell including a light receiving portion and a plurality of transistors is arranged in a matrix on a semiconductor substrate of one conductivity type, and a driving circuit for driving the transistor is arranged around the pixel cells. FIG. 2 is a cross-sectional view of a solid-state imaging device (image cell) which is an embodiment of the solid-state imaging device according to claims 1, 6 to 8. The solid-state imaging device includes a light receiving section 3 provided on a surface of a P-type semiconductor substrate 1 by doping an N-type impurity such as phosphorus or arsenic, and an element isolation insulator for separating both sides of the light receiving section 3 from a drive transistor. A first insulating film 4 covering the surface of the film 2, the light receiving unit 3 and the element isolation insulating film 2, and a groove provided in the first insulating film 4 so as to surround the light receiving unit 3 in a fence shape for shielding light. The semiconductor device includes a buried first buried metal layer 5 and a first-layer metal 6 provided on the first insulating film 4 except for a portion above the light receiving portion for wiring to a drive or a transistor of a peripheral circuit.

Next, the solid-state image pickup device is provided with a second insulating film 7 covering the first insulating film 4 and the first-layer metal 6, and a light-receiving section 3 is surrounded by the second insulating film 7 in a fence shape. A second buried metal layer 8 buried so as to be continuous above the first buried metal layer 5 in the groove and a second insulating film 7 except for a portion above the light receiving portion for wiring to a transistor. A third insulating film 10 covering the second insulating film 7 and the second metal 9;
Similarly, a third buried metal layer 11 buried in a fence-shaped groove in the insulating film 10 and a light-shielding layer covering the outside of the fence-shaped buried metal layers 5, 7, 10 on the third insulating film 10 A third metal 12 as a film and a third insulating film 10
And two-layer surface protection films 13 and 14 covering the third metal layer
And a flattening film 15 on the surface protective film 14 and a microlens 16 provided on the uppermost portion for condensing light.

The first, second, and third insulating films 4, 7, and 10 are
The first, second, and third metal layers 6, 9, and 12 are formed of silicon oxide (BPSG) films containing phosphorus and boron having flatness for promoting fineness of the metal. First, second,
The third buried metal layers 5, 7, and 10 are made of a single-layer film of Cu.W.TiW, which is a common high melting point metal for connection and wiring and can be used for light shielding, or Cu.W.TiW. And Ti
Using a composite film with N.TiW.Ti, each insulating film 4,7,10
Are formed in the same step as the formation of the connection holes for the drive transistor and the peripheral circuit. The first, second, and third metal layers 6, 9, and 12 include:
Al ・ Al with general light shielding properties for transistor wiring
-Si-Al-Cu-Cu-W single-layer film or Al-Al-Si
Use a composite film of Al-Cu-Cu-W and W-TiN-TiW-Ti. The surface protection films 13 and 14 include a silicon nitride film, a silicon oxide film, and a silicon oxide film containing phosphorus.
(PSG film) A single-layer film or a multilayer film such as a SiON film can be used. In the present embodiment, a multilayer film of a PSG film and a silicon nitride film having excellent surface stability is used. Further, the microlenses 16 and the underlying planarizing film 15 are made of an acrylic material.

The method of manufacturing the solid-state image pickup device shown in FIG. 2 will be described with reference to FIGS. First, as shown in FIG. 3A, an insulating film 2 for separating a light receiving portion 3 from a drive transistor and a peripheral circuit transistor is formed on a P-type silicon semiconductor substrate 1 by thermal oxidation of silicon. As oxidation conditions, hydrogen and oxygen gas are introduced into a furnace at 950 to 1100 ° C. to form a 200 to 600 nm silicon oxide film on the surface of the semiconductor substrate 1 in the furnace. Note that transistors and the like around the light receiving unit 3 are not shown. Next, an N-type impurity such as phosphorus or arsenic is ion-implanted into a portion serving as a light receiving portion to form a light receiving portion 3.
To form Next, as shown in FIG. 3B, a first insulating film 4 serving as a base of the first-layer metal 6 (see FIG. 3C) is formed of a silicon oxide film. In order to make the first metal layer 6 for wiring finer, it is desirable to use a silicon oxide film (BPSG film) containing phosphorus and boron because it is desirable to have flatness. The atmospheric pressure CVD apparatus containing a semiconductor substrate 1, SiH ₄ gas 70~100cc / min., PH ₃ gas 150~250cc / min., A B ₂ H ₆ gas 150~250cc / mi
n. and O ₂ gas are introduced at ₂ to 31 / min.
The film was formed at a temperature of ° C, and the concentration of phosphorus contained in the film was adjusted to 3.
Assuming 0-3.5mol% and boron concentration 3.0-3.5wt%, 900 ~
Heat treatment was performed at a temperature of 1000 ° C. to obtain a planarized first insulating film 4.

Thereafter, as shown in the plan view on the right side of FIG. 3B, a groove for the buried metal layer 5 serving as a fence-shaped light-shielding film is formed in a pattern surrounding the light receiving section 3. Due to the necessity of providing a reset transistor adjacent to discharge unnecessary charges, the groove has a partially cut pattern as shown by 5a in a plan view. The part of the groove is cut off because the groove is formed by dry etching, so that the etching can be stopped at the part where the thick first insulating film 4 is formed, but the drawing without the first insulating film 4 If a groove is made in part 5a, etching cannot be stopped,
This is because the semiconductor substrate 1 is damaged. The formation of the groove and the subsequent filling of the buried metal layer 5 can be performed in the same process as the formation of the connection hole for the drive transistor and the peripheral circuit transistor of the light receiving section 3 and the burying of the contact for reducing the contact resistance. Therefore, the number of steps in the manufacturing process does not increase.

Since the burying metal layer 5 is buried in the fence-shaped groove around the light receiving portion in the same step as the CVD growth and etch-back of the contact refractory metal film in the transistor portion, Must be smaller than the contact diameter. Therefore, the etching of the contact in the trench and the transistor portion uses RIE (reactive ion etching), and the pressure of the processing chamber is set to 100 to 300 Pa,
CHF ₃ gas flow rate is 20-100 sccm, CF ₄ gas flow rate is 5
~ 50sccm, Ar gas flow rate 500 ~ 1000sccm, electrode RF
The power is set to 500 to 1000 W, and the processing is performed for an etching time such that the etching stops in the middle of the thick insulating film 4 around the light receiving portion. The high melting point metal film 5 is buried in the trench and the contact after a material such as TiN is formed by sputtering or the like, and then tungsten hexafluoride (WF ₆ ), argon / hydrogen (H ₂ ) / nitrogen (N ₂ ) is used as a source gas by a reduced pressure CVD method or the like.
A tungsten film is formed at a growth temperature of ° C.

Next, the wafer is transferred to another RIE chamber, the processing chamber pressure is set to 15 to 50 Pa, and the SF ₆ gas flow rate is set to 5
After etching the refractory metal film until the TiN film under tungsten is exposed by setting the Ar gas flow rate to 0 to 200 sccm, the Ar gas flow rate to 50 to 150 sccm, the He gas flow rate to 2 to 20 sccm, and the electrode RF power to 300 to 700 W, for example, Using an ECR (Electron Cyclotron Resonance) type plasma etching apparatus, etc., the pressure of the processing chamber is 0.1 to ₃ Pa, and the flow rate of BCl ₃ gas is 20 to 100 scc.
m, SF6 gas flow rate 10 ~ 50sccm, microwave power 200 ~ 500W, bias RF power 20 ~ 100W
The etching of TiN is performed until the insulating film 4 is exposed. In this way, as shown in FIG. 3B, a buried metal layer 5 as a fence-shaped light shielding film is formed. Subsequently, the first-layer metal 6 used as a wiring in the transistor for driving the light receiving unit 3 and the transistor for the peripheral circuit unit is changed to Al, Al-Si,
Al ・ Cu ・ Cu ・ W single layer film or Al ・ Al-Si ・ Al ・
After forming a composite film of Cu, Cu, W and W, TiN, TiW, Ti by a method such as sputtering, the wiring 6 is formed by photo-dry etching. Dry etching conditions are, for example, using an ECR type plasma etching apparatus, the pressure of the processing chamber is 0.1 to ₃ Pa, the flow rate of BCl ₃ gas is 20 to 100 sccm, the flow rate of Cl ₂ gas is 20 to 100 sccm, and the microwave power is 200 to 500 W. , The bias RF power is 2
0 to 100W. Note that in this embodiment mode, FIG.
As shown in the figure, the first metal layer above the light receiving section 3 is entirely removed. Note that the wiring 6 is omitted in the plan view on the right side of FIG.

Thereafter, a silicon oxide film as a second insulating film 7 serving as a base of the second-layer metal 9 (see FIG.
After the film is formed by VD or the like, it is planarized by CMP (mechanochemical polishing) or the like, and the second-layer fence-shaped buried metal layer 8 and the metal in the transistor portion are overlapped on the buried metal layer 5 surrounding the light receiving portion. A connection hole for interlayer connection is formed in the same manner as the formation of the buried metal layer 5 and the first-layer connection hole, thereby obtaining a fence-shaped buried metal layer 8 as shown in FIG. Can be Since the second buried metal layer 8 has no problem of wiring to the reset transistor drawn out from the light receiving section 3, FIG.
As shown in the plan view of FIG. 3, the pattern is continuous over the entire circumference without the cut portion 5a as shown in FIG.

Further, by repeating the same processing as described above, as shown in FIG.
A layer metal 9 (used for wiring in the transistor portion, not shown in the plan view on the right side) is formed, and as shown in FIG.
A third insulating film 10 and a connection hole (not shown) are formed on the surface thereof, a third buried metal layer 11 is formed in a groove provided in a fence shape in the third insulating film 10, and a contact metal is formed in the connection hole. (Not shown) are embedded. Next, the third insulating film 1
As shown in FIG. 4 (G), a third metal layer 12 as a light-shielding film (shown in the plan view on the right side) is formed so as to cover the outside of the embedded metal layer 11 on ) Is formed. This makes it possible to completely prevent light from entering other portions than the light receiving section 3. The third-layer metal 12 is used not only for light shielding but also for wiring in a peripheral circuit portion (not shown) outside the light receiving region where the light receiving portions 3 are arranged in an array.

Thereafter, as shown in FIG. 5H, the surface protection films 13 and 14 and the lens are covered with a silicon nitride film and a silicon oxide film containing phosphorus so as to cover the third insulating film 10 and the third metal layer 12. A planarization film 15 made of an acrylic material as a base is sequentially formed, and finally, as shown in FIG. 5I, a microlens 16 is formed of an acrylic material to complete a solid-state imaging device.

The solid-state imaging device having the above configuration operates as follows. The light receiving section 3 of the solid-state imaging device has a planar metal film 29, 3 except for the area directly above the light receiving section 23 described in FIGS. 1B and 1C.
1A, the portion other than the optical path of the light vertically incident on the light receiving portion 3 from the microlens 16 is embedded in the buried metal layer 19 and the light shielding portion 3 as shown in FIG. It has a three-dimensionally fenced structure with the layer metal 12 and completely shields the area other than the light receiving section 3 from light. In addition, the buried metal layer 19 has a waveguide effect of reflecting light incident through the microlens 16 and guiding the light to the light receiving section 3 as shown by an arrow in FIG. Therefore, since obliquely incident light and irregularly reflected light do not enter the drive transistors and the like other than the light receiving unit 3, noise appearing in a captured image due to such light can be eliminated. Further, even if the light shielding metal 12 is provided in the third layer away from the semiconductor substrate 1, the amount of light incident on the light receiving unit 3 does not decrease, so that light can be collected at a position close to the microlens 16. It is possible to cope with an increase in the aspect ratio due to pixel miniaturization.

FIG. 6 is a sectional view of a solid-state imaging device as one embodiment of the solid-state imaging device according to the second and third aspects.
This solid-state imaging device is the same as the solid-state imaging device of FIG.
When the groove for the first buried metal layer 5 described in (B) is formed in the first insulating film 4 by etching, if the element isolation insulating film 2 around the light receiving section 3 is thin, the etching is performed. The point that it is difficult to stop in the middle, and FIG. 3 (D);
(F) is an improvement on the point that it is difficult to position the upper and lower buried metal layers 5, 8;
In the solid-state imaging device, a floating gate 17 is provided below the first buried metal layer 5, and the first and second buried metal layers 5, 8 and the second and third buried metal layers 8, 11 are provided.
Only the point that a first-layer metal 6 and a second-layer metal 9 are provided as light-shielding metal layers surrounding the light-receiving unit 3 is different from the solid-state imaging device of FIG. 2. The same numbers are assigned and the description is omitted.

The floating gate 17 is a floating gate electrode of a transistor for controlling the on / off of a current signal output from the light receiving section 3 or amplifying the current signal, and the first buried metal via an upper insulating film. It is continuous with the layer 5 and has a wider width than the groove of the first buried metal layer 5, and is formed in the same step as the formation of the gate electrode of the transistor. The first-layer metal 6 and the second-layer metal 9 as the light-shielding metal layers are specifically formed of a floating-interconnect metal film, and are respectively continuous with the second buried metal layer 8 and the third buried metal layer. Tier 1
It has a width wider than one groove, and is formed so as not to be electrically connected to the wiring metal 6 or 9 of the transistor outside in the same layer in the same step.

FIGS. 7A to 7D, 8E to 8G, and 9H.
6 to (J) sequentially show the manufacturing process of the solid-state imaging device in FIG. 6. In this manufacturing process, the floating gate 17 is provided in FIG. 7 (B), and FIG. 7 (D) and FIG. Only the point that the first and second metal layers 6 and 9 for light shielding are provided in FIGS.
Therefore, the description of the same process is omitted.
When a groove for the first buried metal layer 5 surrounding the light receiving portion 3 in FIG. 7C in a fence shape is formed in the first insulating film 4 by etching, element isolation is performed in a step shown in FIG. Insulating film 2
The floating gate 17 is formed thereon. Therefore, even when the element isolation insulating film 2 around the light receiving section 3 is thin,
The etching of the groove can be reliably stopped on the floating gate 17, and the semiconductor substrate 1 is not damaged by excessive etching. Since the floating gate 17 is formed simultaneously with the formation of the gate electrode in the transistor portion, the number of steps in the manufacturing process does not increase.

In the case where the second buried metal layer 8 of FIG. 8E is aligned with the lower first buried metal layer 5 and is superimposed, the first buried metal layer 5 is placed on the first buried metal layer 5 as shown in FIG. Since the light-shielding wide first-layer metal 6 is formed in the step, the second buried metal layer 8 and the first buried metal layer 8 can be formed even if the positioning accuracy of the burying groove provided in the second insulating film 7 is somewhat poor. 5 can be continuously connected via the first metal layer 6, and the upper and lower embedded metal layers 8, 5 can be easily aligned. Further, the second buried metal layer 11 shown in FIG.
In the superposition with the buried metal layer 8 as well, the alignment can be similarly facilitated by the second-layer metal 9 for light shielding. The first and second metal layers 6 and 9 for shading are used.
Is formed at the same time as the formation of the wiring metal film in the transistor portion, so that the number of steps in the manufacturing process does not increase.

FIG. 10 is a sectional view of a solid-state imaging device as one embodiment of the solid-state imaging device according to the fourth and fifth aspects. This solid-state imaging device is different from the solid-state imaging device shown in FIG. 6 in that the first and second wide metal layers 6, 5 for shielding light are interposed between the embedded metal layers 5, 8, 11 surrounding the light receiving section 3 in a fence shape as shown in the figure. 9
Since the right-angled corners protrude from the inner peripheral surface, the light condensed by the microlens 16 is reflected by the inner peripheral surface as shown in FIG. However, there is a problem that the amount of received light is reduced due to irregular reflection at the right-angled corners. The solid-state imaging device includes grooves (fences) having respective buried metal layers 5, 8,
6 except that the area surrounding the light receiving section 3 of the first and second metal layers 6 and 9 for light shielding is larger in the upper layer, except that the side surfaces of the first and second metal layers 6 and 9 are tapered. Since the configuration is the same as that of the solid-state imaging device described above, the same components are denoted by the same reference numerals and description thereof is omitted. The distance between the first, second, and third buried metal layers 5, 8, and 11 increases by about twice the layer width in this order toward the upper layer, and the first and second metal layers 6, 8, 11
Reference numeral 9 denotes an isosceles trapezoidal cross section having a width of about twice as large as the above-mentioned layer width. These form a continuous light guide surface that extends upward in a tapered shape.

The equilateral trapezoidal cross sections of the first and second metal layers 6 and 9 are as follows.
It can be formed by increasing the generation of a sidewall protective film (reaction product) during the etching of these metals.
Using an ECR type plasma etching apparatus or the like, the pressure in the processing chamber is 1 to 5 Pa, the flow rate of BCl ₃ gas is 50 to 150 sccm,
Cl ₂ gas flow rate 10 ~ 50sccm, microwave power
This can be realized by setting the power of the bias RF to 300 to 500 W and the bias RF power to 5 to 50 W. In this manner, the first to third buried metal layers 5, 8, 11 and the first and second metal layers 6, 9 form a waveguide surface that expands in a tapered shape upward. The obliquely incident light reaches the light receiving section 3 without being obstructed or irregularly reflected, the amount of received light can be further increased, and the quality of a captured image can be further improved.

[0047]

As is apparent from the above description, claim 1
Since the light receiving portion of the solid-state imaging device on the semiconductor substrate is surrounded by at least two layers of groove-shaped buried metal layers in a fence shape, the light path other than the optical path of light that is perpendicularly incident on the light receiving portion from the microlens is By covering the entire area with a light-shielding metal film, it is possible to completely prevent light that enters the transistor section etc. other than the light receiving section, and to eliminate the occurrence of noise due to excessive light or oblique incident light. In addition to improving the image quality, the fence-shaped buried metal layer has a waveguide effect that reflects incident light and guides it to the light receiving part, so that light can be collected at a position close to the microlens and future pixel miniaturization Can increase the aspect ratio.

In the solid-state imaging device according to the second aspect, since the floating gate is provided below the embedded metal layer surrounding the light receiving portion in a fence shape, in addition to the effect of the first aspect, a trench for embedding is formed. Etching can be stopped on the floating gate, and groove formation etching can be facilitated without increasing the number of steps in the manufacturing process.

In the solid-state imaging device according to the third aspect, a light-shielding metal layer surrounding the light receiving portion is provided between at least two or more groove-shaped buried metal layers surrounding the light receiving portion in a fence shape. In addition to the function and effect of item 1, by making the width of the light-shielding metal layer larger than the width of the metal layer, the upper and lower metal layers can be easily aligned and continuously connected.

In the solid-state imaging device according to the fourth aspect, since the area surrounding the light receiving portion of the buried metal layer and the light shielding metal layer becomes larger as the upper layer becomes higher, the fence-shaped metal layer having a waveguide effect is formed. Since the obliquely incident light condensed by the microlens reaches the light receiving portion without being obstructed or irregularly reflected, the amount of received light can be further increased, and the image quality of the captured image can be improved. It can be further improved.

In the solid-state imaging device according to the fifth aspect, since the side surface of the light-shielding metal layer between the upper and lower buried metal layers has a tapered shape, it is perpendicular to the inner peripheral surface of the fence-shaped metal layer having a waveguide effect. Since there is no protrusion, the oblique incident light condensed by the microlens reaches the light receiving section without being hindered or irregularly reflected, and as a result, the amount of received light can be further increased, and the image quality of the captured image can be further improved. it can.

In the solid-state imaging device according to the sixth aspect, the metal layer for shielding connecting the upper and lower buried metal layers is formed in the same step as the formation of the wiring metal film of the transistor and its driving circuit, so that the number of manufacturing steps is increased. The above-mentioned effects can be obtained without the above.

In the solid-state imaging device according to a seventh aspect of the present invention, the groove-shaped buried metal layer is a single-layer film of Cu.W.TiW, which is a refractory metal generally used for burying connection holes, or Cu.W.・ Since a composite film of TiW and TiN / TiW / Ti is used, a fence-shaped buried metal layer having a waveguide effect can be formed in the same step as the step of burying the high melting point metal in the connection hole. The above-described effects can be obtained without increasing the number.

In the solid-state imaging device according to the present invention, as the metal layer for light shielding, a single-layer film of Al, Al-Si, Al-Cu, Cu, or W, which is generally used for a transistor wiring, is used.
l ・ Al-Si ・ Al-Cu ・ Cu ・ W and W ・ TiN ・ TiW ・ T
Since the composite film with i is used, the light-shielding metal layer can be formed in the same step as the wiring step of the transistor, and the above operation and effect can be obtained without increasing the number of manufacturing steps.

According to a ninth aspect of the present invention, in the method of manufacturing a solid-state imaging device, at least two insulating films on the light receiving portion are provided so as to surround the light receiving portion.
Since the process includes removing the metal layer in the groove more than once and embedding the metal layer in this groove, the light-receiving metal film is covered by covering all the parts other than the optical path of the light that is perpendicularly incident from the microlens to the light-receiving part with the metal film for light shielding. By completely preventing light incident on the transistor section other than the section, noise caused by excessive light or oblique incident light can be eliminated, and the image quality of the captured image can be improved.
Since the fence-shaped buried metal layer has a waveguide effect of reflecting incident light and guiding it to the light receiving part, light can be condensed at a position close to the microlens, and the aspect ratio will increase with future pixel miniaturization. Can also respond.

According to a tenth aspect of the present invention, there is provided a
Since the metal layer embedded in the groove is formed simultaneously with the metal layer for the transistor and the wiring connection hole of the driving circuit for driving the transistor, the light receiving portion is surrounded in a fence shape, and the metal layer having a waveguide effect is formed. Since it can be formed in the same process as the formation of the wiring connection hole of the transistor and its driving circuit,
The above effects can be obtained without increasing the number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a comparison between converging trajectories of the present invention and a conventional solid-state imaging device.

FIG. 2 is a cross-sectional view illustrating a main part of one embodiment of the solid-state imaging device according to the present invention.

FIG. 3 is a cross-sectional view of a principal part showing a manufacturing process of the solid-state imaging device in FIG. 2;

4 is a fragmentary cross-sectional view showing a manufacturing step of the solid-state imaging device in FIG. 2;

5 is a fragmentary cross-sectional view showing a manufacturing step of the solid-state imaging device in FIG. 2;

FIG. 6 is a cross-sectional view illustrating a main part of another embodiment of the solid-state imaging device of the present invention.

7 is a fragmentary cross-sectional view showing a manufacturing step of the solid-state imaging device of FIG. 6;

8 is a fragmentary cross-sectional view showing a manufacturing step of the solid-state imaging device in FIG. 6;

9 is a fragmentary cross-sectional view showing a manufacturing step of the solid-state imaging device of FIG. 6;

FIG. 10 is a sectional view showing a main part of another embodiment of the solid-state imaging device of the present invention.

FIG. 11 is a cross-sectional view of a main part showing an example of a conventional solid-state imaging device.

FIG. 12 is a cross-sectional view of main parts showing another example of a conventional solid-state imaging device.

FIG. 13 is a cross-sectional view of a main part showing another example of a conventional solid-state imaging device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation insulating film 3 light receiving section 4 first insulating film 5 first buried metal layer 6 first layer metal 7 second insulating film 8 second buried metal layer 9 second layer metal 10 third insulating film 11th 3 buried metal layer 12 3rd metal 13 and 14 surface protection film 15 planarization film 16 micro lens 17 floating gate 19 fence-shaped metal film layer

Claims (10)

[Claims] 1. A solid-state imaging device in which pixel cells each including a light receiving portion and a plurality of transistors are arranged in a matrix on a semiconductor substrate of one conductivity type, and provided with a driving circuit for driving the plurality of transistors. 3. The solid-state imaging device according to claim 1, wherein the solid-state imaging device has a structure in which at least two or more groove-shaped buried metal layers surrounding the light receiving unit in a fence shape are stacked. 2. The solid-state imaging device according to claim 1, wherein a floating gate is provided below the lowermost groove-shaped buried metal layer. 3. The solid-state imaging device according to claim 1, wherein a light-shielding metal layer surrounding the light-receiving portion is provided between the at least two or more groove-shaped buried metal layers. Solid-state imaging device. 4. The solid-state imaging device according to claim 3, wherein the groove-shaped buried metal layer and the light-shielding metal layer are larger as the area surrounding the light receiving section is higher. apparatus. 5. The solid-state imaging device according to claim 3, wherein a side surface of the light-shielding metal layer has a tapered shape. 6. The solid-state imaging device according to claim 3, wherein the metal layer for light shielding comprises:
A solid-state imaging device which is formed simultaneously with the wiring and the wiring metal film of the driving circuit for driving the transistor, and is not electrically connected to the wiring metal film. 7. The solid-state imaging device according to claim 1, wherein the groove-shaped buried metal layer is a single-layer film of Cu.W.TiW or a Cu.W.Ti.
A solid-state imaging device using a composite film of TiW and TiN / TiW / Ti. 8. The solid-state imaging device according to claim 1, wherein the metal layer for shielding is a single-layer film of Al.Al-Si.Al-Cu.Cu.W. , Or Al ・ Al-Si ・ Al-Cu ・ Cu ・ W and W ・ TiN ・ TiW ・
A solid-state imaging device using a composite film with Ti. 9. A solid-state imaging device in which pixel cells each including a light receiving portion and a plurality of transistors are arranged in a matrix on a semiconductor substrate of one conductivity type, and provided with a driving circuit for driving the plurality of transistors. The method of manufacturing a solid-state imaging device according to claim 1, further comprising a step of removing the insulating film on the light receiving section in a groove shape at least twice so as to surround the light receiving section and embedding a metal layer in the groove. Method. 10. The method for manufacturing a solid-state imaging device according to claim 9, wherein the metal layer buried in the groove is formed simultaneously with the metal layer for a wiring connection hole of the transistor and a driving circuit for driving the transistor. A method for manufacturing a solid-state imaging device, which is formed.