JP2008010544A - Solid-state image pickup element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup element that suppresses stray light caused by reflection of incident light from the surface of a semiconductor substrate without deteriorating manufacturing throughput. <P>SOLUTION: An air gap AG1 is formed in a contact interlayer film 7 so as to surround the central part of a photodiode 2 formed in the surface layer of the semiconductor substrate 1. It is possible to restrain stray light L2, caused by reflection of incident light L1 from the surface of the semiconductor substrate, from entering into a neighboring pixel since the air gap AG1 is formed in the contact interlayer film 7. It is not necessary to execute anisotropic etching for forming the air gap AG1 for a long period of time since the air gap AG1 is formed only in the contact interlayer film 7. Consequently, it is also possible to prevent the manufacturing throughput from deteriorating. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device having an air gap for condensing incident light in a desired region.

  In the conventional solid-state imaging device, when incident light is incident on the solid-state imaging device from an oblique direction, the incident light is not incident on a pixel that should be incident on, but is incident on an adjacent pixel as photoelectrical conversion. For this reason, imaging characteristics are deteriorated (crosstalk between adjacent pixels) between adjacent pixels. Therefore, the invention of Patent Document 1 provides an air gap (hollow part) between pixels and optically totally reflects the stray light through the air gap, thereby reducing the probability of obliquely incident light entering adjacent pixels. .

  Prior arts related to the present invention are disclosed in Patent Documents 2 and 3.

US Patent Application Publication No. 2005/0040317 JP-A-8-50308 (see paragraphs [0083] to [0089], FIGS. 54 to 63) Japanese Patent Laid-Open No. 10-41521

  However, in the solid-state imaging device having an air gap in Patent Document 1, no air gap is provided in the contact interlayer film formed below the first-layer metal wiring, so that the position is low due to reflection on the surface of the semiconductor substrate or the like. It is impossible to suppress stray light. As a result, imaging characteristics are deteriorated between adjacent pixels.

  Further, in the structure of Patent Document 1, if the air gap is extended to the contact interlayer film, stray light due to reflection on the surface of the semiconductor substrate or the like can be suppressed. However, it is necessary to set a longer anisotropic dry etching time when forming the air gap, which not only deteriorates the manufacturing throughput but also increases the required resist film thickness accordingly. Is essential. As a result, there arises a problem that the air gap width cannot be reduced.

  Accordingly, the present invention has been made to solve the above-described problems, and provides a solid-state imaging device capable of suppressing stray light due to reflection of incident light on the surface of a semiconductor substrate without deteriorating manufacturing throughput. .

  The solid-state imaging device according to claim 1 includes a photodiode formed on a semiconductor substrate, a first interlayer film formed on the semiconductor substrate so as to cover the photodiode, and the first interlayer film. The central portion of the photodiode is surrounded in plan view by the multilayer wiring formed in the second interlayer film formed above and the first interlayer film between the lowermost wiring and the semiconductor substrate. And a hollow portion formed as described above.

  The solid-state imaging device according to claim 18, a photodiode formed on a semiconductor substrate, an element isolation film embedded in a groove formed in the semiconductor substrate so as to surround the photodiode in plan view, A hollow portion disposed in the element isolation film.

  The solid-state imaging device according to claim 20, wherein a photodiode formed on a semiconductor substrate, an interlayer film formed on the semiconductor substrate so as to cover the photodiode, and a multilayer wiring formed on the interlayer film And a hollow portion formed in the interlayer film so as to surround the center portion of the photodiode in a plan view and disposed on the predetermined wiring.

  The solid-state imaging device according to claim 21, wherein a photodiode formed on a semiconductor substrate, an interlayer film formed on the semiconductor substrate so as to cover the photodiode, and a multilayer wiring formed on the interlayer film A passivation film formed so as to cover the wiring in the uppermost layer, a color filter formed on the passivation film, and the uppermost layer in the color filter so as to surround a central portion of the photodiode. And a hollow portion disposed on the wiring.

  According to the solid-state imaging device of the first aspect, since the hollow portion is provided in the first interlayer film between the lowermost layer wiring and the semiconductor substrate, the reflected light at a low position on the surface of the semiconductor substrate is transmitted to the adjacent pixel. Incident light can be suppressed. As a result, crosstalk between adjacent pixels can be suppressed. Also, by forming the hollow portion only in the first interlayer film between the lowermost wiring and the semiconductor substrate, it is not necessary to perform anisotropic dry etching for forming the hollow portion for a long time, and the manufacturing throughput is deteriorated. I don't have to.

  According to the solid-state image pickup device according to claim 18, since the hollow portion can prevent the oblique incident light from passing to adjacent pixels in the semiconductor substrate, the crosstalk between adjacent pixels can be suppressed and the sensitivity can be improved. Can be realized.

  According to the solid-state imaging device of the twentieth aspect, the etching of the interlayer film for forming the hollow portion can be stopped by the metal wiring. For this reason, it is easy to form the hollow portion only in the interlayer film, and therefore, for example, it is not necessary to form the hollow portion at once at all levels from the uppermost wiring to the surface of the semiconductor substrate. As a result, the required resist film thickness can be reduced, and as a result, the width of the hollow portion can be narrowed, and the cleaning process of the processing apparatus for long-time dry etching can be omitted. Can be improved.

  According to the solid-state imaging device of the twenty-first aspect, since the hollow portion exists in the color filter, it is possible to suppress the incidence of light on the adjacent pixels. As a result, crosstalk between adjacent pixels can be suppressed and sensitivity can be improved.

<Embodiment 1>
<A. Configuration>
FIG. 1 is a cross-sectional view illustrating a configuration of a pixel region of the solid-state imaging device according to the first embodiment. FIG. 2 is a top view showing the configuration of the pixel region of the solid-state imaging device according to the first embodiment. 1 corresponds to a cross-sectional view taken along line AA in FIG. A photodiode 2 is formed on the surface layer of a semiconductor substrate (substrate) 1. An interlayer film composed of a contact interlayer film 7 (first interlayer film) and a via interlayer film 9 (second interlayer film) is formed so as to cover the photodiode 2.

  In the interlayer film, multilayer wiring composed of metal wiring 8 and metal wiring 10 is formed. Specifically, a metal wiring 8, which is the lowermost wiring, is formed on the contact interlayer film 7. A via interlayer film 9 is formed on the contact interlayer film 7 so as to cover the metal wiring 8, and a metal wiring 10 that is the uppermost layer wiring is formed on the via interlayer film 9. A passivation film 11 (also referred to as a glass coat film) is formed so as to cover the metal wiring 10.

  An air gap AG <b> 1 (hollow portion) is formed in the contact interlayer film 7, which is an interlayer film between the metal wiring 8, which is the lowermost wiring, and the semiconductor substrate 1. The width of the air gap AG1 is formed with a width of 200 nm or more so that light can be totally reflected.

As shown in FIG. 2, the air gap AG1 is formed in a quadrangular shape so as to surround the central portion of the photodiode 2 in plan view. As shown in FIG. 2, a MOS transistor is arranged adjacent to the photodiode 2. A gate electrode 4 of the MOS transistor is formed adjacent to the photodiode 2, and an N ⁺ diffusion layer 3 is formed adjacent to the gate electrode 4. A contact hole 5 is provided in the gate electrode 4.

  In FIG. 1, the lower end of the air gap AG1 may or may not be in contact with the surface of the semiconductor substrate 1. Further, FIG. 1 shows obliquely incident light L1 described later and stray light L2 generated by reflection on the surface of the semiconductor substrate.

<B. Manufacturing method>
Next, a method for manufacturing the solid-state imaging device according to the first embodiment will be described with reference to FIGS. 3 to 6 are cross-sectional views illustrating the manufacturing process of the solid-state imaging device according to the first embodiment. Here, since the steps other than the step of forming the air gap AG1 are the same as the known steps for manufacturing the solid-state imaging device, only the step for forming the air gap AG1 will be described below.

  First, in the process shown in FIG. 3, a semiconductor substrate 1 on which a photodiode 2 is formed is prepared. Then, a BPTEOS film 12 having a thickness of 20000 to 30000 mm is formed on the substrate 1 so as to cover the photodiode 2 by the CVD method. Subsequently, after the BPTEOS film is polished by a CMP method, a 1000 to 3000-thick oxide film 13 is formed on the BPTEOS film 12 by a CVD method. Here, as the oxide film 13, a film whose etching rate by wet etching is lower than that of the BPTEOS film 12, for example, a P (plasma) -SiO film is used.

  Next, in the process shown in FIG. 4, a mask for forming the air gap AG1 is formed on the oxide film 13 using a normal photolithography process, and the oxide film 13 and the BPTEOS film 12 are formed by a dry etching method or the like. The groove 14 is formed by etching.

  Next, in the step shown in FIG. 5, the BPTEOS film 12 and the oxide film 13 are wet-etched using hydrofluoric acid. At this time, the etching rate for the wet etching is slower in the oxide film 13 than in the lower BPTEOS film 12, so that the etching of the BPTEOS film 12 proceeds faster, and the shape of the groove 14 is narrower in the width of the frontage portion, The inner width is wide. This is because BPTEOS contains impurities such as B (boron) and P (phosphorus) in the TEOS oxide film, so that the wet etching rate is higher than that of the silicon oxide film not containing impurities.

  Next, in the step shown in FIG. 6, an oxide film 16 is formed so as to fill the trench 14. At this time, the trench 14 is filled with an oxide film 16 having poor step coverage such as a P-SiO film. As a result, the oxide film 16 cannot completely fill the groove 14, and the narrow opening of the groove 14 is blocked. As a result, an air gap AG1 is formed in the groove 14. Further, the contact interlayer film 7 is formed by the BPTEOS film 12 and the oxide films 13 and 16.

  Here, if the groove 14 is simply filled with the oxide film 16, a streak (line) enters the closed portion on the groove 14, and the etching solution may soak into the air gap AG <b> 1 by wet etching or the like in a later process. . Therefore, the stripes on the groove 14 can be reduced by further combining the oxide film formation by HDP (High Density Plasma) -CVD and the etch back. In FIG. 6, the shape of the air gap AG1 is different from that of FIG. 1, but in FIG. 1, the shape of the air gap AG1 is simplified. The same applies to the following embodiments.

<C. Effect>
Before describing the effects of the solid-state imaging device according to the first embodiment, the configuration of a conventional solid-state imaging device will be described for comparison. FIG. 7 is a cross-sectional view showing a configuration of a conventional solid-state imaging device. As shown in FIG. 7, in the conventional solid-state imaging device, the air gap AG <b> 1 </ b> D is formed in the via interlayer film 9, and no air gap is formed in the contact interlayer film 7. Therefore, if the oblique incident light L1 is totally reflected by the air gap AG1D and further reflected by the surface of the semiconductor substrate 1 to become stray light L2 at a low position, the stray light L2 cannot be prevented from entering the adjacent pixels.

  In the solid-state imaging device according to the first embodiment, an air gap AG1 is provided in the contact interlayer film 7 as shown in FIG. Since the reflected light from the surface of the semiconductor substrate 1 is totally reflected by the air gap AG1, it is possible to suppress the reflected light from entering the adjacent pixels as the stray light L2, so that crosstalk between the adjacent pixels can be suppressed. As described above, if the width of the air gap AG1 is 200 nm or more, light having a wavelength necessary for the sensor can be totally reflected.

  Further, since there is no air gap in the via interlayer film 9 and the air gap AG1 is formed only in the contact interlayer film 7, it is not necessary to perform anisotropic dry etching for forming the air gap AG1 for a long time. Deterioration of manufacturing throughput can be suppressed.

  In the solid-state imaging device according to the first embodiment, since there is no air gap in the via interlayer film 9, oblique incident light L1 incident on a high position such as on the first-layer metal wiring 8 is applied to adjacent pixels. Incidence is possible. However, most of the light is condensed to some extent by a microlens formed on the color filter on the chip and an inner lens (also referred to as an inner lens) formed on the passivation film 11 (also referred to as a glass coat film). Therefore, since the amount of light incident at an angle that may be incident on an adjacent pixel from a high position such as on the first-layer metal wiring 8 is small, there is substantially no problem.

<Embodiment 2>
<A. Configuration>
FIG. 8 is a cross-sectional view showing the configuration of the pixel region of the solid-state imaging device according to the second embodiment. In the solid-state imaging element according to the second embodiment, the upper end of the air gap AG2 (hollow part) is extended to a position higher than the height of the metal wiring 10 that is the adjacent uppermost layer wiring. Other configurations are the same as those of the first embodiment, and the same components as those of the first embodiment are denoted by the same reference numerals and redundant description is omitted.

<B. Manufacturing method>
In the solid-state imaging device according to the second embodiment, the air gap AG2 is formed by applying the formation method of the air gap AG1 described in the first embodiment to the contact interlayer film 7, the via interlayer film 9, and the passivation film 11. Can be formed. Since other manufacturing methods are the same as those in the first embodiment, detailed description thereof is omitted.

<C. Effect>
In the solid-state imaging device according to the second embodiment, the upper end of the air gap AG2 extends to a position higher than the height of the metal wiring 10 which is the uppermost wiring. Since the gap between the upper end of the air gap AG2 and the adjacent metal wiring 10 is small, the oblique incident light L1 at a high position passing over the metal wiring 8 or the metal wiring 10 is changed to the metal wiring 8 or the metal wiring 10. There is no risk of entering the adjacent pixels through the gap between the air gap AG2.

  Further, since the obliquely incident light L1 is blocked by the air gap AG2, the light does not strike the side walls of the metal wirings 8 and 10, and the amount of reflected light on the side walls of the metal wiring is increased due to irregularities on the side walls of the metal wiring and shape variations due to etching variations. And the reflection direction of reflected light does not vary.

<Embodiment 3>
<A. Configuration>
FIG. 9 is a cross-sectional view showing the configuration of the pixel region of the solid-state imaging device according to the third embodiment. In the solid-state imaging device according to the third embodiment, the upper end of the air gap AG3 (hollow part) extends to a position lower than the metal wiring 10 that is the adjacent uppermost wiring. An interval S from the upper end of the air gap AG3 to the lower side of the adjacent metal wiring 10 is set to 0.5 to 3 times the width of the air gap AG3.

  Here, the grounds for setting the distance S to a distance 0.5 to 3 times the width of the air gap AG3 will be described. After forming a groove to be the air gap AG3 in the contact interlayer film 7 and the via interlayer film 9, the lower limit of the film thickness necessary to cap the opening of the groove is 0.5 times the air gap width. .

  The factors that determine the upper limit value of the film thickness are the film thickness variation necessary for capping the groove and the film thickness necessary for flattening the interlayer film on the air gap. Further, in order to realize an oblique incident angle that is generally required as a sensor, characteristic deterioration is caused even if the film thickness is too thick. Therefore, the optimum value is 0.5 to 3 times the air gap width. That is, the interval S is 0.5 to 3 times the width of the air gap AG3. Other configurations are the same as those of the first embodiment, and the same components as those of the first embodiment are denoted by the same reference numerals and redundant description is omitted.

<B. Manufacturing method>
In the solid-state imaging device according to the third embodiment, the air gap AG3 is formed by applying the method for forming the air gap AG1 described in the first embodiment to the contact interlayer film 7 and the via interlayer film 9. Can do. Since other manufacturing methods are the same as those in the first embodiment, detailed description thereof is omitted.

<C. Effect>
In the solid-state imaging device according to the third embodiment, the upper end of the air gap AG3 is lower than the lower side of the adjacent metal wiring 10 by a distance S that is 0.5 to 3 times the width of the air gap AG3. Therefore, as compared with the solid-state imaging device according to the second embodiment, the incident efficiency is not lowered due to oblique incident light being caused by the upper end of the air gap AG3.

<Embodiment 4>
<A. Configuration>
FIG. 10 is a cross-sectional view showing the configuration of the pixel region of the solid-state imaging device according to the fourth embodiment. The solid-state imaging device according to the fourth embodiment is provided with an antireflection film 17 for making it difficult to reflect light incident on the photodiode 2. The antireflection film 17 generally uses an insulating film having a higher refractive index than that of a silicon oxide film (SiO ₂ film) and lower than that of Si. For example, a silicon nitride film (Si ₃ film) is used. An insulating film made of a material such as N ₄ ) or silicon oxynitride film (SiON) is used.

  In the example of the fourth embodiment, a silicon nitride film is used as the antireflection film 17. The lower end of the air gap AG4 exists in the antireflection film 17, and the upper end of the air gap AG4 is disposed under the uppermost metal wiring 10. Other configurations are the same as those of the first embodiment, and the same components as those of the first embodiment are denoted by the same reference numerals and redundant description is omitted. In FIG. 10, since the antireflection film 17 is used as a stopper when etching the groove, the lower end of the air gap AG4 exists in the antireflection film 17, but the antireflection film 17 is described later. It may be present above. Further, the antireflection film may have a laminated structure of, for example, a silicon nitride film, a silicon oxide film, and a silicon nitride film. As a result, the antireflection effect is enhanced and etching can be stopped at a desired position in the antireflection film.

<B. Manufacturing method>
In the solid-state imaging device according to the fourth embodiment, the air gap AG4 is formed by forming the air gap AG1 described in the first embodiment after forming the antireflection film 17 directly on the photodiode 2, using the contact layer. It can be formed by applying to the film 7 and the via interlayer film 9. Here, the antireflection film also has a role as an etching stopper at the time of dry etching of the groove. Therefore, the material of the antireflection film needs to be different from that of the contact interlayer film. Since other manufacturing methods are the same as those in the first embodiment, detailed description thereof is omitted.

<C. Effect>
As described in the first embodiment, when the air gap AG4 is formed, it is necessary to first form a groove formed so as to surround the center portion of the photodiode 2, and this groove is generally formed by anisotropic dry etching. Open by. When dry etching for opening the groove is performed, if the dry etching reaches the semiconductor substrate 1 on the photodiode 2, a dark current (a minute leak current) is generated due to a lattice defect caused by the dry etching.

  However, in order to prevent the dry etching for forming the air gap AG4 from reaching the surface of the semiconductor substrate 1, it is necessary to perform dry etching by time designation. In consideration of variations in the finished film thickness of the contact interlayer film 7 and the via interlayer film 9 in which the air gap AG4 is formed, dry etching by time designation has a problem in manufacturing stability.

  In the solid-state imaging device according to the fourth embodiment, an antireflection film 17 is provided immediately above the photodiode 2. Therefore, when forming a groove for forming the air gap AG4, the antireflection film 17 can be used as an etching stopper film, and dry etching can be stopped in the film of the antireflection film 17.

  As a result, the surface of the semiconductor substrate is not etched by the dry etching for forming the air gap, so that a dark current due to a defect caused by the dry etching of the surface of the semiconductor substrate does not occur. Further, even when the time-specified etching is performed, the antireflection film 17 does not cause dry etching damage to the photodiode surface even when the contact interlayer film 7 fluctuates greatly in a very thin direction.

  In the solid-state imaging device according to the fourth embodiment, the lower end of the air gap AG4 has a structure that stops on or in the silicon nitride film as the antireflection film 17, but the structure is not limited to this structure. Absent. For example, if possible, dry etching may be stopped at an intermediate position of the contact interlayer film 7. It is also possible to provide a new film made of a material different from that of the contact interlayer film 7 which does not have a function as an antireflection film, and to stop dry etching on or in the film.

  That is, the case where the film stops in a film made of a material different from that of the contact interlayer film 7 existing before reaching the surface of the semiconductor substrate is also included. In addition, the case where the dry etching is stopped by the antireflection film 17 to form a groove and the groove is slightly buried to finally include the case where the lower end of the air gap AG14 exists in the contact interlayer film 7 is also included.

<Embodiment 5>
<A. Configuration>
FIG. 11 is a cross-sectional view showing the configuration of the pixel region of the solid-state imaging device according to the fifth embodiment. As shown in FIG. 11, the N-type photodiode 2 includes a P-type (first conductivity type) P-well region 38 (first impurity region) and an N-type (first-type) disposed in the surface layer portion of the P-well region 38. 2 conductivity type) N ⁻ region 36 (second impurity region). The air gap AG5 (hollow portion) is disposed on the P well region 38. That is, the lower end of the air gap AG5 is disposed on the semiconductor substrate 1 having the same potential as the P well region 38.

  In the fifth embodiment, the upper end of the air gap AG5 is formed above the uppermost metal wiring 10. Other configurations are the same as those of the first embodiment, and the same components are denoted by the same reference numerals, and redundant description is omitted.

<B. Manufacturing method>
In the solid-state imaging device according to the fifth embodiment, for the air gap AG5, the method for forming the air gap AG1 described in the first embodiment is applied to the contact interlayer film 7, the via interlayer film 9, and the passivation film 11. Can be formed. Since the other method of manufacturing the solid-state imaging device is the same as that of the first embodiment, detailed description thereof is omitted.

<C. Effect>
Hereinafter, the case of the N-type photodiode 2 will be described. In order to form the N-type photodiode 2, generally, a P-type P well region 38 is formed in the N-type semiconductor substrate 1 by ion implantation and heat treatment, and then an N-type impurity is ion-implanted. In this way, an N ⁻ / P ⁻ well photodiode 2 is formed. Here, in the case of forming a P-type photodiode, all of the above conductivity types may be considered in the opposite direction.

  The solid-state imaging device according to the fifth embodiment can eliminate etching damage to the photodiode 2 by stopping the dry etching for forming the air gap AG5 on the P-well region 38, such as leakage current. It is difficult to cause defects. As a result, the solid-state imaging device according to the fifth embodiment does not need to be provided with a silicon nitride film such as the antireflection film 17 as compared with the solid-state imaging device according to the fourth embodiment, and the manufacturing process can be reduced. Note that the lower end of the air gap AG5 does not need to be in contact with the semiconductor substrate 1, and a region where dry etching is stopped may be provided in the region of the P well and the conductive potential.

<Embodiment 6>
<A. Configuration>
FIG. 12 is a cross-sectional view showing the configuration of the pixel region of the solid-state imaging device according to the sixth embodiment. As shown in FIG. 12, an air gap AG <b> 61 (hollow part) is formed on the semiconductor substrate 1 so as to surround the center part of the photodiode 2. A metal wiring 8 is disposed above the air gap AG61. An air gap AG62, which is another hollow portion, is formed in the via interlayer film 9 so as to surround the center portion of the photodiode 2 in a plan view and on the metal wiring 8 that is a predetermined wiring. The metal wiring 10 is disposed above the air gap AG62. Other configurations are the same as those of the first embodiment, and the same components as those of the first embodiment are denoted by the same reference numerals and redundant description is omitted.

<B. Manufacturing method>
In the solid-state imaging device according to the sixth embodiment, the air gap AG62 can be formed by applying the method for forming the air gap AG1 described in the first embodiment to the via interlayer film 9 on the metal wiring 8. Further, the air gap AG61 can be formed by the method of forming the air gap AG1 of Embodiment 1 except for the formation position. Since the other method of manufacturing the solid-state imaging device is the same as that of the first embodiment, detailed description thereof is omitted.

<C. Effect>
In the solid-state imaging device according to the sixth embodiment, since the air gap AG62 is arranged on the metal wiring 8, the etching of the via interlayer film 9 for forming the air gap AG62 can be stopped by the metal wiring 8. Therefore, the air gap AG62 can be easily formed only in the via interlayer film 9, so that it is not necessary to form the air gap at a time from the uppermost metal wiring 10 to the surface of the semiconductor substrate all at once. Therefore, the resist film thickness required for the dry etching can be reduced, and as a result, the widths of the air gaps AG61 and AG62 can be reduced, and the process margin can be improved and the pixel area can be reduced. In addition, since the apparatus cleaning process by dry etching for a long time can be omitted, the manufacturing throughput can be improved.

  Further, in the solid-state imaging device according to the sixth embodiment, as shown in FIG. 12, air gaps AG61 and AG62 and metal wirings 8 and 10 cover most regions from the uppermost metal wiring 10 to the surface of the semiconductor substrate 1. It can also be enclosed with.

  Note that it is not necessary to cover from under the uppermost metal wiring 10 to the surface of the semiconductor substrate with the air gaps AG61 and AG62. For example, the air gap AG61 in the contact interlayer film 7 may not exist. Further, in FIG. 12, the air gap AG <b> 62 may be on the metal wiring 10 instead of on the metal wiring 8.

  Further, the air gap AG2 of the via interlayer film 9 does not need to completely surround the photodiode 2. In addition to the metal wirings 8 and 10, the metal wiring is used in various parts for connecting elements in the pixel. Even if the air etching is stopped in the metal wiring used in the circuit, the metal wiring is used. Alternatively, it may be stopped by a floating metal wiring such as a dummy metal.

  Further, in the sixth embodiment, the air gap AG61 is arranged outside the photodiode 2, but as shown in the first embodiment, it may be formed on the photodiode 2.

<Embodiment 7>
<A. Configuration>
FIG. 13 is a cross-sectional view showing the configuration of the pixel region of the solid-state imaging device according to the seventh embodiment. As shown in FIG. 13, in the solid-state imaging device according to the seventh embodiment, an air gap AG <b> 7 (hollow part) is formed across the contact interlayer film 7 and the via interlayer film 9. The air gap AG7 includes an air gap AG71 (first hollow portion) and an air gap AG72 (second hollow portion) formed on the air gap A71.

  And as shown in FIG. 13, the width | variety of the air gap AG72 is narrower than the width | variety of the air gap AG71. Other configurations are the same as those of the first embodiment, and the same components as those of the first embodiment are denoted by the same reference numerals and redundant description is omitted.

<B. Manufacturing method>
In the solid-state imaging device according to the seventh embodiment, the air gap AG7 is formed by applying the formation method of the air gap AG1 described in the first embodiment to the two layers of the contact interlayer film 7 and the via interlayer film 9. it can. Here, the groove for forming the air gap AG72 is formed to be thinner than the groove for forming the air gap AG71. Since the other method of manufacturing the solid-state imaging device is the same as that of the first embodiment, detailed description thereof is omitted.

<C. Effect>
In the solid-state imaging device according to the seventh embodiment, the width of the upper air gap AG72 is narrower than the width of the lower air gap AG71. Therefore, the area surrounded by the air gap AG72 is the air gap AG71. It can be wider than the area surrounded by. Therefore, rather than forming an air gap from the lower layer to the upper layer with the same width as the air gap A71, it becomes easier for obliquely incident light to enter the region surrounded by the air gap AG7 (light is not easily lost), and the sensor The characteristics can be improved.

  Note that the air gap AG7 does not need to be formed continuously with the wide air gap AG71 and the thin air gap AG72. For example, as shown in the sixth embodiment, the air gap AG7 is formed below the metal wiring 8 of the contact interlayer film 7. A narrow air gap AG72 may be formed on the metal wiring 8 by forming the wide air gap AG71 and etching the via interlayer film 9 using the metal wiring 8 as a stopper.

<Eighth embodiment>
<A. Configuration>
FIG. 14 is a cross-sectional view showing the configuration of the pixel region of the solid-state imaging device according to the eighth embodiment. FIG. 14 corresponds to a cross section taken along line BB in FIG. A MOS transistor constituting a circuit in the pixel is formed on the semiconductor substrate 1 and is disposed adjacent to the photodiode 2. An N ⁺ diffusion layer 3 of the MOS transistor is arranged next to the photodiode 2.

A gate insulating film 22 is formed on the semiconductor substrate 1 so as to straddle the photodiode 2 and the N ⁺ diffusion layer 3, and a gate electrode 4 is formed on the gate insulating film 22. An air gap AG <b> 8 is formed so as to surround the center portion of the photodiode 2. The air gap AG8 includes a region arranged on the gate electrode 4. Other configurations are the same as those of the first embodiment, and the same components as those of the first embodiment are denoted by the same reference numerals and redundant description is omitted.

<B. Manufacturing method>
In the solid-state imaging device according to the eighth embodiment, the air gap AG8 applies the method for forming the air gap AG1 described in the first embodiment to the contact interlayer film 7, the via interlayer film 9, and the passivation film 11. Can be formed. Since the other method of manufacturing the solid-state imaging device is the same as that of the first embodiment, detailed description thereof is omitted.

<C. Effect>
In the fourth and fifth embodiments, the invention has been described in which dry etching for opening a groove for forming an air gap is stopped on the antireflection film 17 or the P well region 38. In the eighth embodiment, dry etching for opening a groove for forming an air gap is stopped on the gate electrode 4. Normally, the contact hole for the gate electrode 4 (connection hole to the first-layer metal wiring 8) is made on a region having a large oxide film thickness, such as on the element isolation film. It may extend over both of the element isolation and the active region.

  The solid-state imaging device according to the eighth embodiment does not require a process for newly providing a region having the same potential as that of the antireflection film 17 or the semiconductor substrate 1 as in the fourth and fifth embodiments. Cost can be reduced. The gate electrode 4 for stopping the dry etching is used for the MOS transistor constituting the circuit in the pixel, and is not provided by adding a new process.

  Therefore, the manufacturing cost does not increase. Further, the gate electrode 4 may be a gate electrode used for constituting a circuit, or may be a floating gate electrode in terms of potential, and the air gap AG8 has no conductivity. So it doesn't matter at all. The lower end of the air gap AG8 on the gate electrode 4 may exist in the gate electrode 4 or may exist at a position higher than the height of the gate electrode 4.

<Embodiment 9>
<A. Configuration>
FIG. 15 is a cross-sectional view illustrating the configuration of the pixel region of the solid-state imaging device according to the ninth embodiment. FIG. 16 is a plan view showing the configuration of the pixel region of the solid-state imaging device according to the ninth embodiment. FIG. 15 corresponds to a cross-sectional view taken along the line CC of FIG. A passivation film 11 is formed so as to cover the metal wiring 10 which is the uppermost layer wiring. A color filter 25 that allows only one of R / G / B light to pass through in each pixel is formed on the passivation film 11. As shown in FIGS. 15 and 16, an air gap AG <b> 9 (hollow part) is formed in the color filter 25 so as to surround the center part of the photodiode 2 in plan view, and on the metal wiring 10 that is the uppermost layer wiring. Is arranged.

  On the color filter 25, a microlens 23 for collecting incident light is formed. Here, there is also a gap between the microlens 23 and the upper end of the air gap AG9. Other configurations are the same as those of the first embodiment, and the same components as those of the first embodiment are denoted by the same reference numerals and redundant description is omitted.

  In FIG. 15, the air gap AG <b> 9 is formed to stop on the passivation film 11 on the sensor device resurface, but may be formed to stop on the uppermost metal wiring 10.

<B. Manufacturing method>
In the solid-state imaging device according to the ninth embodiment, the air gap AG9 can be formed by applying the method for forming the air gap AG1 described in the first embodiment to the color filter 25. Since the other method of manufacturing the solid-state imaging device is the same as that of the first embodiment, detailed description thereof is omitted.

<C. Effect>
In the solid-state imaging device according to the ninth embodiment, the presence of the air gap AG9 also in the color filter 25 can suppress the incidence of light on adjacent pixels. Further, in the step of etching the color filter 25 to form the air gap AG9, the etching can be stopped at the passivation film 11 or the uppermost metal wiring 10, so that the manufacturing margin can be greatly increased. Further, since there is a gap between the microlens 23 and the upper end of the air gap AG9, when the gap between the microlens 23 is very small or not, the light condensed at the end of the microlens can be efficiently air. The region is surrounded by the gap AG9.

  When the air gap AG9 is formed by performing dry etching from the surface of the color filter 25 to the surface of the semiconductor substrate, the cleaning frequency increases due to long-time dry etching processing. Moreover, the greatest concern is a decrease in yield due to the occurrence of foreign matter. However, since the solid-state imaging device according to the ninth embodiment does not have a long-time dry etching process, it can be manufactured stably with a high yield.

  In the ninth embodiment, the air gap AG9 is formed in the color filter 25. However, an air gap may be further formed in the contact interlayer film 7 or the via interlayer film 9.

<Embodiment 10>
<A. Configuration>
FIG. 17 is a cross-sectional view showing the configuration of the solid-state imaging device according to the tenth embodiment. In the solid-state imaging device according to the tenth embodiment, an air gap AG <b> 10 (hollow part) is formed so as to be in contact with the metal wiring 8. The air gap AG10 according to the tenth embodiment is an air gap formed in a self-aligning manner using the metal wiring 8 as a mask. Other configurations are the same as those of the first embodiment, and the same components are denoted by the same reference numerals, and redundant description is omitted.

<B. Manufacturing method>
Next, a method for manufacturing the solid-state imaging device according to the tenth embodiment will be described with reference to FIGS. 18 and 19 are cross-sectional views showing manufacturing steps of the solid-state imaging device according to the tenth embodiment. First, according to a normal process, a semiconductor substrate 1 having a metal wiring 8 formed on a contact interlayer film 7 is prepared. Next, an oxide film is formed on the contact interlayer film 7 so as to cover the metal wiring 8 by the CVD method, and is planarized by the CMP method, thereby forming the interlayer film 41. Next, a photoresist 40 is formed on the interlayer film 41 by a photolithography process so that the opening 42 overlaps the metal wiring 8 in a plan view.

  Next, in the process shown in FIG. 20, the groove 43 is formed by etching the interlayer film 41 and the contact interlayer film 7 by dry etching using the photoresist 40 as a mask. At this time, the groove 43 is formed in a self-aligning manner so as to be in contact with the metal wiring 8 using the metal wiring 8 as a mask.

  After removing the photoresist 40, the trench 43 is filled with a film having poor step coverage. At this time, in the film having poor step coverage, the groove 43 cannot be completely filled, and the air gap AG10 is formed. Through the above processes, the solid-state imaging device according to the tenth embodiment forms the air gap AG10 so as to be in contact with the metal wiring 8 by performing self-aligned etching. Subsequently, after forming the air gap AG10, a solid-state imaging device can be obtained through processes such as formation of the uppermost metal wiring 10 and formation of the passivation film 11.

<C. Effect>
Conventionally, a groove for forming an air gap has to be formed at a certain distance from the metal wiring 8 so as not to collide with the metal wiring 8, and as a result, the groove for forming the air gap is formed in the center photo. It had to be moved to the diode 2 side. As a result, the area surrounded by the air gap is reduced, which makes it difficult for light to enter.

  In the solid-state imaging device according to the tenth embodiment, the opening 42 of the photoresist 40 serving as a mask when dry etching for air gap formation is performed so as to reach the metal wiring 8 in advance. In general, the air gap AG10 is formed so as not to collide with the metal wiring 8, but in the tenth embodiment, the metal wiring 8 is used to perform self-aligned air gap forming dry etching. It is said. Therefore, the air gap AG10 can be brought close to the metal wiring 8. As a result, since the area surrounded by the air gap AG10 is widened, the amount of incident light can be increased.

  In the tenth embodiment, the method of forming the air gap using the metal wiring 8 as a mask has been described. However, even if the metal wiring 10 is used as a mask, the air gap can be formed in a self-aligning manner. it can.

<Embodiment 11>
<A. Configuration>
FIG. 20 is a plan view showing the configuration of the pixel region of the solid-state imaging device according to the eleventh embodiment. A MOS transistor is formed on the semiconductor substrate 1 and arranged adjacent to the photodiode 2. An air gap AG11 (hollow portion) is formed so as to sandwich the gate electrode 4 of the MOS transistor in plan view. That is, the air gap AG11 is not formed on the gate electrode 4, but is formed in a shape in which the line is not closed, instead of a shape in which the line is closed like a ring shape in plan view.

  The air gap AG11 may be formed by combining four linear air gaps. At this time, the four air gaps do not need to be continuously connected as shown in FIG. 20, and the four air gaps may be formed apart from each other. Other configurations are the same as those in FIG. 2 of the first embodiment, and the same components as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

<B. Manufacturing method>
Since the manufacturing method of the solid-state imaging device according to the eleventh embodiment is the same as that of the first embodiment except that the air gap AG11 is formed so as to sandwich the gate electrode 4 in plan view, the detailed description is omitted. To do.

<C. Effect>
In order to form an air gap on the gate electrode 4, it is necessary to perform dry etching for forming the air gap also on the gate electrode 4. At this time, since the gate electrode 4 is usually present at a position higher than the active region, only the groove for forming an air gap on the gate electrode 4 has a disadvantage that the groove width becomes large and it is difficult to cap.

  Since the air gap AG11 is not formed on the gate electrode 4 in the solid-state imaging device according to the eleventh embodiment, the air gap AG11 having a substantially uniform width is not easily capped. Can be formed.

  In addition, when the air gap is formed in a ring shape so as to avoid the gate electrode 4, the area of the region surrounded by the air gap is reduced, and the collection efficiency of incident light deteriorates when the light collection rate by the microlens is not high. there is a possibility. In the solid-state imaging device according to the eleventh embodiment, since the air gap AG11 is not formed in a ring shape, the area surrounded by the air gap AG11 can be increased, and incident light collection efficiency does not deteriorate.

<Embodiment 12>
<A. Configuration>
FIG. 21 is a plan view showing the configuration of the pixel region of the solid-state imaging device according to the twelfth embodiment. In the solid-state imaging device according to the twelfth embodiment, a polygonal air gap AG12 (hollow portion) having a pentagon or more corners in plan view is formed. In the example of FIG. 21, an octagonal air gap AG12 is formed. Other configurations are the same as those in FIG. 2 of the first embodiment, and the same components as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

<B. Manufacturing method>
Since the manufacturing method of the solid-state imaging device according to the twelfth embodiment is the same as that of the first embodiment except that the air gap AG12 is formed in a polygon, a detailed description thereof will be omitted.

<C. Effect>
If the air gap has a rectangular or square shape as usual, as shown in FIG. 22, the groove width of the upper side of the groove 44 opened to form the air gap is larger than the groove width A of the straight portion. Thus, the groove width B at the corner portion becomes larger. Here, FIG. 22 is a diagram illustrating a configuration of a part of the groove 44 formed in a rectangular shape or a square shape in a plan view.

  This difference in the width of the upper side of the groove affects the characteristics when the groove is capped. In other words, the larger the width of the upper side, the harder it is to be capped, and the deposition film thickness required for capping must be increased. When the deposited film thickness is increased, for example, if a contact hole is to be formed in the contact interlayer film 7, there is a concern that the depth of the contact hole becomes deeper and the hole diameter becomes smaller, leading to deterioration in yield.

  In the twelfth embodiment, the air gap AG12 is formed in a polygonal shape of a pentagon or more in order to reduce the width of the upper side of the corner portion. As a result, the width of the upper side of the groove serving as the air gap AG12 is substantially the same in the corner portion and the straight portion, and the deposition film thickness necessary for capping the groove can be made uniform. As a result, yield deterioration can be suppressed.

  In the solid-state imaging device according to the twelfth embodiment, the air gap AG12 in which the sides of the polygon are closed has been described. For example, a part of the polygon may not be connected, and as a result, a portion that bends at a right angle. It is only necessary that the groove is easily capped by bending at a smaller angle than a right angle. If the air gap is circular, the groove width can be made uniform over the entire circumference.

<Embodiment 13>
<A. Configuration>
FIG. 23 is a cross-sectional view showing the configuration of the pixel region of the solid-state imaging device according to the thirteenth embodiment. An inner lens (inner lens) 29 is formed on the passivation film 11 according to the thirteenth embodiment. Here, unlike the microlens formed on the color filter, the in-layer lens 29 is a lens provided above the uppermost metal wiring 10 using the same material as that forming the solid-state imaging device. It is. As a material of the intralayer lens 29, a silicon nitride film (Si ₃ N ₄ film) or a silicon oxynitride film (SiON film) having a refractive index higher than that of the silicon oxide film (SiO ₂ ) is often used.

  In the thirteenth embodiment, both the intralayer lens 29 and the air gap AG13 (hollow part) exist inside the solid-state imaging device. The height of the air gap AG13 is set to a height that does not block the incident light L1 collected by the intralayer lens 29. Here, the condensable range R <b> 1 indicates a range in which incident light can be collected by the intralayer lens 29. Other configurations are the same as those of the first embodiment, and the same components as those of the first embodiment are denoted by the same reference numerals and redundant description is omitted.

<B. Manufacturing method>
Since the manufacturing method of the solid-state imaging device according to the thirteenth embodiment is the same as that of the first embodiment except that the in-layer lens 29 is formed, detailed description thereof is omitted.

<C. Effect>
For example, in a solid-state imaging device provided with only the in-layer lens 29 with a fixed curvature, the shape of the in-layer lens 29 changes when the total film thickness of the contact interlayer film 7, the via interlayer film 9 and the passivation film 11 varies. There is a risk that light may not be collected well on the photodiode 2 due to variations, and light may enter the adjacent pixels.

  On the other hand, in a solid-state imaging device provided with only an air gap, when the height of the air gap is low, oblique incident light may enter the adjacent pixel through the air gap. Therefore, it is necessary to make the air gap higher than the uppermost metal wiring 10, and there is a concern that the yield may decrease due to the generation of foreign matter during dry etching for forming the air gap.

  In the solid-state imaging device according to the fourteenth embodiment, the height of the air gap AG13 is increased to the condensable range R1 that can be collected by the inner lens 29. Therefore, the incidence of light on adjacent pixels can be suppressed almost completely. As a result, the manufacturing margin can be increased, and not only the yield can be improved, but also the production efficiency can be improved.

<Embodiment 14>
<A. Configuration>
FIG. 24 is a plan view showing the configuration of the pixel region of the solid-state imaging device according to the fourteenth embodiment. In the solid-state imaging device according to the fourteenth embodiment, an air gap AG14 (hollow part) similar to the hexagonal inner lens 29 is formed in plan view. Other configurations are the same as those of the twelfth embodiment, and the same components as those of the twelfth embodiment are denoted by the same reference numerals and redundant description is omitted.

<B. Manufacturing method>
The manufacturing method of the solid-state imaging device according to the fourteenth embodiment is the same as that of the first embodiment except that the air gap AG14 having a shape similar to that of the intralayer lens 29 is formed.

<C. Effect>
FIG. 25 is a plan view showing a configuration of a pixel region of a solid-state imaging device including a rectangular air gap AG14D and an octagonal inner lens 29 in plan view. In such a solid-state imaging device, the light condensed in the region R2 by the intralayer lens 29 cannot enter the air gap AG14D.

  As shown in FIG. 24, the solid-state imaging device according to the fourteenth embodiment has an air gap AG14 that is similar in shape to the intralayer lens 29 in plan view, and therefore can collect light efficiently. As described above, in the fourteenth embodiment, the air gap AG14 and the in-layer lens 29 may have similar plane shapes. For example, the air gap AG14 is hexagonal, but the corner portion is cut off to form six It may be only the side.

<Embodiment 15>
<A. Configuration>
FIG. 26 is a cross-sectional view showing the configuration of the pixel region of the solid-state imaging device according to the fifteenth embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted. An N ⁺ diffusion layer 3 is formed at a predetermined distance from the N ⁻ region 36 in the surface layer portion of the P well region 38 formed in the semiconductor substrate 1. A gate electrode 4 is formed on the semiconductor substrate 1 so as to cover the P ⁺ region 35, the N ⁻ region 36, and the P well region 38 with the gate insulating film 22 interposed therebetween. Sidewalls 32 are formed on the side walls of the gate electrode 4.

In FIG. 26, the photodiode 2 is formed by a junction between the surface P ⁺ region 35 and the P well region 38 and the N ⁻ region 36. As shown in FIG. 26, an element isolation film 33 such as STI is formed so as to surround the active region in which the photodiode 2 and the MOS transistor are formed in a plan view. An air gap AG <b> 15 (hollow part) is formed in the semiconductor substrate 1 and is disposed under the element isolation film 33. Here, the air gap AG <b> 15 is disposed in a groove for forming the element isolation film 33.

<B. Manufacturing method>
Next, a method for manufacturing the solid-state imaging element according to the fifteenth embodiment will be described. Since the method other than the method of forming the air gap AG15 is the same as the conventional method, only the method of manufacturing the air gap AG15 will be described. First, a groove (trench) such as STI is formed in the semiconductor substrate 1. Next, when the insulating film is embedded in the groove, the groove is not completely embedded.

  That is, in STI, a trench is generally formed on the surface of a semiconductor substrate and an oxide film is buried therein, but at that time, the trench is not completely buried, thereby forming an air gap 34. Specifically, the filling is performed using an oxide film such as a P-SiO film having poor filling characteristics. As a result, the air gap AG15 and the element isolation film 33 are formed so as to surround and cover the air gap AG15.

<C. Effect>
Since the solid-state imaging device according to the fifteenth embodiment includes the air gap AG15, it is possible to suppress the oblique incident light from passing through to adjacent pixels in the semiconductor substrate 1, and as a result, the cross-pixel cross Talk can be suppressed and sensitivity can be improved. In addition, by providing a hollow portion having a low dielectric constant in the element isolation, the original isolation characteristics of the element isolation can be improved.

  In the fifteenth embodiment, an air gap may be further formed in the contact interlayer film 7 and the via interlayer film 9 as in the first and second embodiments.

<Embodiment 16>
<A. Configuration>
FIG. 27 is a cross-sectional view showing a configuration of the solid-state imaging device according to the sixteenth embodiment. In the solid-state imaging device according to the sixteenth embodiment, a P-type impurity is added to a region surrounded by the element isolation film 33 at a higher concentration than the P-well region 38 so as to be adjacent to the photodiode 2. ⁺⁺ region 37 (third impurity region) is formed. Other configurations are the same as those of the fifteenth embodiment, and the same components are denoted by the same reference numerals, and redundant description is omitted.

<B. Manufacturing method>
In the solid-state imaging device according to the sixteenth embodiment, a P ⁺⁺ region 37 is formed between the photodiode 2 and the element isolation film 33 by ion implantation or the like. Since other manufacturing methods are the same as those in the fifteenth embodiment, detailed description thereof is omitted.

<C. Effect>
When the semiconductor substrate 1 is separated by the air gap AG15 as in the fifteenth embodiment, the metal atoms present in the photodiode 2 are difficult to getter and there is a concern about deterioration due to dark current.

Therefore, the solid-state imaging device according to the sixteenth embodiment is provided with a P ⁺⁺ region 37 in which an impurity capable of gettering metal atoms is added in a high concentration within a region surrounded by the air gap 34. Therefore, the gettering effect can be obtained even in the region surrounded by the air gap 34. As a result, dark current can be suppressed. It should be noted that the P ⁺⁺ region 37 is also effective when provided in the semiconductor substrate 1 on the left and right sides or below the air gap AG15.

3 is a cross-sectional view illustrating a configuration of a pixel region of the solid-state imaging element according to Embodiment 1. FIG. 3 is a top view illustrating a configuration of a pixel region of the solid-state imaging element according to Embodiment 1. FIG. 5 is a cross-sectional view showing a manufacturing process of the solid-state imaging device according to Embodiment 1. FIG. 5 is a cross-sectional view showing a manufacturing process of the solid-state imaging device according to Embodiment 1. FIG. 5 is a cross-sectional view showing a manufacturing process of the solid-state imaging device according to Embodiment 1. FIG. 5 is a cross-sectional view showing a manufacturing process of the solid-state imaging device according to Embodiment 1. FIG. 1 is a cross-sectional view illustrating a configuration of a conventional solid-state imaging element according to Embodiment 1. FIG. 6 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state imaging element according to Embodiment 2. FIG. 6 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state imaging element according to Embodiment 3. FIG. 6 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state imaging device according to Embodiment 4. FIG. FIG. 10 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state imaging element according to a fifth embodiment. 10 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state imaging element according to Embodiment 6. FIG. FIG. 10 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state image sensor according to a seventh embodiment. FIG. 10 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state imaging element according to an eighth embodiment. FIG. 10 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state imaging element according to a ninth embodiment. FIG. 10 is a plan view illustrating a configuration of a pixel region of a solid-state imaging element according to a ninth embodiment. FIG. 10 is a cross-sectional view illustrating a configuration of a solid-state imaging element according to Embodiment 10. FIG. 25 is a cross-sectional view showing a manufacturing process of the solid-state imaging element according to the tenth embodiment. FIG. 25 is a cross-sectional view showing a manufacturing process of the solid-state imaging element according to the tenth embodiment. 22 is a plan view showing a configuration of a pixel region of a solid-state imaging element according to Embodiment 11. FIG. FIG. 22 is a plan view illustrating a configuration of a pixel region of a solid-state imaging element according to Embodiment 12. FIG. 38 is a plan view showing a configuration of a part of a groove formed in a rectangle or a square in plan view according to the twelfth embodiment. FIG. 34 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state imaging element according to Embodiment 13. FIG. 38 is a plan view showing a configuration of a pixel region of a solid-state imaging element according to a fourteenth embodiment. FIG. 38 is a plan view showing a configuration of a pixel region of a solid-state imaging device including a rectangular air gap and a hexagonal intralayer lens in plan view according to the fourteenth embodiment. FIG. 25 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state imaging element according to a fifteenth embodiment. FIG. 24 is a cross-sectional view illustrating a configuration of a pixel region of a solid-state imaging element according to a sixteenth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Photodiode, 3 Diffusion layer, 4 Gate electrode, 5 Contact hole, 6 Air gap, 7 Contact interlayer film, 8, 10 Metal wiring, 9 Via interlayer film, 11 Passivation film, 12 BPTEOS film, 13, 16 Oxide film, 14 grooves, 17 Antireflection film, AG1 to AG5, AG7 to AG15, AG1D, AG14D, AG61, AG62, AG71, AG72 Air gap, 22 Gate insulating film, 23 Microlens, 25 Color filter, 29 In layer Lens, 32 sidewalls, 33 element isolation film, 35 P ⁺ region, 36 N ⁻ region, 37 P ⁺⁺ region, 38 P well region, 40 photoresist, 41 interlayer film, 42 opening, 43, 44 groove, L1 Incident light, L2 stray light.

Claims (21)

A photodiode formed on a semiconductor substrate;
A first interlayer film formed on the semiconductor substrate so as to cover the photodiode;
A multilayer wiring formed in a second interlayer film formed above the first interlayer film;
A hollow portion formed in the first interlayer film between the lowermost layer wiring and the semiconductor substrate so as to surround a central portion of the photodiode in a plan view;
A solid-state imaging device comprising:   2. The solid-state imaging device according to claim 1, wherein an upper end of the hollow portion extends to a position higher than the wiring of the uppermost layer.   The upper end of the hollow portion is extended to a position lower than the wiring of the uppermost layer by an interval of 0.5 to 3 times the width of the hollow portion. The solid-state imaging device according to 1.   The solid-state imaging device according to claim 1, further comprising an insulating film formed immediately above the photodiode and having a higher refractive index than a silicon oxide film.   The solid-state imaging device according to claim 4, wherein a material of the insulating film is a silicon nitride film or a silicon oxynitride film.   The solid-state imaging device according to claim 4, wherein the hollow portion is formed above the insulating film, and a lower end thereof reaches the inside of the insulating film. The photodiode is
A first impurity region of a first conductivity type disposed in a surface layer portion of the semiconductor substrate;
A second impurity region of a second conductivity type disposed in a surface layer portion of the first impurity region;
With
The solid-state imaging device according to claim 1, wherein the hollow portion is disposed on the first impurity region.   The further hollow part formed in the said 2nd interlayer film so that the center part of the said photodiode might be enclosed by planar view, and further arrange | positioned on the said predetermined wiring is further provided. Solid-state image sensor. The hollow part is
A first hollow portion;
A second hollow portion disposed on the first hollow portion;
With
The solid-state imaging device according to claim 1, wherein a width of the second hollow portion is narrower than a width of the first hollow portion. A MOS transistor formed on the semiconductor substrate and disposed adjacent to the photodiode;
The solid-state imaging device according to claim 1, wherein the hollow portion includes a region disposed on a gate electrode of the MOS transistor. A passivation film formed so as to cover the wiring in the uppermost layer;
A color filter formed on the passivation film;
Another hollow portion formed in the color filter so as to surround the central portion of the photodiode in plan view, and disposed on the uppermost wiring;
The solid-state imaging device according to claim 1, further comprising:   The solid-state imaging device according to claim 1, wherein the hollow portion is a hollow portion formed in a self-aligning manner using the wiring as a mask. A MOS transistor formed on the semiconductor substrate and disposed adjacent to the photodiode;
The solid-state imaging device according to claim 1, wherein the hollow portion is not formed on the gate electrode of the MOS transistor in plan view.   2. The solid-state imaging device according to claim 1, wherein the shape of the hollow portion is a polygonal shape of a pentagon or more in plan view. A passivation film formed so as to cover the wiring in the uppermost layer;
On the passivation film, an in-layer lens formed of a material having a refractive index larger than that of the silicon oxide film,
Further comprising
2. The solid-state imaging device according to claim 1, wherein the height of the hollow portion is set to a height that does not block incident light collected by the in-layer lens.   The solid-state imaging device according to claim 15, wherein the shape of the hollow portion is similar to the shape of the intralayer lens in plan view. An element isolation film embedded in a groove formed in the semiconductor substrate so as to surround the photodiode in plan view;
Another hollow portion disposed in the element isolation membrane;
The solid-state imaging device according to claim 1, further comprising: A photodiode formed on a semiconductor substrate;
An element isolation film embedded in a groove formed in the semiconductor substrate so as to surround the photodiode in plan view;
A hollow portion disposed in the element isolation membrane;
A solid-state imaging device comprising: The photodiode is
A first impurity region of a first conductivity type disposed in a surface layer portion of the semiconductor substrate;
A second impurity region of a second conductivity type disposed in a surface layer portion of the first impurity region;
With
A third impurity region formed on a surface layer of the semiconductor substrate and having a higher concentration than the first impurity region;
The solid-state imaging device according to claim 18, wherein the third impurity region is disposed adjacent to the photodiode in a region surrounded by the element isolation film. A photodiode formed on a semiconductor substrate;
An interlayer film formed on the semiconductor substrate so as to cover the photodiode;
Multilayer wiring formed in the interlayer film;
A hollow portion formed in the interlayer film so as to surround the center portion of the photodiode in a plan view, and disposed on the predetermined wiring;
A solid-state imaging device comprising: A photodiode formed on a semiconductor substrate;
An interlayer film formed on the semiconductor substrate so as to cover the photodiode;
Multilayer wiring formed in the interlayer film;
A passivation film formed so as to cover the wiring in the uppermost layer;
A color filter formed on the passivation film;
A hollow portion formed in the color filter so as to surround a central portion of the photodiode in plan view, and disposed on the uppermost wiring;
A solid-state imaging device comprising:

Images