KR100938951B1 - Backside illuminated image sensor and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide a back-illuminated image sensor that emits light from the back surface of the wafer and a method of manufacturing the same. An alignment key formed to penetrate the interlayer insulating film and the first substrate to be spaced apart from the device, a wiring layer formed on the interlayer insulating film in multiple layers, and having a rear surface of a lowermost layer exposed, and a protective layer formed to cover the upper surface of the wiring layer; And a color filter and a micro lens formed on a rear surface of the first substrate so as to correspond to the light receiving element.

Image sensor, back-illumination image sensor, alignment key

Description

BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME}

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to an image sensor and a method for manufacturing the same, and more particularly to a backside illuminated image sensor and a method for manufacturing the same.

In general, a complementary metal oxide semiconductor (CMOS) image sensor has a peripheral area such as a light receiving element unit, a digital control block, an analog-to-digital converter, and the like in a limited area chip, so that the area ratio of the pixel array per chip area is high. It is limited to around 40%. In addition, the pixel size is reduced in order to achieve high quality, and thus, the amount of light that can be received by one light receiving element is reduced, resulting in various problems such as image loss due to increased noise.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and an object thereof is to provide a back-illuminated image sensor and a method of manufacturing the same that emit light from the back of the wafer.

According to an aspect of the present invention, there is provided a light receiving device formed in a first substrate, an interlayer insulating film formed to cover the light receiving device, and the interlayer insulating film and the first substrate spaced apart from the light receiving device. An alignment key formed through the layer, a wiring layer formed on the interlayer insulating layer in a multilayer manner, and a rear surface of the lowermost layer exposed; a protective layer formed to cover the upper surface of the wiring layer; and a rear surface of the first substrate so as to correspond to the light receiving element. Provided is a back side illuminated image sensor comprising a color filter and a micro lens formed thereon.

In addition, the present invention according to another aspect for achieving the above object, forming a light receiving element in the first substrate, forming an interlayer insulating film on the first substrate to cover the light receiving element, Forming a via hole by partially etching the interlayer insulating film and the first substrate, forming an alignment key to fill the via hole, forming a protective film to cover the wiring layer, and forming a second substrate on the protective film. Bonding, exposing a rear surface of the alignment key to a rear surface of the first substrate, etching the first substrate and the interlayer insulating layer to expose a rear surface of a lowermost layer of the wiring layer, and the light receiving device And forming a color filter and a micro lens on a rear surface of the first substrate so as to correspond to the first substrate. The.

According to the present invention having the configuration described above, the following effects can be obtained.

First, according to the present invention, by providing a back-illuminated image sensor that shines light from the back of the substrate (wafer) to minimize the loss of light incident to the light receiving element compared to the conventional CMOS image sensor (front-illuminated image sensor) The light receiving yield can be improved.

Second, according to the present invention, in the method of manufacturing a back-illuminated image sensor applying a back grinding process, a via-hole alignment key is formed in the substrate before the back grinding process of grinding the back surface of the substrate, and using the same. Therefore, the back grinding process can be easily controlled by controlling the back grinding target of the substrate during the back grinding process.

Third, according to the present invention, by etching the substrate in the rear direction to expose the bottom of the lowermost layer of the wiring layer formed on the upper surface of the substrate, and using the exposed back of the lower layer as a pad by wire bonding (wire bonding) through a subsequent process It is possible to place the pads on the back of the substrate rather than on the front, which allows for a variety of designs during the packaging process.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described in detail. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and when referred to as being on or above another layer or substrate, it is different. It may be formed directly on the layer or the substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process. In addition, the first and second conductivity types are p-type or n-type means different conductivity types.

Example

1 is a cross-sectional view illustrating a backside illumination image sensor according to an exemplary embodiment of the present invention. For convenience of explanation, only the photodiode and the gate electrode of the driving transistor are shown among the unit pixels of the CMOS image sensor.

As shown in FIG. 1, a backside illumination image sensor according to an embodiment of the present invention is a device wafer-a wafer on which a light receiving element such as a photodiode is formed, and a handle wafer 200-a digital block. And a wafer-bonded structure in which a peripheral circuit such as an analog digital converter is formed. Hereinafter, for convenience of description, the device wafer will be referred to as a first substrate, and the handle wafer will be referred to as a second substrate.

The back-illuminated image sensor according to the exemplary embodiment of the present invention includes an interlayer insulating layer formed to cover the first substrate 100C, a light receiving element formed in the first substrate 100C, for example, the photodiode 106 and the photodiode 106. 108B, an alignment key 112A formed through a pillar structure through the interlayer insulating film 108B and the first substrate 100C, and formed on the interlayer insulating film 108B in multiple layers, On the back surface of the first substrate 100C to correspond to the photodiode 106 and the wiring layers M1 to M4 formed to expose the back surface of the layer, the protective layer 124 formed to cover the wiring layers M1 to M4, and the photodiode 106. The formed color filter 126 and the micro lens 128 are included. In addition, the backside illumination image sensor according to the embodiment of the present invention further includes a second substrate 200 bonded to the protective layer 124.

112 A of aligning keys are formed in multiple numbers, and the upper surface is locally connected with the back surface of the lowest layer M1 among wiring layers M1-M4. The alignment key 112A may be formed of an insulating material, for example, an oxide film-based material or a nitride film-based material. In addition, the alignment keys 112A are formed in a circle (including ellipses) or polygons (triangles, squares, pentagons, etc.), and the number and size (width) thereof are not limited.

The first and second substrates 100C and 200 may use any one of a bulk substrate, an epitaxial substrate, and a silicon on insulator (SOI) substrate, respectively.

In addition, the back-illuminated image sensor according to the embodiment of the present invention further includes a plurality of transistors for transmitting and processing (amplifying) the optical signal focused on the photodiode 106. For example, the driving transistor among the plurality of transistors is formed in the gate electrode 104 formed between the first substrate 100C and the interlayer insulating film 108B, and in the first substrate 100C exposed to both sides of the gate electrode 104. Source and drain regions 107.

Hereinafter, a method of manufacturing a backside illuminated image sensor according to an exemplary embodiment of the present invention shown in FIG. 1 will be described.

2A to 2I are cross-sectional views illustrating a method of manufacturing a backside illuminated image sensor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, a semiconductor substrate, that is, a first substrate 100 is prepared. In this case, the first substrate 100 may use a bulk substrate, an epitaxial substrate, or an SOI substrate. In the drawings, an SOI substrate is used for convenience of description.

In addition, the first substrate 100 may be doped with a first conductivity type (p type) or a second conductivity type (n type) according to the design of the device. Here, what is doped with the first conductivity type will be described as an example.

Subsequently, an epitaxial layer (not shown) doped with a first conductivity type is formed on the first substrate 100 using the silicon growth method. In this case, the epi layer is doped at a lower concentration than the first substrate 100. For example, when the SOI substrate is used as the first substrate 100, the epitaxial layer may be a semiconductor layer formed on a buried oxide layer (BOX), or may be separately formed on the semiconductor layer. On the other hand, in the SOI substrate, the buried oxide layer BOX is formed to a thickness of 500-10000 kPa, and the semiconductor layer formed on the buried oxide layer BOX is formed to a thickness of about 1 ~ 10㎛.

Subsequently, a device isolation film 101 is locally formed in the first substrate 100. In this case, the device isolation layer 101 may be formed by a shallow trench isolation (STI) process or a LOCOS (LOCal Oxidation of Silicon) process. However, the device isolation layer 101 may be formed by an STI process that is advantageous for high integration, as shown in FIG. When the STI process is applied, it may be formed of a high density plasma (HDP) film having excellent embedding characteristics even at a high aspect ratio or a laminated film of an HDP film and a spin on dielectric (SOD) film.

Subsequently, the gate insulating layer 102 and the gate conductive layer 103 are formed on the first substrate 100 and then etched to form the gate electrode 104 of the driving transistor. At the same time, although not shown, the gate electrodes of the reset transistor, the transfer transistor, and the select transistor constituting the unit pixel of the CMOS image sensor are also formed.

Subsequently, spacers 105 are formed on both side walls of the gate electrode 104. In this case, the spacer 105 may be formed of an oxide film, a nitride film, or a laminated film in which they are stacked.

Meanwhile, a lightly doped drain (LDD) region (not shown) that is lightly doped with a second conductivity type may be formed in the first substrate 100 exposed to both sides of the gate electrode 104 before the spacer 105 is formed.

Subsequently, a lightly doped photodiode 106 of the second conductivity type is formed in the first substrate 100.

Subsequently, source and drain regions 107 heavily doped with a second conductivity type are formed in the first substrate 100 exposed to both sides of the spacer 105. In this case, the source and drain regions 107 are formed to have a higher doping concentration than the LDD region and the photodiode 106.

Subsequently, a doped region (not shown) doped with a first conductivity type may be further formed to cover the upper surface of the photodiode 106 to prevent surface noise of the photodiode 106.

Meanwhile, the method of sequentially forming the gate electrode 104, the spacer 105, the photodiode 106, the source and drain regions 107 has been described as an example, but the order in which they are formed is not limited. The order in which they are formed may vary depending on the design.

Next, an interlayer insulating film 108 is formed to cover the first substrate 100 including the gate electrode 104, the spacer 105, the photodiode 106, the source and drain regions 107. In this case, the interlayer insulating film 108 may be formed of an oxide film, for example, an oxide film containing silicon (SiO ₂ ), and more specifically, BoroPhosphoSilicate Glass (BPSG), PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), and USG (Un). It may be formed of any one selected from -doped Silicate Glass (TEOS), TEOS (Tetra Ethyle Ortho Silicate), HDP film or a laminated film thereof. In addition, it may be formed of a film coated by a spin coating method, such as a spin on dielectric (SOD) film.

Subsequently, as illustrated in FIG. 2B, an etching process is performed to locally etch the interlayer insulating layer 108A, thereby forming a contact hole 109 through which the source and drain regions 107 are exposed. In this case, the etching process may be either a dry etching or a wet etching process, but it is preferable to perform the dry etching process to form a vertical profile.

Subsequently, an etching process is performed to locally etch the interlayer insulating film 108A and the first substrate 100A, thereby forming a via hole 110 extending from the interlayer insulating film 108A to the first substrate 100A. In this case, the via holes 110 may be formed in plural as shown on the right side of the same drawing.

The via hole 110 has a circular structure, and preferably has a vertical profile. Specifically, the vertical profile angle is formed to be 88 ~ 90 °, the depth is formed to a depth of 20000 Å or less, preferably 4000 ~ 20000 으로 relative to the upper surface of the interlayer insulating film (108A). More specifically, it is formed to a depth of 1000 ~ 10000A relative to the upper surface of the first substrate (100A). The width (critical dimension, CD) is formed to be 1.6 µm or less, preferably 1.0 to 1.6 µm. In addition, the bottom width of the via hole 110 is formed to be 1.2 μm or less, preferably 1.0 to 1.4 μm. In addition, when the plurality of via holes 110 are implemented, it is preferable that the uniformity (angle, depth, or width) therebetween is 4% or less. In addition, the number and shape of the via holes 110 is not limited. In particular, the form can be implemented in various forms, for example, a circular or polygonal (triangle, square, pentagon, octagon, etc.) structure.

Meanwhile, the process of forming the contact hole 109 and the via hole 110 may be performed in-situ using the same etching equipment. At this time, the etching equipment uses a plasma etch (plasma etch) equipment. In addition, in the forming order, the via hole 110 may be formed first, and then the contact hole 109 may be formed.

Specifically, the etching process for forming the via hole 110 is performed in two steps using a dry etching process.

First, the first step is to etch the interlayer insulating film 108A. The etching rate (selection ratio) of the interlayer insulating film 108A to the photosensitive film pattern (not shown) is 5: 1 to 2: 1 (interlayer insulating film: photosensitive film pattern). ), Preferably 2.4: 1 (interlayer insulating film: photosensitive film pattern). In addition, the etching amount is performed to be 7000 to 8000 Å / min, preferably 7200 Å / min. For example, as an etching condition, a pressure of 100 to 200 mTorr and a source power of 100 to 2000 W are used, and a fluorocarbon compound such as CHF ₃ or CF ₄ is used as a source gas to improve etching speed and anisotropy. Ar is further added to the source gas to be used. At this time, the flow rate of CHF ₃ is set to 5 to 200 sccm, the flow rate of CF ₄ is set to 20 to 200 sccm, and the flow rate of Ar is set to 100 to 2000 sccm.

In the second step, the semiconductor substrate 100A is etched so that the etching amount is 1000 to 3000 m 3 / min, preferably 2000 m 2 / min. For example, as an etching condition, a pressure of 15 to 30 mTorr, a source power (RF power) of 400 to 600 W, a bias power of 80 to 120 W, and a power to improve ion straightness are used. SF ₆ and O ₂ are used. At this time, the flow rate of SF ₆ is 5 ~ 200sccm, the flow rate of O ₂ is 1 ~ 100sccm.

Meanwhile, the via hole 110 may be partially etched into the buried oxide layer (BOX) by over-etching the buried oxide layer (BOX) to a depth of 100 to 4000Å, or the buried oxide layer (BOX) may be completely as shown in FIG. It may be formed to penetrate.

In addition, in the case of the SOI substrate, the etching is stopped by using the buried oxide layer as an etch stop layer.

Subsequently, as shown in FIG. 2C, the conductive material is embedded to fill the contact hole 109 (see FIG. 2B) to form the contact plug 111. In this case, the conductive material may be a polycrystalline silicon film doped with impurity ions, copper (Cu), platinum (Pt), tungsten (W), aluminum (Al) or an alloy film containing these materials. However, the conductive material is not limited to these materials, and any metal or alloy film having conductivity may be used. For example, when tungsten is used as the conductive material, it is formed by CVD (Chemical Vapor Deposition) process or ALD process, and when aluminum is used, it is formed by CVD process. In addition, when copper is used, it is formed by an electroplating method or a CVD process.

Subsequently, an insulating material 112 is formed on the entire surface including the interlayer insulating layer 108A so as to fill the via hole 110 (see FIG. 2B). In this case, the insulating material 112 may be formed of a heterogeneous material having excellent embedding characteristics and having an interlayer insulating film 108A and a high etching selectivity (or polishing selectivity). For example, the insulating material 112 is formed of an oxide film-based material or a nitride film-based material. Specifically, the oxide-based material may be formed of a silicon oxide film, more specifically, a film selected from any one of BPSG, BSG, USG, TEOS, and HDP film, or a laminated film thereof. In addition, the nitride film-based material may be formed of a silicon nitride film. In addition, it may be formed of a film coated by a spin coating method such as a spin on dielectric (SOD) film having excellent coating properties.

Next, as illustrated in FIG. 2D, a planarization process is performed to form an alignment key 112A having an isolated pillar structure inside the via hole 110 (see FIG. 2B). In this case, the planarization process may include an etch back process or a chemical mechanical polishing (CMP) process. In addition, during the planarization process, the interlayer insulating film 108A is used as an etch stop film or a polishing stop film.

Subsequently, as shown in FIG. 2E, a plurality of metal wiring layers 113, 116, 119, and 122, contact plugs 115, 118, and 121, and an interlayer insulating layer 114, 117, and 120 are formed by performing a wiring process. , 123). For example, some of the plurality of wiring layers 113 are electrically separated from each other and connected to the contact plug 111, and some are supported by the alignment keys 112A.

The wiring layers 113, 116, 119, and 122 are formed through a deposition process and an etching process, and are formed of a conductive material such as a metal or an alloy film in which at least two kinds of metals are mixed. It is preferably formed of aluminum. The contact plugs 115, 118, and 121 are formed through damascene processes in the interlayer insulating layers 114, 117, 120, and 123, respectively, and the wiring layers 113, 116, 119, and 122 stacked up and down are formed. It is formed by any one selected from a conductive material such as a polycrystalline silicon film doped with impurity ions, a metal, or an alloy film containing at least two kinds of metals for electrical connection. It is preferably formed of tungsten. The interlayer insulating films 114, 117, 120, and 123 are formed of any one oxide film selected from BPSG, PSG, BSG, USG, TEOS, and HDP films, or a laminated film in which two or more layers are laminated. In addition, the interlayer insulating layers 114, 117, and 120 may be planarized through a CMP process after deposition.

Meanwhile, the present invention is not limited to the structures of the metal wires 113, 116, 119, and 122 and the contact plugs 115, 118, and 121 shown in FIG. 2E, and may be applied to various structures.

Subsequently, a passivation layer 124 is formed on the uppermost interlayer insulating layer 123. In this case, the protective layer 124 may be formed of a film selected from among BPSG, PSG, BSG, USG, TEOS, or HDP. Preferably, the film is formed to a thickness of 1000 to 40000 kV using a TEOS film or an HDP film. The protective layer 124 may be formed of a nitride film or a laminated film of an oxide film and a nitride film.

Next, the protective layer 124 is planarized. At this time, the planarization process may be performed by a CMP process.

Subsequently, a heat treatment process can be performed to achieve densification of the protective layer 124. In this case, the heat treatment process may be performed by an annealing process using a furnace (furnace) equipment.

Subsequently, as illustrated in FIG. 2F, the first substrate 100A and the second substrate 200 manufactured through the processes of FIGS. 2A to 2E are bonded. In this case, the bonding process may use any one method selected from among oxide film-oxide film bonding, oxide film-silicon bonding, oxide film-metal film bonding, oxide film-bonding member-oxide film bonding or oxide film-bonding member-silicon bonding.

For example, the oxide film-oxide film (formed on the second substrate 200) junction and the oxide film-silicon (silicon substrate) junction are both plasma treatment—O ₂ or N ₂ use—and water treatment. ) And then join. Moreover, in addition to the method of joining after water treatment, the application of the method of joining after chemical processing, such as an amine, is also possible. In the oxide film-metal film (formed on the second substrate 200), a metal such as titanium (Ti), aluminum (Al), copper (Cu), or the like may be used as the metal film. In the oxide film-adhesive member-oxide film bonding and the oxide film-adhesive member-silicon bonding method, BCB (Benzo Cyclo Butene) may be used as the adhesive member.

Subsequently, as shown in FIG. 2G, a back grinding process is performed to grind the back surface of the first substrate 100B. In this case, when the alignment key 112A is formed to penetrate the investment oxide layer BOX, the back grinding process is performed until the investment oxide layer BOX is exposed to expose the alignment key 112A. In this process, the buried oxide layer BOX may be partially ground. On the other hand, when the alignment key 112A is formed in a structure that does not penetrate the buried oxide layer BOX—the structure extended to a predetermined depth of the buried oxide layer BOX—the buried oxide layer BOX is also exposed so that the alignment key 112A is exposed. A part or all of the buried oxide layer BOX may be etched by grinding or removing it, or by performing a separate etching process.

Subsequently, as illustrated in FIG. 2H, the buried oxide layer BOX, the first substrate 100C, and the interlayer insulating layer 108B are locally etched from the rear surface of the first substrate 100C to form the rear surface of the lowermost wiring layer 113. Local exposure. As a result, the lowermost wiring layer 113 exposed serves as a pad and is wire bonded through a subsequent process.

Meanwhile, after exposing the back surface of the wiring layer 113, a separate pad conductive material may be formed on the back surface of the wiring layer 113. In this case, the conductive material may be formed of a metal or a mixed film in which at least two kinds of metals are mixed. It is preferably formed of aluminum.

Subsequently, as shown in FIG. 2I, a protective layer 125 is formed on the rear surface of the buried oxide layer BOX.

Subsequently, the color filter 126 is formed on the passivation layer 125 corresponding to the photodiode 106.

Meanwhile, the lower planarization layer may be formed on the protective layer 125 before the color filter 126 is formed.

Next, the upper planarization film 127 is formed to cover the color filter 126.

Subsequently, the microlens 128 is formed on the upper planarization layer 127 to correspond to the color filter 126.

Subsequently, a low temperature oxide layer 129 is formed on the passivation layer 125 including the microlens 128.

Subsequently, a packaging process is performed to package the first substrate 100C and the second substrate 200. At this time, the packaging process includes a wire bonding process and a sawing process. Here, the wire bonding is made by connecting the pad (wiring layer 113) and the external chip with a wire.

As described above, although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, although the embodiment of the present invention has been described as an example of the CMOS image sensor, it can be applied to both the image sensor and the integrated device of the 3D structure using the back irradiation method. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a cross-sectional view of a backside illuminated image sensor in accordance with an embodiment of the present invention.

2A to 2I are cross-sectional views illustrating a method of manufacturing a backside illuminated image sensor according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 100A, 100B, 100C: first substrate (element wafer)

101: device separator

102: gate insulating film

103: gate conductive film

104: gate electrode

105: spacer

106: photodiode

107: source and drain regions

108, 108A, 108B, 114, 117, 120, 123: interlayer insulating film

109: contact hole

110: via hole

111, 115, 118, 121: contact plug

112: insulation material

112A: Sort Key

113, 116, 119, 122: wiring layer

124, 125: protective layer

126: color filter

127: planarization film

128: Micro Lens

129: low temperature oxide film

200: second substrate (handle wafer)

Claims (24)

A light receiving element formed in the first substrate; An interlayer insulating film formed to cover the light receiving element; An alignment key spaced apart from the light receiving element and formed through the interlayer insulating layer and the first substrate; A plurality of wiring layers formed on the interlayer insulating film, the back surface of the lowermost layer of the wiring layers being exposed; A protective layer formed to cover upper surfaces of the wiring layers; And The color filter and the micro lens formed on the rear surface of the first substrate so as to correspond to the light receiving element Wherein the alignment key is used as a grinding target upon back grinding of the back side of the first substrate. The method of claim 1, A top surface of the alignment key is locally connected with a rear surface of the bottom layer of the wiring layers. The method of claim 1, And the alignment key comprises an insulating material. The method of claim 3, wherein The insulating material is an oxide-based material or nitride-based material, back-illuminated image sensor. The method of claim 1, And the alignment keys are provided in plurality. The method of claim 1, And the alignment key is formed in a pillar structure. The method of claim 1, And a second substrate bonded to the protective layer. The method of claim 1, And the first substrate uses any one selected from the group consisting of a bulk substrate, an epitaxial substrate, or a silicon on insulator (SOI) substrate. The method of claim 1, And the alignment key is formed through the buried oxide layer of the first substrate. The method of claim 9, The buried oxide layer is formed to a thickness of 500 ~ 10000Å, back irradiation image sensor. The method of claim 1, A gate electrode formed on the first substrate; And Source and drain regions spaced apart from the light receiving element and exposed to both sides of the gate electrode and formed in the first substrate Rear irradiation image sensor further including. The method of claim 1, A backside of the bottom layer of the wiring layers is wire bonded. Forming a light receiving element in a first substrate, wherein a buried oxide layer is formed on the first substrate; Forming an interlayer insulating film on the first substrate to cover the light receiving element; Partially etching the interlayer insulating layer and the first substrate to form via holes; Forming an alignment key to bury the via hole; Forming a plurality of wiring layers on the first substrate including the alignment key; Forming a protective layer to cover the wiring layers; Bonding a second substrate to the protective layer; Exposing a back side of the alignment key to a back side of the first substrate; Exposing a bottom surface of a lowermost layer of the wiring layers by etching the first substrate and the interlayer insulating layer; And Forming a color filter and a micro lens on a rear surface of the first substrate so as to correspond to the light receiving element The method may further include exposing a rear surface of the alignment key. Back grinding the back surface of the first substrate; And Etching the buried oxide layer of the first substrate so that the back side of the alignment key is exposed Including, the manufacturing method of the back irradiation image sensor. The method of claim 13, And an upper surface of the alignment key is locally connected to a rear surface of the lowermost layer of the wiring layers. The method of claim 13, And the alignment key comprises an insulating material. The method of claim 15, The insulating material is an oxide film-based material or nitride film-based material, manufacturing method of the back-illuminated image sensor. The method of claim 13, And a plurality of alignment keys are provided. The method of claim 13, And the alignment key is formed in a pillar structure. The method of claim 13, And the first substrate is any one selected from the group consisting of a bulk substrate, an epitaxial substrate, or a silicon on insulator (SOI) substrate. The method of claim 13, When the first substrate is used as a silicon on insulator (SOI) substrate, the via hole penetrates the buried oxide layer of the SOI substrate. The method of claim 13, When using the first substrate as a silicon on insulator (SOI) substrate, the via hole extends locally to the buried oxide layer of the SOI substrate. delete The method of claim 13, After forming the color filter and the micro lens, And packaging the first and second substrates. The method of claim 23, And the packaging step includes wire bonding on the back side of the bottom layer of the wiring layers.

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