JP2001265286A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly definite and compact liquid crystal display device by reducing the occupancy area of D/A converters on a substrate in liquid crystal display device which driving circuits are integrally formed on a glass substrate. SOLUTION: In this display device, D/A converters 132 having smaller numbers of gradation than those of conventional practice are made to be used by providing a signal processing circuit 140 which converts the low-definition and high-gradation signal outputted from an external driving circuit 150 into a high-definition and low-gradation signal to supply it to a signal line driver 130 between the external driving circuit 150 and the signal line driver 130 to reduce the occupancy area of the D/A converters on the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a high definition display screen, and more particularly to a liquid crystal display device having a function of converting a low definition, high gradation signal into a high definition, low gradation signal. About.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have become widespread in various fields mainly for displays of office automation equipment, taking advantage of the characteristics of light weight, thinness, and low power consumption. In particular, an active matrix type liquid crystal display device that has a switch element for each pixel can minimize crosstalk between adjacent pixels, so high-definition displays such as personal computer displays and large color liquid crystal panels It is often used in fields that require a stable display image.

At present, the resolution of a liquid crystal display device is 12.1 which is the highest definition among the mainstream large-sized panels.
Even a panel conforming to the inch XGA standard (1024 × 768 pixels) is about 106 dpi (dot per inch). On the other hand, printed matter generally has a resolution of 300 to 400 dpi, and it can be said that the resolution is insufficient even with a high-definition panel in order to use the liquid crystal display device instead of the printed matter. In recent years, by using a low-temperature p-si (polysilicon) technology, an analog sample-and-hold type driving circuit is integrally formed on a glass substrate, thereby achieving up to 200 ppi (pixel).
per inch) panel can be realized.

[0004]

A D / A converter for converting a digital video signal (gradation signal) sampled by the driving circuit into an analog video signal is provided on a printed wiring board outside a glass substrate. Since they are separately formed, they increase the mounting space and increase the cost. This problem can be solved by integrally forming the D / A converter on the glass substrate like the drive circuit. However, a multi-level D of about 256 levels
Since the A / A converter occupies a large area of the circuit, it is necessary to integrally form the A / A converter on a glass substrate constituting a high-definition panel.
A wide frame is required, and it is difficult to realize a compact liquid crystal display device.

It is an object of the present invention to provide a high-definition and compact liquid crystal display device by reducing the area occupied by a circuit by a D / A converter.

[0006]

In order to achieve the above object, according to the first aspect of the present invention, a plurality of scanning lines and a plurality of signal lines intersecting with each other are arranged at each intersection of these scanning lines and signal lines. A first electrode integrally formed with a plurality of switch elements, a plurality of pixel electrodes connected to the signal line via the switch elements, and a drive circuit for writing a gradation signal input from the outside to the pixel electrodes; A substrate, a second electrode substrate on which a counter electrode facing the pixel electrode is formed,
In a liquid crystal display device having a liquid crystal layer interposed between these substrates, a signal processing circuit for converting a low-definition, high-gradation signal input from the outside into a high-definition, low-gradation signal and supplying the same to the driving circuit Is provided.

According to a second aspect of the present invention, in the first aspect, the signal processing circuit is formed integrally with the drive circuit on the first electrode substrate.

According to a third aspect of the present invention, when the high-level signal is an i-bit signal and the low-level signal is a j-bit signal, the signal processing circuit converts the gray-scale signal. It is characterized in that display of i-bit gradation is performed by j-bit gradation pixels.

According to a fourth aspect of the present invention, in the first and second aspects, the signal processing circuit corresponds to a gray level of a high gray scale signal corresponding to one pixel of low definition to the one pixel of low definition. Means for dividing by the number of high-definition low-tone pixels, and calculating the quotient as an approximate value for dispersing the high-tone signal to low-tone pixels; Means for arranging one or a plurality of low gradation pixels in accordance with an area gradation algorithm.

According to a preferred aspect of the present invention, each means constituting the signal processing circuit is realized by a combination circuit including, for example, a division circuit, an encoder circuit, and an addition circuit. Alternatively, the arithmetic processing circuit such as a CPU and a program describing the processing procedure of each unit described above are used, and the CPU is controlled according to the program to execute the arithmetic processing.

Further, the invention of claim 5 is characterized in that, in claim 4, the area gradation algorithm is a Bayer type dither matrix.

In a preferred embodiment of the present invention, the area gradation algorithm is an error dispersion type dither matrix.

According to the liquid crystal display device having the above-described structure, the display is performed by the high-definition and low-gradation signals converted by the signal processing circuit, so that a D / A converter having a smaller number of gradations than usual is used. This makes it possible to reduce the area occupied by the D / A converter on the substrate. In this case, although the gradation information on the screen is reduced,
The human eye is less sensitive to contrast for patterns that change at a fine pitch, such as a high-definition display. Image quality comparable to the case of using a D / A converter having.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a liquid crystal display device integrated with a driving circuit according to this embodiment. Also, FIG.
FIG. 2 is a partial cross-sectional view of a display pixel unit 110 shown in FIG.

The liquid crystal display device 100 includes a display pixel section 110 in which a plurality of display pixels 10 are formed, a scanning line driver 120, a signal line driver 130, and a signal processing circuit 14.
0.

Among them, the scanning line driver 120, the signal line driver 130, and the signal processing circuit 140 are formed integrally with the signal lines 11, the scanning lines 12, the pixel electrodes 14, and the like, which will be described later, on the array substrate 101.

In the display pixel section 110, a plurality of signal lines 11 and a plurality of scanning lines 12 intersecting the signal lines 11 are arranged in a matrix on an array substrate 101, and a switching element is provided at each intersection of both lines. TFT 13 is provided. The signal lines 11 and the scanning lines 12 are electrically insulated by an insulating film (not shown).

The TFT 13 has a source electrode connected to the signal line 11 and a drain electrode connected to the pixel electrode 14. Counter electrode 1 arranged opposite to this pixel electrode 14
5 is formed on the counter substrate 102 as shown in FIG. A liquid crystal layer 16 is provided between the pixel electrode 14 and the counter electrode 15.
Are sandwiched to form a liquid crystal capacitance (Clc). Further, an auxiliary capacitor 17 is connected to the pixel electrode 14 in parallel to maintain a potential relationship with the counter electrode 15. The auxiliary capacitance 17 forms a capacitance (Cs) between the pixel electrode 14 and an auxiliary capacitance line (not shown).

The common electrode 15 is supplied with a constant common voltage from the external drive circuit 150. A video signal (gradation signal) written from a signal line driver 130 to be described later through the signal line 11 is held for one frame scanning period by the liquid crystal capacitance Clc and the capacitance Cs.

The scanning line driver 120 includes a shift register 121 and a buffer circuit 122.
A scanning signal is sequentially output to each scanning line 12 based on a vertical clock / start signal supplied from the external driving circuit 150.

The signal line driver 130 includes a shift register 131, a D / A converter 132, and a video bus wiring (not shown). Shift register 131
Samples the video signal on the signal line 11 at a predetermined timing based on a horizontal clock / start signal supplied together with the video signal from the external drive circuit 150.

The signal processing circuit 140 includes the external drive circuit 15
The low-definition, high-gradation signal input from 0 is converted into a high-definition, low-gradation signal and supplied to the signal line driver 130.

In order to realize such conversion of the gradation signal, the signal processing circuit 140 is provided with a gradation level (hereinafter referred to as gradation) of a high gradation signal corresponding to one pixel of low definition input from the external driving circuit 150. Information) is divided by the number of high-definition low-gradation pixels corresponding to one low-definition pixel, and the quotient is calculated as an approximation for dispersing the high-gradation signal to the low-gradation pixels. A circuit 141 and, when a remainder is generated by the division, a remainder arrangement circuit 1 for arranging the remainder in one or a plurality of low gradation pixels according to an area gradation algorithm.
42. These circuits 141 and 14
2 can be realized by a combination circuit including, for example, a division circuit, an encoder circuit, and an addition circuit.

The external drive circuit 150 is composed of a control IC (not shown) or the like, and converts and processes a reference clock signal, a digital video signal, and the like supplied from an external device as appropriate, and scans the scanning line driver 120 and a signal processing circuit. 140 and the like. The external drive circuit 150 and the liquid crystal display device 100 are electrically connected by an unillustrated FPC (flexible wiring board).

Next, the conversion processing of the gradation signal in the signal processing circuit 140 will be described.

Here, low-definition, high-gradation signals are converted to high-definition,
As an example of conversion into a low gray scale signal, a high gray scale signal of 0 to 255 gray scales as shown in FIG.
Is converted into a low gradation signal of 0 to 15 gradations (hereinafter, a 4-bit gradation signal). Note that one pixel of the 8-bit gray scale signal corresponds to 16 pixels of the 4-bit gray scale signal (4 × 4 matrix arrangement).

First, the gradation information of the 8-bit gradation signal input from the external drive circuit 150 to the signal processing circuit 140 is as follows:
The division is performed by the approximate value calculation circuit 141. Here, in order to convert the 8-bit gradation signal into 16 4-bit gradation signals,
The gradation information is divided by 16. As a result of this division, a quotient and / or remainder is output. The quotient obtained here is an approximate value for dispersing the 8-bit grayscale signal to 16 pixels. Therefore, the quotient is spread over 16 pixels. For example, looking at the gradation information 16 in FIG.
Since 6 = 1 (quotient), 1 is distributed to 16 pixels. If there is a remainder, the extra arrangement circuit 142 arranges one or a plurality of pixels in accordance with a Bayer-type dither matrix which is an area gradation algorithm.

FIG. 4 is an explanatory diagram of a 4 × 4 Bayer type dither matrix. This dither matrix is a table indicating the order for randomly arranging the output gradation information on 16 pixels.
Are arranged according to a predetermined rule.

As an algorithm for area gradation, this B
In addition to the aerer type dither matrix, there is an error dispersion type dither matrix.

The remainder output by the division by the approximate value calculation circuit 141 is arranged according to the matrix shown in FIG. For example, looking at the gradation information 17 in FIG. 3, the remainder 1 is arranged at a position corresponding to “0” in FIG. Looking at the gradation information 19, the remainder 3 is “0”, “1”, “2” in FIG.
, And the gradation information of the three pixels is 2.

As shown in FIG. 3, the 8-bit gray scale signal is
When converted to a bit gradation signal, there is a concern that image quality may be degraded because gradation information is reduced. However, 200
In a high-definition display of about ppi or more, when a viewer sees from a normal viewing distance, the pixel pitch is limited to the resolution of the eye (viewing angle: about 1 minute, pixel pitch: 12 from 45 cm distance).
However, it is clear that the human eye is less sensitive to contrast for a pattern that changes at such a fine pitch (corresponding to viewing a display of 7 μm (200 ppi)). Big head: Applied physics, p128-p138 (1977) etc.). That is, in a high-definition display, a high-gradation signal is not necessarily required, and the number of gradations can be reduced within a range where deterioration of image quality is not recognized.

In this embodiment, the pixel pitch is set to 200 ppi in order to realize a resolution comparable to a printed matter. In order to perform color display, a three-color stripe array, that is, a color filter having a stripe shape of a different color for each signal line in the order of R, G, and B is used, and one pixel is formed at three signal line pitches. Therefore, the signal line interval is as narrow as 42 μm. For this reason, it is difficult to fit a 6 to 8 bit gray scale D / A converter used in a general liquid crystal display device in a frame width of about 5 mm, and a wide frame width is required. On the other hand, in the case of this embodiment,
Since a D / A converter (132) having a 4-bit gradation can be used, the frame width can be reduced to a narrow frame width of about 5 mm, and a compact liquid crystal display device can be realized. In addition, even when the image is displayed on a 200 ppi high-definition display, D / A of 8 bit gradation is applied to all signal lines.
Image quality comparable to that obtained when a converter is connected can be obtained.

As described above, the quotient obtained by the division is 16
By dispersing the pixels, it is possible not only to secure a necessary gradation (a 4-bit gradation in this example) in high-definition details on the screen, but also to arrange the remainder of the division according to the dither matrix. High gradation display can be performed even in a portion having a low spatial frequency.

Next, an embodiment will be described in which the conversion processing of the gradation signal by the signal processing circuit 140 is realized using an arithmetic processing circuit such as a CPU and a program.

FIG. 5 is a flowchart showing the procedure of the gradation signal conversion processing by the signal processing circuit 140. In the signal processing circuit 140, the CPU is controlled according to a program describing this flowchart.

First, the gradation information X of the 8-bit gradation signal input from the external drive circuit 150 is divided by 16 (step 101). Here, the quotient: A and the remainder: B are output.
Subsequently, the quotient A is divided into 16 pixels (step 1).
02), it is determined whether the remainder B is at least 1 or more (step 103). If yes, the remaining B is Bay
(Step 1)
04) 4-bit data of a 4 × 4 matrix arrangement is output to the shift register 131 (step 105). If No in step 103, the process proceeds to step 105, and outputs the 4-bit data of the 4 × 4 matrix array obtained in step 102 to the shift register 131.
Such a gradation signal conversion process is sequentially performed on the inputted gradation signal.

Next, the liquid crystal display device 1 according to this embodiment will be described.
00 will be described with reference to FIG. FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the liquid crystal display device. The area on the right side of the broken line shows the pixel portion (display pixel section 110), and the area on the left side shows the drive circuit section (scanning line driver 120 and the like). . Hereinafter, description will be made in the order of (a) to (f) of FIG.

(A) An amorphous silicon (a-Si) thin film 51 having a thickness of 50 nm is deposited on a transparent insulating substrate 50 such as glass by a plasma CVD method, and the amorphous silicon thin film 51 is annealed by a XeCl excimer laser device. This causes polycrystallization. Here, the Xe
The laser light 52 from the Cl excimer laser device
And the region irradiated with the laser light 52 is crystallized to form a polycrystalline silicon film 53. At this time, by performing laser irradiation more than once while increasing the laser irradiation energy stepwise, hydrogen in the amorphous silicon film can be effectively removed, and ablation during crystallization can be prevented. The irradiation energy is 200 to 500 m
J / cm ² .

(B) The polycrystalline silicon film 53 is patterned by photolithography to form an active layer 54 of the thin film transistor.

(C) After a gate insulating film 55 of a silicon oxide film is formed by a plasma CVD method, a molybdenum-tungsten alloy film is formed by a sputtering method and patterned to form a gate electrode 56. Scanning lines are also formed at the same time as the patterning. Gate insulating film 55
Alternatively, a silicon nitride film or a silicon oxide film formed by a normal pressure CVD method can be used.

After forming the gate electrode 56, the gate electrode 5
Impurities are implanted by ion doping using the mask 6 as a mask to form source / drain regions 54a of the thin film transistor. As impurities, phosphorus can be used for an N-ch transistor and boron can be used for a P-ch transistor. For the transistor in the pixel portion, LDD (Light
It is effective to use a (Tly DopedDrain) structure. In this case, after the impurity is implanted into the source / drain electrodes 54a, the gate electrode 56 is re-patterned to make it smaller by a certain amount, and then the low concentration impurity is implanted again.

(D) Plasma CVD on the gate electrode 56
A first interlayer insulating film 57 of a silicon oxide film is formed by a CVD method or a normal pressure CVD method.

(E) After forming contact holes in the first interlayer insulating film 57 and the gate insulating film 55, the contact holes are formed by sputtering.
Source / drain electrodes 59 and 60 are formed by forming and patterning an l film. At this time, signal lines are formed at the same time.

(F) A low dielectric constant insulating film (second interlayer insulating film) 61 is formed on the Al film. Low dielectric constant insulating film 61
May be a silicon nitride film formed by a plasma CVD method, or a multilayer film of a low dielectric constant insulating film such as a silicon nitride film and a silicon oxide film. Then, the low dielectric constant insulating film 6
1 is formed with a contact hole, and ITO (Indium) is formed.
A pixel electrode is formed by forming and patterning a (Tin Oxide) film 62.

By the above process, the transparent insulating substrate 50
A pixel portion and a driver circuit portion can be formed over the same. Thereafter, the transparent insulating substrate 50 and the opposing substrate on which the opposing electrode (not shown) is formed are opposed to each other, the periphery thereof is sealed with a sealing material made of epoxy resin, and a liquid crystal composition is injected therein.
The liquid crystal display device can be completed by sealing (see FIG. 2).

Note that a p-Si (polysilicon) TFT
Since the mobility of electrons is about two orders of magnitude higher than that of an a-Si TFT, the TFT size can be reduced,
The peripheral driving circuit can also be integrally formed on the substrate at the same time. It is desirable that the peripheral circuit has a CMOS structure in order to achieve high speed and low power consumption. For this reason, the impurity doping step is performed in two steps of P-type and N-type impurity doping steps using a resist mask.

[0048]

As described above, in the liquid crystal display device according to the present invention, low-definition signals input from the outside can be used.
Since the high gradation signal is converted into a high definition and low gradation signal for display, it is possible to use a D / A converter having a smaller number of gradations than usual, and the area occupied by the D / A converter on the substrate Can be reduced. In addition, even in a high-definition display, an image quality comparable to that obtained by using a D / A converter having a normal number of gradations can be obtained, so that a high-definition and compact liquid crystal display device can be provided. .

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a drive circuit integrated type liquid crystal display device according to an embodiment.

FIG. 2 is a partial cross-sectional view of the display pixel portion shown in FIG.

FIG. 3 is an explanatory diagram when an 8-bit gradation signal is converted into a 4-bit gradation signal.

FIG. 4 is an explanatory diagram of a 4 × 4 Bayer-type dither matrix.

FIG. 5 is a flowchart illustrating a procedure of a gradation signal conversion process performed by the signal processing circuit.

FIG. 6 is a schematic sectional view showing a manufacturing process of the liquid crystal display device.

[Explanation of symbols]

100: liquid crystal display device, 101: array substrate, 102:
Counter substrate 110: display pixel portion, 120: scanning line driver, 130
... Signal line driver 132 ... D / A converter, 140 ... Signal processing circuit, 141 ... Approximation value calculation circuit, 142 ... Remaining circuit, 150
... External drive circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) G09G 3/20 641 G09G 3/20 641P 641H 650 650C H04N 5/66 102 H04N 5/66 102B F term (reference) 2H093 NA54 NC24 ND06 ND17 ND43 5C006 AA13 AC21 AF47 AF82 BB16 BC16 BF03 FA43 5C058 AA06 BA08 BA25 BB05 5C080 AA10 BB05 DD22 EE29 FF11 GG09 GG12 JJ01 JJ02 JJ06 JJ07 EE30 BB30 AA18

Claims (5)

[Claims] A plurality of scanning lines and a plurality of signal lines intersecting with each other, a plurality of switching elements disposed at each intersection of the scanning lines and the signal lines, and a plurality of switching elements connected to the signal lines via the switching elements. A first electrode substrate integrally formed with a plurality of pixel electrodes and a driving circuit for writing a grayscale signal input from the outside to the pixel electrodes; and a second electrode formed with a counter electrode facing the pixel electrodes. In a liquid crystal display device including an electrode substrate and a liquid crystal layer interposed between these substrates, a low definition, high gradation signal input from the outside is converted into a high definition, low gradation signal and supplied to the drive circuit. A liquid crystal display device provided with a signal processing circuit that performs the following. 2. The liquid crystal display device according to claim 1, wherein the signal processing circuit is formed integrally with the drive circuit on the first electrode substrate. 3. The display according to claim 1, wherein when the high gradation signal is an i-bit signal and the low gradation signal is a j-bit signal, an i-bit gradation is displayed by a j-bit gradation pixel. 3. The liquid crystal display device according to 1. 4. The signal processing circuit divides a gradation level of a high gradation signal corresponding to one pixel of low definition by the number of high definition low gradation pixels corresponding to the one pixel of low definition. Means for calculating the quotient as an approximation for dispersing the high gradation signal to the low gradation pixels, and, when there is a remainder due to the division, dividing the remainder with respect to one or more low gradation pixels by area gradation 3. The liquid crystal display device according to claim 1, further comprising means for arranging according to the following algorithm. 5. The area gray scale algorithm is Bay
The liquid crystal display device according to claim 4, wherein the liquid crystal display device is an er type dither matrix.