JP2001257158A - Electron beam lithography system - Google Patents

Electron beam lithography system

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Publication number
JP2001257158A
JP2001257158A JP2000072457A JP2000072457A JP2001257158A JP 2001257158 A JP2001257158 A JP 2001257158A JP 2000072457 A JP2000072457 A JP 2000072457A JP 2000072457 A JP2000072457 A JP 2000072457A JP 2001257158 A JP2001257158 A JP 2001257158A
Authority
JP
Japan
Prior art keywords
electron beam
wafer
beam lithography
electrode
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000072457A
Other languages
Japanese (ja)
Inventor
Masaru Matsushima
勝 松島
Yoshimasa Fukushima
芳雅 福嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000072457A priority Critical patent/JP2001257158A/en
Publication of JP2001257158A publication Critical patent/JP2001257158A/en
Pending legal-status Critical Current

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable electron beam lithography system which suppresses wafer potential regardless of the grounded state of the wafer when the system electrostatically attracts the wafer. SOLUTION: The electrode in an electrostatic chuck 9 is divided into two electrodes (10a and 10b) which are respectively connected to DC power sources 16a and 16b having different polarities. The wafer 14 is grounded by pressing an earth pin 12 against the wafer 14 and made to be electrostatically attracted to the surface of the chuck 9. Since the current flowing to the pin 12 can be reduced, the rise of the wafer potential can be suppressed even when the wafer 14 is defectively grounded. Consequently, the current flowing to the pin 12 can be reduced and, accordingly, the rise of the wafer potential can be suppressed and highly reliable electron beam lithography becomes possible.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体製造分野に
おいて使用される電子線描画装置の改良に係り、特に静
電吸着機構(以下、静電チャックと記す)によって半導
体基板を吸着保持しながら描画を行なう電子線描画装置
の改良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an electron beam lithography apparatus used in the field of semiconductor manufacturing, and more particularly to drawing while holding a semiconductor substrate by means of an electrostatic chuck mechanism (hereinafter referred to as an electrostatic chuck). The present invention relates to an improvement in an electron beam lithography apparatus that performs the following.

【0002】[0002]

【従来の技術】半導体基板上にLSIのパタンを形成す
る主要な工程の一つに電子線リソグラフィがある。電子
線リソグラフィとは、電子銃から放出された電子線の断
面形状及び軌道を制御して、感光性材料(電子線レジス
ト)を塗布した基板上に逐次的にパターンを描画してい
く方式である。
2. Description of the Related Art Electron beam lithography is one of the main processes for forming LSI patterns on a semiconductor substrate. Electron beam lithography is a method in which a cross-sectional shape and a trajectory of an electron beam emitted from an electron gun are controlled to sequentially draw a pattern on a substrate coated with a photosensitive material (electron beam resist). .

【0003】図5に従来の電子線描画装置における描画
室の概略構成を示す。図において、電子銃1から放出さ
れた電子線2は、絞り3と成形偏向器4とによって矩形
断面形状に成形され、電子レンズ5と偏向器6とにより
基板7上の任意の位置に結像される。基板7は、静電チ
ャックを備えた基板ホルダ8上に吸着保持され、それに
より基板7の平坦化が行なわれる。これは、基板7が反
った状態であるとパターン形成面が歪んでしまい、高精
度の描画が出来ないためである。基板ホルダ8には、基
板7を吸着保持する誘電体9と、誘電体9に電圧を印加
するための電極10とが設けられており、電極10には
直流電源11が接続されている。また、基板7には接地
用のアースピン12を押し付けられる構造となってお
り、誘電体10に直流電圧を印加すると、誘電体10内
に発生した分極電荷により基板7をアース電位に保ちな
がら誘電体10上に吸着保持することができる。また、
基板ホルダ8は長い移動ストロークを持ったXYステー
ジ13上に固定されている。これにより、電子線の偏向
範囲が数mm□程度であっても、XYステージを移動さ
せることによって基板7全面へのLSIパターンの描画
が可能となる。LSIパターンは、基板上に幾層にも積
み上げられて構成されるため、描画の際には、下地とな
るパターンに精度良く位置合わせを行なう必要がある。
FIG. 5 shows a schematic configuration of a drawing chamber in a conventional electron beam drawing apparatus. In the figure, an electron beam 2 emitted from an electron gun 1 is shaped into a rectangular cross section by a stop 3 and a shaping deflector 4, and is imaged at an arbitrary position on a substrate 7 by an electron lens 5 and a deflector 6. Is done. The substrate 7 is sucked and held on a substrate holder 8 provided with an electrostatic chuck, whereby the substrate 7 is flattened. This is because if the substrate 7 is in a warped state, the pattern formation surface is distorted, and high-precision drawing cannot be performed. The substrate holder 8 is provided with a dielectric 9 for adsorbing and holding the substrate 7 and an electrode 10 for applying a voltage to the dielectric 9, and a DC power supply 11 is connected to the electrode 10. Further, a ground pin 12 for grounding is pressed against the substrate 7. When a DC voltage is applied to the dielectric 10, the dielectric charge is generated in the dielectric 10 while maintaining the substrate 7 at the ground potential. 10 can be held by suction. Also,
The substrate holder 8 is fixed on an XY stage 13 having a long moving stroke. Thus, even if the deflection range of the electron beam is about several mm square, the LSI pattern can be drawn on the entire surface of the substrate 7 by moving the XY stage. Since the LSI pattern is formed by being stacked on a substrate in a number of layers, it is necessary to accurately align the pattern to be a base when drawing.

【0004】ここで、基板7は、アースピン12により
接地されているが、厳密に云えば、0Vにはなっていな
い。これは、誘電体10に電圧を印加した際に流れるリ
ーク電流Iとアースピン12の押し付け部で発生する接
触抵抗Rが原因である。このとき発生する電位Vは、オ
ームの法則により、次の式(1)で表わされる。 V=I×R ・・・(1) 例えば、一般的な静電チャックの誘電体において、体積
抵抗率が109Ω・cm程度であるとすると、表面の接触
状態によっても変わるがリーク電流Iは200μA程度
流れる。ここで、アースピンの接触抵抗Rが20kΩで
あるとすると、基板には4Vの電位が発生する。この発
生電位によって、負の電荷を持つ電子線の軌道が乱さ
れ、描画精度が劣化するという問題が生じる。基板(ウ
エハ)の電位と電子線の軌道との関係については、M.
Miyazaki等により J. Phys.E: Sci. Instrum.
14, 194 (1981) に報告されており、このときのビーム
位置のずれ量△Lは、偏向距離L,加速電圧Uとする
と、次の式(2)で表わされる。 △L/L = −V/(4×U) ・・・(2) 従って、L=2.5mm,U=50kVとすると、上記
した基板電位4V発生時には、50nmもの位置ずれが
発生することになる。半導体素子の微細化が進む中、1
80nmやそれ以下のパターン線幅を描画する際には、
このビーム位置ずれ量は無視できない値である。
[0004] Here, the substrate 7 is grounded by the earth pin 12, but strictly speaking, does not reach 0V. This is due to the leak current I flowing when a voltage is applied to the dielectric 10 and the contact resistance R generated at the pressed portion of the ground pin 12. The potential V generated at this time is expressed by the following equation (1) according to Ohm's law. V = I × R (1) For example, assuming that the volume resistivity of a dielectric material of a general electrostatic chuck is about 10 9 Ω · cm, the leakage current I varies depending on the contact state of the surface. Flows about 200 μA. Here, assuming that the contact resistance R of the ground pin is 20 kΩ, a potential of 4 V is generated on the substrate. The generated potential disturbs the trajectory of the electron beam having a negative charge, causing a problem that the drawing accuracy is deteriorated. Regarding the relationship between the potential of the substrate (wafer) and the trajectory of the electron beam, see M.S.
J. Phys.E: Sci. Instrum. By Miyazaki et al.
14, 194 (1981), and the deviation ΔL of the beam position at this time is represented by the following equation (2), assuming that the deflection distance L and the acceleration voltage U are: ΔL / L = −V / (4 × U) (2) Therefore, if L = 2.5 mm and U = 50 kV, a displacement of as much as 50 nm occurs when the above-described substrate potential 4V is generated. Become. As the miniaturization of semiconductor devices progresses,
When drawing a pattern line width of 80 nm or less,
This beam position shift amount is a value that cannot be ignored.

【0005】そこで、従来は、(a)アースピンの硬度を
上げ基板への押し付け力を強化する等により積極的にア
ースを取って接触抵抗を低減する手法,(b)基板電位発
生分だけ電子線の偏向量を補正する手法,(c)誘電体を
高抵抗化しリーク電流を抑制する手法などを用いてき
た。
Therefore, conventionally, (a) a method of reducing the contact resistance by positively taking the ground by increasing the hardness of the earth pin and increasing the pressing force against the substrate, and (b) an electron beam by an amount corresponding to the generation of the substrate potential (C) a method of increasing the resistance of a dielectric to suppress a leak current.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、アース
ピンを強く基板(ウエハ等)に押し付けても、接触抵抗の
低減には限界があり、数kΩは残ってしまう。特に、プ
ロセスウエハでは、基板表面に厚い絶縁膜が堆積してい
るため、再現性よく接地することは困難である。また、
アースピンの消耗・劣化等によっても接触抵抗は増大す
るため、発生電位のバラツキが生じ、電子線の偏向補正
では対処しきれなくなる。また、誘電体の高抵抗化にお
いては、リーク電流が小さくなってアース不良に対する
効果は高いが、誘電体の抵抗値が高くなるほど蓄積され
た電荷が逃げにくくなるため、残留吸着という問題が発
生する。例えば、1012 Ω・cm台の誘電体を用いた場
合、電圧OFF後2分間経過しても3gf/cm2 もの
残留吸着力が発生することが実験で確認されており、こ
れが基板搬送時のトラブル発生の原因となる。また、残
留電荷は集塵効果を生じるため、塵埃の吸着・挟み込み
によるウエハ吸着時の平面度悪化と云う問題が発生す
る。
However, even if the ground pin is strongly pressed against the substrate (wafer or the like), there is a limit in reducing the contact resistance, and several kΩ remain. In particular, in a process wafer, it is difficult to ground with good reproducibility because a thick insulating film is deposited on the surface of the substrate. Also,
Since the contact resistance also increases due to wear and deterioration of the earth pin, the generated potential varies, and the deflection correction of the electron beam cannot cope with it. Also, in increasing the resistance of the dielectric, the leakage current is reduced and the effect on the ground failure is high. However, the higher the resistance value of the dielectric, the more difficult it is for accumulated charges to escape, resulting in a problem of residual adsorption. . For example, when a dielectric substance of the order of 10 12 Ω · cm is used, it has been confirmed by experiments that a residual adsorption force of 3 gf / cm 2 is generated even after 2 minutes from turning off the voltage. It may cause trouble. In addition, since the residual charge produces a dust collecting effect, there is a problem that the flatness at the time of wafer suction is deteriorated due to dust suction and pinching.

【0007】従って、本発明の目的は、基板に発生する
電位を抑制し、かつ残留吸着を低減することが可能な静
電チャックを提供し、もって信頼性の高い電子線描画装
置を実現することにある。
Accordingly, an object of the present invention is to provide an electrostatic chuck capable of suppressing a potential generated on a substrate and reducing residual adsorption, thereby realizing a highly reliable electron beam drawing apparatus. It is in.

【0008】[0008]

【課題を解決するための手段】上記の目的を達成するた
め、本発明においては、静電チャック内部の電極を2つ
に分割し、各々に極性の異なる直流電源を接続する。ま
た、基板表面には接地のためのアースピンを押し付けた
状態にて、電子線描画を行なう。かかる方式を採用する
ことにより、アースピンに流れる電流を小さくでき、発
生基板電位を低く抑えることができるため、この発生基
板電位に起因して生じるビーム位置ずれを防止でき、信
頼性の高い電子線描画を実現できる。
In order to achieve the above-mentioned object, in the present invention, the electrode inside the electrostatic chuck is divided into two, and each of them is connected to a DC power supply having a different polarity. Electron beam drawing is performed with a ground pin pressed against the surface of the substrate. By adopting this method, the current flowing through the ground pin can be reduced, and the potential of the generated substrate can be suppressed. Therefore, it is possible to prevent a beam position shift caused by the potential of the generated substrate, and to achieve highly reliable electron beam writing. Can be realized.

【0009】[0009]

【発明の実施の形態】以下、本発明の実施の形態につ
き、実施例を挙げ、図面を参照して詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below in detail with reference to the drawings.

【0010】〈実施例1〉図1に、本発明の一実施例に
なる電子線描画装置全体の概略構成を示す。図におい
て、電子銃1には高圧電源19が接続され、電子線2が
放射される。電子線2は、絞り3を通過し、偏向制御系
20により制御される成形偏向器4によって矩形断面形
状に成形される。さらに、レンズ電源21が接続された
電子レンズ5と偏向器6とを制御することによって、電
子線2は基板(ウエハ)14上の任意の位置に結像され
る。ウエハ14は、基板ホルダ8上に固定保持され、さ
らに基板ホルダ8はXYステージ13上に固定されてい
る。基板ホルダ8のウエハ保持面は誘電体9で構成さ
れ、その内部に埋め込まれた半月形で互いに面積の等し
い2つの電極10a,10bには、直流電圧を印加出来
るように給電端子15が設けられている。各給電端子1
5には、互いに極性が異なりかつ絶対値が等しい直流電
圧を出力する2つの直流電源16a,16bがスイッチ
17を介して接続されており、スイッチ17のOFF時
には各電極がアース電位になるよう構成されている。接
地された基板ホルダ8には、アースピン12が組み込ま
れており、このアースピン12をウエハ14上に押し付
けるための機構が付設されている。これによりウエハ1
4はアース電位になり、描画時には、スイッチ17をO
Nとすることにより、ウエハ14は誘電体9上面に吸着
保持される。XYステージ13には反射鏡22が固定さ
れ、レーザー干渉計23によりXYステージ13の位置
が測定される。描画中は、XYステージ13を所定の位
置に移動すべく、ステージ駆動系24によってステージ
13の位置制御が行なわれる。各制御系は中央演算処理
装置25に接続されて、描画における統括的な制御が行
なわれる。
FIG. 1 shows a schematic configuration of an entire electron beam lithography apparatus according to an embodiment of the present invention. In the figure, a high-voltage power supply 19 is connected to an electron gun 1 and an electron beam 2 is emitted. The electron beam 2 passes through the stop 3 and is shaped into a rectangular cross section by a shaping deflector 4 controlled by a deflection control system 20. Further, by controlling the electron lens 5 and the deflector 6 to which the lens power supply 21 is connected, the electron beam 2 is imaged at an arbitrary position on the substrate (wafer) 14. The wafer 14 is fixed and held on the substrate holder 8, and the substrate holder 8 is fixed on the XY stage 13. The wafer holding surface of the substrate holder 8 is composed of a dielectric material 9, and two half-moon-shaped electrodes 10a and 10b embedded in the dielectric body 9 are provided with a power supply terminal 15 so that a DC voltage can be applied. ing. Each power supply terminal 1
5 is connected via a switch 17 to two DC power supplies 16a and 16b which output DC voltages having different polarities and the same absolute value. When the switch 17 is turned off, each electrode has a ground potential. Have been. Ground pins 12 are incorporated in the grounded substrate holder 8, and a mechanism for pressing the ground pins 12 onto the wafer 14 is provided. Thereby, the wafer 1
4 is at ground potential, and switch 17 is set to O
By setting N, the wafer 14 is suction-held on the upper surface of the dielectric 9. The reflecting mirror 22 is fixed to the XY stage 13, and the position of the XY stage 13 is measured by the laser interferometer 23. During drawing, the position of the stage 13 is controlled by the stage drive system 24 in order to move the XY stage 13 to a predetermined position. Each control system is connected to the central processing unit 25 to perform overall control in drawing.

【0011】ここで、本発明における発生基板電位の低
減原理について説明する。図2に、図1における静電チ
ャック部分の構成模式図及びその電気的な等価回路を示
す。この等価回路の閉路方程式を解くことにより発生ウ
エハ電位Vw が求められる。その結果を次の式(3)に示
す。 Vw = (Va/Ra−Vb/Rb)×(1/Ra+1/Rb+1/Rw)-1 ・・・(3) ここで、+Va,-Vb … 電源16a,16bによる印加電
圧 Ra, Rb … 電極10a,10b側での抵抗成分 Rw … アースピン12の接触抵抗 つまり、発生ウエハ電位Vw は、アースピン12に流れ
る電流値と各抵抗成分の並列時の合成抵抗値との積であ
るが、Ra,Rb>>Rw であるので、合成抵抗値≒Rw
となる。従って、従来と比較し、アースピンに流れる電
流が小さくなる分だけ発生電位が小さくなる。例えば、
Ra=Rb=4MΩ,Rw=50kΩ,Va=405V,V
b =−395Vとおくと、従来方式ではアースピンに1
00μAの電流が流れるため、Vw =5Vの電位が発生
したが、本発明ではアースピンに2.5μAしか流れな
いため、発生ウエハ電位もVw =0.12Vと約1/4
0になる。この結果、電子線の位置ずれ量も1/40に
低減され、高精度な描画が可能となった。
Here, the principle of reducing the generated substrate potential in the present invention will be described. FIG. 2 shows a schematic configuration diagram of the electrostatic chuck portion in FIG. 1 and an electrical equivalent circuit thereof. The generated wafer potential Vw is obtained by solving the closed circuit equation of this equivalent circuit. The result is shown in the following equation (3). Vw = (Va / Ra−Vb / Rb) × (1 / Ra + 1 / Rb + 1 / Rw) −1 (3) where + Va, −Vb... Voltages applied by the power supplies 16a and 16b Ra, Rb. Resistance components Rw on the 10a, 10b side Contact resistance of earth pin 12 In other words, the generated wafer potential Vw is the product of the current value flowing through the ground pin 12 and the combined resistance value of each resistance component in parallel, but Ra, Rb >> Rw, the combined resistance value ≒ Rw
Becomes Therefore, as compared with the conventional case, the generated potential is reduced by an amount corresponding to the reduction in the current flowing through the ground pin. For example,
Ra = Rb = 4MΩ, Rw = 50kΩ, Va = 405V, V
If b = −395V, the conventional method requires 1
Since a current of 00 μA flows, a potential of Vw = 5 V is generated. However, in the present invention, since only 2.5 μA flows through the ground pin, the generated wafer potential is also about 1/4 of Vw = 0.12 V.
It becomes 0. As a result, the amount of displacement of the electron beam is reduced to 1/40, and high-precision drawing is enabled.

【0012】〈実施例2〉図3に本発明の第二の実施例
になる電子線描画装置における静電チャック部の概略構
成を示す。図において、誘電体9内には同心円形状の2
つの電極10a,10bが埋め込まれており、各々の給
電端子15には直流電源16a,16bが接続されてい
る。電極10a,10bの直径は各々120mmφ,2
00mmφとなっており、面積比は約1.8:1であ
る。よって、直流電源16a,16bの電圧比をその逆
数の1:1.8すなわち300V,−540Vに設定す
ることにより、各電極を流れる電流値が等しくなり、ア
ースピンを流れる電流値を抑えることができ、発生ウエ
ハ電位の抑制が可能となった。但し、印加電圧が異なる
と吸着力も変化するため、面積比を1:1に近づけるこ
とがより好ましい。
Embodiment 2 FIG. 3 shows a schematic configuration of an electrostatic chuck portion in an electron beam lithography apparatus according to a second embodiment of the present invention. In the figure, a concentric 2
Two electrodes 10a and 10b are embedded, and a DC power supply 16a and 16b is connected to each power supply terminal 15. The diameter of each of the electrodes 10a and 10b is 120 mmφ, 2
00 mmφ, and the area ratio is about 1.8: 1. Therefore, by setting the voltage ratio of the DC power supplies 16a and 16b to the reciprocal of 1: 1.8, that is, 300 V and -540 V, the current flowing through each electrode becomes equal, and the current flowing through the ground pin can be suppressed. Thus, the generated wafer potential can be suppressed. However, if the applied voltage differs, the attraction force also changes. Therefore, it is more preferable to make the area ratio close to 1: 1.

【0013】〈実施例3〉図4に本発明の第三の実施例
になる電子線描画装置における静電チャック部の概略構
成を示す。図において、誘電体9の内部には櫛(くし)歯
形状をした2つの電極10a,10bが埋め込まれてお
り、各電極への給電端子15には直流電源16a,16
bと電流計18a,18bとが接続されている。直流電
源の一方の16aは、出力電圧調整が可能な可変直流電
圧電源となっており、2つの電流計18a,18bの指
示電流値が等しくなるようにその出力電圧値を調整する
ことが可能である。これにより、くし歯状電極の形状差
や誘電体9の抵抗値分布等が生じていても、アースピン
12に流れる電流値を十分に低減することができる。例
えば、2つの電極に流れる電流値の差を1μA以下に抑
えることにより、従来100μA流れていたとした時に
生じるビーム位置ずれ量をその1/100以下に低減で
き、アース不具合による描画不良問題を効果的に解決す
ることが可能となった。
Embodiment 3 FIG. 4 shows a schematic configuration of an electrostatic chuck section in an electron beam lithography apparatus according to a third embodiment of the present invention. In the figure, two electrodes 10a and 10b having a comb shape are embedded in a dielectric 9 and a DC power supply 16a, 16
b and ammeters 18a and 18b are connected. One of the DC power supplies 16a is a variable DC voltage power supply capable of adjusting the output voltage, and its output voltage value can be adjusted so that the indicated current values of the two ammeters 18a and 18b become equal. is there. Thus, the current flowing through the ground pin 12 can be sufficiently reduced even if there is a difference in the shape of the interdigital electrode or the distribution of the resistance of the dielectric material 9. For example, by suppressing the difference between the values of the currents flowing through the two electrodes to 1 μA or less, the amount of beam misalignment that would otherwise occur when a current of 100 μA was applied can be reduced to 1/100 or less, and the drawing failure problem due to a ground defect can be effectively reduced. It became possible to solve.

【0014】[0014]

【発明の効果】本発明により、基板(ウエハ)の静電吸着
時において、アースピンの接触具合に左右されずに発生
基板電位を効果的に低減でき、もって信頼性の高い電子
線描画が可能となる。
According to the present invention, when electrostatically attracting a substrate (wafer), the potential of the generated substrate can be effectively reduced without being influenced by the contact condition of the ground pin, and thus highly reliable electron beam drawing can be performed. Become.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第一の実施例になる電子線描画装置の
概略構成を示す図。
FIG. 1 is a diagram showing a schematic configuration of an electron beam lithography apparatus according to a first embodiment of the present invention.

【図2】図1に示した実施例における発生基板(ウエハ)
電位の低減原理を説明するための静電チャック部の模式
構成及びその等価回路を示す図。
FIG. 2 shows a generating substrate (wafer) in the embodiment shown in FIG.
FIG. 4 is a diagram illustrating a schematic configuration of an electrostatic chuck unit and an equivalent circuit thereof for explaining a principle of reducing a potential;

【図3】本発明の第二の実施例になる電子線描画装置に
おける静電チャック部の概略構成を示す図。
FIG. 3 is a diagram illustrating a schematic configuration of an electrostatic chuck unit in an electron beam lithography apparatus according to a second embodiment of the present invention.

【図4】本発明の第三の実施例になる電子線描画装置に
おける静電チャック部の概略構成を示す図。
FIG. 4 is a diagram showing a schematic configuration of an electrostatic chuck section in an electron beam lithography apparatus according to a third embodiment of the present invention.

【図5】従来の電子線描画装置における描画室内の概略
構成を示す図。
FIG. 5 is a diagram showing a schematic configuration of a drawing chamber in a conventional electron beam drawing apparatus.

【符号の説明】[Explanation of symbols]

1…電子銃, 2…電子線, 3
…絞り,4…成形偏向器, 5…電子レンズ,
6…偏向器,7…基板, 8…基板
ホルダ, 9…誘電体,10…電極,
11…直流電源, 12…アースピン,13…
XYステージ, 14…ウエハ, 15…給
電端子,16…直流電源, 17…スイッチ,
18…電流計,19…高圧電源, 20…
偏向制御系, 21…レンズ電源,22…反射鏡,
23…レーザー干渉計, 24…ステージ駆
動系,25…中央演算処理装置。
1 ... Electron gun, 2 ... Electron beam, 3
... Aperture, 4 ... Shaping deflector, 5 ... Electronic lens,
6: deflector, 7: substrate, 8: substrate holder, 9: dielectric, 10: electrode,
11 DC power supply 12 Ground pin 13
XY stage, 14 wafer, 15 power supply terminal, 16 DC power supply, 17 switch,
18 ... ammeter, 19 ... high voltage power supply, 20 ...
Deflection control system, 21: lens power supply, 22: reflecting mirror,
23: laser interferometer, 24: stage drive system, 25: central processing unit.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】誘電体下面に形成された電極と上記誘電体
上面に載置された半導体基板との間に電圧を印加するこ
とによって上記半導体基板を上記誘電体上面に吸着保持
する静電吸着方式の基板保持具を具備してなる電子線描
画装置であって、上記電極は2枚の電極部分に分割され
ていて、各電極部分には互いに極性の異なる直流電圧が
印加されており、かつ、上記半導体基板を接地手段によ
って接地しながら上記半導体基板上にパターン描画を行
なう如く構成されてなることを特徴とする電子線描画装
置。
An electrostatic chuck for attracting and holding the semiconductor substrate on the dielectric upper surface by applying a voltage between an electrode formed on the lower surface of the dielectric and a semiconductor substrate mounted on the upper surface of the dielectric. An electron beam lithography apparatus comprising a substrate holder of the system, wherein the electrodes are divided into two electrode portions, and DC voltages having different polarities are applied to each electrode portion, and An electron beam lithography apparatus configured to perform pattern drawing on the semiconductor substrate while grounding the semiconductor substrate by grounding means.
【請求項2】上記2枚の電極部分のうち少なくとも一方
の電極部分に印加する上記直流電圧の値を調整するため
の電圧可変手段が付設されてなることを特徴とする請求
項1に記載の電子線描画装置。
2. The apparatus according to claim 1, further comprising a voltage varying means for adjusting a value of the DC voltage applied to at least one of the two electrode portions. Electron beam drawing equipment.
【請求項3】上記2枚の電極部分のそれぞれの電極面積
は互いにほぼ同等であり、かつ上記2枚の電極部分にそ
れぞれ印加される上記極性の異なる直流電圧の値はその
絶対値がほぼ同等であることを特徴とする請求項1又は
2に記載の電子線描画装置。
3. The electrode areas of the two electrode portions are substantially equal to each other, and the DC voltages of different polarities applied to the two electrode portions have substantially equal absolute values. The electron beam lithography apparatus according to claim 1, wherein:
【請求項4】上記2枚の電極部分間の電極面積比は、上
記2枚の電極部分のそれぞれに印加される上記直流電圧
の絶対値間での比の逆数とほぼ同等に設定されてなるこ
とを特徴とする請求項1又は2に記載の電子線描画装
置。
4. An electrode area ratio between the two electrode portions is set substantially equal to a reciprocal of a ratio between absolute values of the DC voltage applied to each of the two electrode portions. 3. The electron beam lithography apparatus according to claim 1, wherein:
【請求項5】上記の電圧可変手段は、上記2枚の電極部
分のそれぞれに流れる電流値が互いにほぼ等しくなるよ
うに、上記2枚の電極部分のうち少なくとも一方の電極
部分に印加する上記直流電圧の値を調整するものである
ことを特徴とする請求項2に記載の電子線描画装置。
5. The DC voltage applying means according to claim 1, wherein said DC voltage applied to at least one of said two electrode portions is such that current values flowing through said two electrode portions are substantially equal to each other. 3. The electron beam writing apparatus according to claim 2, wherein the value of the voltage is adjusted.
JP2000072457A 2000-03-10 2000-03-10 Electron beam lithography system Pending JP2001257158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000072457A JP2001257158A (en) 2000-03-10 2000-03-10 Electron beam lithography system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000072457A JP2001257158A (en) 2000-03-10 2000-03-10 Electron beam lithography system

Publications (1)

Publication Number Publication Date
JP2001257158A true JP2001257158A (en) 2001-09-21

Family

ID=18590863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000072457A Pending JP2001257158A (en) 2000-03-10 2000-03-10 Electron beam lithography system

Country Status (1)

Country Link
JP (1) JP2001257158A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108643A (en) * 2004-09-10 2006-04-20 Hitachi High-Technologies Corp For charged particle beam lithography device and charged particle beam lithography method
KR20070052660A (en) * 2005-11-17 2007-05-22 가부시키가이샤 이빔 Substrate treatment apparatus and substrate treatment method
WO2010140649A1 (en) * 2009-06-04 2010-12-09 株式会社 日立ハイテクノロジーズ Charged particle beam device and evaluation method using the charged particle beam device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108643A (en) * 2004-09-10 2006-04-20 Hitachi High-Technologies Corp For charged particle beam lithography device and charged particle beam lithography method
US7408760B2 (en) 2004-09-10 2008-08-05 Hitachi High-Technologies Corporation Charged particle beam application system
JP4637684B2 (en) * 2004-09-10 2011-02-23 株式会社日立ハイテクノロジーズ Charged particle beam application equipment
KR20070052660A (en) * 2005-11-17 2007-05-22 가부시키가이샤 이빔 Substrate treatment apparatus and substrate treatment method
WO2010140649A1 (en) * 2009-06-04 2010-12-09 株式会社 日立ハイテクノロジーズ Charged particle beam device and evaluation method using the charged particle beam device
JP2010282825A (en) * 2009-06-04 2010-12-16 Hitachi High-Technologies Corp Charged particle beam device and evaluation method using the same
US8653455B2 (en) 2009-06-04 2014-02-18 Hitachi High-Technologies Corporation Charged particle beam device and evaluation method using the charged particle beam device

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