JP2001256105A - 非整列循環アドレス指定を用いるマイクロプロセッサ - Google Patents
非整列循環アドレス指定を用いるマイクロプロセッサInfo
- Publication number
- JP2001256105A JP2001256105A JP2001042414A JP2001042414A JP2001256105A JP 2001256105 A JP2001256105 A JP 2001256105A JP 2001042414 A JP2001042414 A JP 2001042414A JP 2001042414 A JP2001042414 A JP 2001042414A JP 2001256105 A JP2001256105 A JP 2001256105A
- Authority
- JP
- Japan
- Prior art keywords
- address
- memory
- data
- instruction
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
- G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
- G06F9/30014—Arithmetic instructions with variable precision
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30109—Register structure having multiple operands in a single register
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30112—Register structure comprising data of variable length
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/355—Indexed addressing
- G06F9/3552—Indexed addressing using wraparound, e.g. modulo or circular addressing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/355—Indexed addressing
- G06F9/3555—Indexed addressing using scaling, e.g. multiplication of index
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
- G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
- Memory System (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US18341700P | 2000-02-18 | 2000-02-18 | |
| US183417 | 2000-10-31 | ||
| US703105 | 2000-10-31 | ||
| US09/703,105 US6539467B1 (en) | 1999-11-15 | 2000-10-31 | Microprocessor with non-aligned memory access |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001256105A true JP2001256105A (ja) | 2001-09-21 |
| JP2001256105A5 JP2001256105A5 (enExample) | 2008-04-03 |
Family
ID=26879103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001042414A Abandoned JP2001256105A (ja) | 2000-02-18 | 2001-02-19 | 非整列循環アドレス指定を用いるマイクロプロセッサ |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6539467B1 (enExample) |
| EP (1) | EP1126368B1 (enExample) |
| JP (1) | JP2001256105A (enExample) |
| DE (1) | DE60139825D1 (enExample) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007234065A (ja) * | 2002-06-28 | 2007-09-13 | Renesas Technology Corp | データ処理装置 |
| JP2008530714A (ja) * | 2005-02-17 | 2008-08-07 | クゥアルコム・インコーポレイテッド | 非整列メモリアクセス予測 |
| JP2009238132A (ja) * | 2008-03-28 | 2009-10-15 | Nec Corp | データ処理装置 |
| JP2010044487A (ja) * | 2008-08-11 | 2010-02-25 | Seiko Epson Corp | 信号処理プロセッサ及び半導体装置 |
| JP2015164061A (ja) * | 2009-12-17 | 2015-09-10 | インテル・コーポレーション | 単一命令でシフト・アンド・排他的論理和演算を行う方法および装置 |
| JP2016526220A (ja) * | 2013-05-24 | 2016-09-01 | コーヒレント・ロジックス・インコーポレーテッド | プログラム可能な最適化を有するメモリネットワークプロセッサ |
Families Citing this family (66)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6643765B1 (en) * | 1995-08-16 | 2003-11-04 | Microunity Systems Engineering, Inc. | Programmable processor with group floating point operations |
| US5953241A (en) * | 1995-08-16 | 1999-09-14 | Microunity Engeering Systems, Inc. | Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction |
| US7301541B2 (en) | 1995-08-16 | 2007-11-27 | Microunity Systems Engineering, Inc. | Programmable processor and method with wide operations |
| US6295599B1 (en) | 1995-08-16 | 2001-09-25 | Microunity Systems Engineering | System and method for providing a wide operand architecture |
| US6775758B2 (en) * | 2000-12-21 | 2004-08-10 | Hewlett-Packard Development Company, L.P. | Buffer page roll implementation for PCI-X block read transactions |
| US7653710B2 (en) | 2002-06-25 | 2010-01-26 | Qst Holdings, Llc. | Hardware task manager |
| US7489779B2 (en) | 2001-03-22 | 2009-02-10 | Qstholdings, Llc | Hardware implementation of the secure hash standard |
| US7400668B2 (en) | 2001-03-22 | 2008-07-15 | Qst Holdings, Llc | Method and system for implementing a system acquisition function for use with a communication device |
| US7962716B2 (en) | 2001-03-22 | 2011-06-14 | Qst Holdings, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
| US7752419B1 (en) | 2001-03-22 | 2010-07-06 | Qst Holdings, Llc | Method and system for managing hardware resources to implement system functions using an adaptive computing architecture |
| US6836839B2 (en) | 2001-03-22 | 2004-12-28 | Quicksilver Technology, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
| US20040133745A1 (en) | 2002-10-28 | 2004-07-08 | Quicksilver Technology, Inc. | Adaptable datapath for a digital processing system |
| US6577678B2 (en) | 2001-05-08 | 2003-06-10 | Quicksilver Technology | Method and system for reconfigurable channel coding |
| US6912173B2 (en) * | 2001-06-29 | 2005-06-28 | Broadcom Corporation | Method and system for fast memory access |
| US6789179B2 (en) * | 2001-06-29 | 2004-09-07 | Broadcom Corporation | Method and system for fast data access using a memory array |
| JP2003099250A (ja) * | 2001-09-20 | 2003-04-04 | Oki Electric Ind Co Ltd | レジスタ読み出し回路及びマイクロプロセッサ |
| US7046635B2 (en) | 2001-11-28 | 2006-05-16 | Quicksilver Technology, Inc. | System for authorizing functionality in adaptable hardware devices |
| US6986021B2 (en) | 2001-11-30 | 2006-01-10 | Quick Silver Technology, Inc. | Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements |
| US8412915B2 (en) | 2001-11-30 | 2013-04-02 | Altera Corporation | Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements |
| US7602740B2 (en) | 2001-12-10 | 2009-10-13 | Qst Holdings, Inc. | System for adapting device standards after manufacture |
| US7215701B2 (en) | 2001-12-12 | 2007-05-08 | Sharad Sambhwani | Low I/O bandwidth method and system for implementing detection and identification of scrambling codes |
| US7403981B2 (en) | 2002-01-04 | 2008-07-22 | Quicksilver Technology, Inc. | Apparatus and method for adaptive multimedia reception and transmission in communication environments |
| US7493375B2 (en) | 2002-04-29 | 2009-02-17 | Qst Holding, Llc | Storage and delivery of device features |
| US7660984B1 (en) | 2003-05-13 | 2010-02-09 | Quicksilver Technology | Method and system for achieving individualized protected space in an operating system |
| US7328414B1 (en) | 2003-05-13 | 2008-02-05 | Qst Holdings, Llc | Method and system for creating and programming an adaptive computing engine |
| EP1369774A1 (fr) * | 2002-06-06 | 2003-12-10 | CSEM Centre Suisse d'Electronique et de Microtechnique SA Recherche et Développement | Dispositif d'élaboration d'adresses pour un processeur de signaux numériques |
| US8108656B2 (en) | 2002-08-29 | 2012-01-31 | Qst Holdings, Llc | Task definition for specifying resource requirements |
| US7937591B1 (en) | 2002-10-25 | 2011-05-03 | Qst Holdings, Llc | Method and system for providing a device which can be adapted on an ongoing basis |
| US7478031B2 (en) | 2002-11-07 | 2009-01-13 | Qst Holdings, Llc | Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information |
| US8276135B2 (en) | 2002-11-07 | 2012-09-25 | Qst Holdings Llc | Profiling of software and circuit designs utilizing data operation analyses |
| US7225301B2 (en) | 2002-11-22 | 2007-05-29 | Quicksilver Technologies | External memory controller node |
| US7571287B2 (en) | 2003-03-13 | 2009-08-04 | Marvell World Trade Ltd. | Multiport memory architecture, devices and systems including the same, and methods of using the same |
| US7286976B2 (en) * | 2003-06-10 | 2007-10-23 | Mentor Graphics (Holding) Ltd. | Emulation of circuits with in-circuit memory |
| US7609297B2 (en) | 2003-06-25 | 2009-10-27 | Qst Holdings, Inc. | Configurable hardware based digital imaging apparatus |
| CN1293462C (zh) * | 2003-07-23 | 2007-01-03 | 凌阳科技股份有限公司 | 一种执行不同长度指令集的处理器及方法 |
| US7721069B2 (en) | 2004-07-13 | 2010-05-18 | 3Plus1 Technology, Inc | Low power, high performance, heterogeneous, scalable processor architecture |
| KR20070055487A (ko) * | 2004-07-13 | 2007-05-30 | 쓰리플러스원 테크놀러지, 인크 | 프로그램가능한 프로세서 아키텍처 |
| US20060200649A1 (en) * | 2005-02-17 | 2006-09-07 | Texas Instruments Incorporated | Data alignment and sign extension in a processor |
| US7434040B2 (en) * | 2005-07-25 | 2008-10-07 | Hewlett-Packard Development Company, L.P. | Copying of unaligned data in a pipelined operation |
| US20070050592A1 (en) * | 2005-08-31 | 2007-03-01 | Gschwind Michael K | Method and apparatus for accessing misaligned data streams |
| US7395517B2 (en) * | 2005-09-20 | 2008-07-01 | International Business Machines Corporation | Data aligner in reconfigurable computing environment |
| US7366842B1 (en) * | 2005-12-15 | 2008-04-29 | Nvidia Corporation | Creating permanent storage on the fly within existing buffers |
| US7873953B1 (en) | 2006-01-20 | 2011-01-18 | Altera Corporation | High-level language code sequence optimization for implementing programmable chip designs |
| US8156310B2 (en) * | 2006-09-11 | 2012-04-10 | International Business Machines Corporation | Method and apparatus for data stream alignment support |
| US8127104B1 (en) | 2007-08-06 | 2012-02-28 | Marvell International Ltd. | Alignment matrix memory copy |
| US8688947B1 (en) * | 2007-11-21 | 2014-04-01 | Marvell International Ltd. | Aligned data access |
| US8131915B1 (en) | 2008-04-11 | 2012-03-06 | Marvell Intentional Ltd. | Modifying or overwriting data stored in flash memory |
| US8683085B1 (en) | 2008-05-06 | 2014-03-25 | Marvell International Ltd. | USB interface configurable for host or device mode |
| US8423710B1 (en) | 2009-03-23 | 2013-04-16 | Marvell International Ltd. | Sequential writes to flash memory |
| US8213236B1 (en) | 2009-04-21 | 2012-07-03 | Marvell International Ltd. | Flash memory |
| US8127078B2 (en) * | 2009-10-02 | 2012-02-28 | International Business Machines Corporation | High performance unaligned cache access |
| US8356145B2 (en) * | 2010-01-15 | 2013-01-15 | Qualcomm Incorporated | Multi-stage multiplexing operation including combined selection and data alignment or data replication |
| US8756394B1 (en) | 2010-07-07 | 2014-06-17 | Marvell International Ltd. | Multi-dimension memory timing tuner |
| CN102609378B (zh) * | 2012-01-18 | 2016-03-30 | 中国科学院计算技术研究所 | 一种消息式内存访问装置及其访问方法 |
| US9575755B2 (en) | 2012-08-03 | 2017-02-21 | International Business Machines Corporation | Vector processing in an active memory device |
| US9632777B2 (en) * | 2012-08-03 | 2017-04-25 | International Business Machines Corporation | Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry |
| US9569211B2 (en) | 2012-08-03 | 2017-02-14 | International Business Machines Corporation | Predication in a vector processor |
| US9594724B2 (en) | 2012-08-09 | 2017-03-14 | International Business Machines Corporation | Vector register file |
| US9477473B2 (en) * | 2012-12-31 | 2016-10-25 | Cadence Design Systems, Inc. | Bit-level register file updates in extensible processor architecture |
| US9448801B2 (en) | 2012-12-31 | 2016-09-20 | Cadence Design Systems, Inc. | Automatic register port selection in extensible processor architecture |
| US9606803B2 (en) * | 2013-07-15 | 2017-03-28 | Texas Instruments Incorporated | Highly integrated scalable, flexible DSP megamodule architecture |
| US10180829B2 (en) * | 2015-12-15 | 2019-01-15 | Nxp Usa, Inc. | System and method for modulo addressing vectorization with invariant code motion |
| US10884939B2 (en) * | 2018-06-11 | 2021-01-05 | Amazon Technologies, Inc. | Cache pre-fetching using cyclic buffer |
| US10936317B2 (en) * | 2019-05-24 | 2021-03-02 | Texas Instruments Incorporated | Streaming address generation |
| US11755324B2 (en) * | 2021-08-31 | 2023-09-12 | International Business Machines Corporation | Gather buffer management for unaligned and gather load operations |
| FR3152078B1 (fr) * | 2023-08-09 | 2025-07-18 | St Microelectronics Int Nv | Système mémoire |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814976C1 (en) | 1986-12-23 | 2002-06-04 | Mips Tech Inc | Risc computer with unaligned reference handling and method for the same |
| US5329471A (en) * | 1987-06-02 | 1994-07-12 | Texas Instruments Incorporated | Emulation devices, systems and methods utilizing state machines |
| US5072418A (en) * | 1989-05-04 | 1991-12-10 | Texas Instruments Incorporated | Series maxium/minimum function computing devices, systems and methods |
| US5535331A (en) * | 1987-09-04 | 1996-07-09 | Texas Instruments Incorporated | Processor condition sensing circuits, systems and methods |
| JP3644959B2 (ja) * | 1992-09-29 | 2005-05-11 | セイコーエプソン株式会社 | マイクロプロセッサシステム |
| US6219773B1 (en) * | 1993-10-18 | 2001-04-17 | Via-Cyrix, Inc. | System and method of retiring misaligned write operands from a write buffer |
| EP0651321B1 (en) * | 1993-10-29 | 2001-11-14 | Advanced Micro Devices, Inc. | Superscalar microprocessors |
| DE69616718D1 (de) * | 1995-05-26 | 2001-12-13 | Nat Semiconductor Corp | Vorrichtung und verfahren zur bestimmung von adressen fehlausgerichteter daten |
| US5617543A (en) * | 1995-05-26 | 1997-04-01 | National Semiconductor Corporation | Non-arithmetical circular buffer cell availability status indicator circuit |
| US5987561A (en) * | 1995-08-31 | 1999-11-16 | Advanced Micro Devices, Inc. | Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle |
| US5940859A (en) * | 1995-12-19 | 1999-08-17 | Intel Corporation | Emptying packed data state during execution of packed data instructions |
| US6182203B1 (en) * | 1997-01-24 | 2001-01-30 | Texas Instruments Incorporated | Microprocessor |
| US6289418B1 (en) * | 1997-03-31 | 2001-09-11 | Sun Microsystems, Inc. | Address pipelined stack caching method |
| US6167466A (en) * | 1997-07-09 | 2000-12-26 | Texas Instruments Incorporated | Multi-channel serial port with programmable features |
| US6260137B1 (en) * | 1997-09-12 | 2001-07-10 | Siemens Aktiengesellschaft | Data processing unit with digital signal processing capabilities |
| US6073228A (en) * | 1997-09-18 | 2000-06-06 | Lucent Technologies Inc. | Modulo address generator for generating an updated address |
| US5864703A (en) * | 1997-10-09 | 1999-01-26 | Mips Technologies, Inc. | Method for providing extended precision in SIMD vector arithmetic operations |
| US6061779A (en) * | 1998-01-16 | 2000-05-09 | Analog Devices, Inc. | Digital signal processor having data alignment buffer for performing unaligned data accesses |
| US6349383B1 (en) * | 1998-09-10 | 2002-02-19 | Ip-First, L.L.C. | System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for execution |
| US6209082B1 (en) * | 1998-11-17 | 2001-03-27 | Ip First, L.L.C. | Apparatus and method for optimizing execution of push all/pop all instructions |
-
2000
- 2000-10-31 US US09/703,105 patent/US6539467B1/en not_active Expired - Lifetime
-
2001
- 2001-02-19 EP EP01000022A patent/EP1126368B1/en not_active Expired - Lifetime
- 2001-02-19 JP JP2001042414A patent/JP2001256105A/ja not_active Abandoned
- 2001-02-19 DE DE60139825T patent/DE60139825D1/de not_active Expired - Lifetime
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007234065A (ja) * | 2002-06-28 | 2007-09-13 | Renesas Technology Corp | データ処理装置 |
| JP2008530714A (ja) * | 2005-02-17 | 2008-08-07 | クゥアルコム・インコーポレイテッド | 非整列メモリアクセス予測 |
| JP2011150712A (ja) * | 2005-02-17 | 2011-08-04 | Qualcomm Inc | 非アラインドメモリアクセス予測 |
| JP4856100B2 (ja) * | 2005-02-17 | 2012-01-18 | クゥアルコム・インコーポレイテッド | 非アラインドメモリアクセス予測 |
| JP2009238132A (ja) * | 2008-03-28 | 2009-10-15 | Nec Corp | データ処理装置 |
| JP2010044487A (ja) * | 2008-08-11 | 2010-02-25 | Seiko Epson Corp | 信号処理プロセッサ及び半導体装置 |
| JP2015164061A (ja) * | 2009-12-17 | 2015-09-10 | インテル・コーポレーション | 単一命令でシフト・アンド・排他的論理和演算を行う方法および装置 |
| US9495165B2 (en) | 2009-12-17 | 2016-11-15 | Intel Corporation | Method and apparatus for performing a shift and exclusive or operation in a single instruction |
| US9501281B2 (en) | 2009-12-17 | 2016-11-22 | Intel Corporation | Method and apparatus for performing a shift and exclusive or operation in a single instruction |
| US9747105B2 (en) | 2009-12-17 | 2017-08-29 | Intel Corporation | Method and apparatus for performing a shift and exclusive or operation in a single instruction |
| JP2017152016A (ja) * | 2009-12-17 | 2017-08-31 | インテル・コーポレーション | 単一命令でシフト・アンド・排他的論理和演算を行うシステム |
| US10684855B2 (en) | 2009-12-17 | 2020-06-16 | Intel Corporation | Method and apparatus for performing a shift and exclusive or operation in a single instruction |
| JP2016526220A (ja) * | 2013-05-24 | 2016-09-01 | コーヒレント・ロジックス・インコーポレーテッド | プログラム可能な最適化を有するメモリネットワークプロセッサ |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1126368B1 (en) | 2009-09-09 |
| US6539467B1 (en) | 2003-03-25 |
| EP1126368A2 (en) | 2001-08-22 |
| DE60139825D1 (de) | 2009-10-22 |
| EP1126368A3 (en) | 2007-04-25 |
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