JP2001255832A - Display panel - Google Patents
Display panelInfo
- Publication number
- JP2001255832A JP2001255832A JP2000066672A JP2000066672A JP2001255832A JP 2001255832 A JP2001255832 A JP 2001255832A JP 2000066672 A JP2000066672 A JP 2000066672A JP 2000066672 A JP2000066672 A JP 2000066672A JP 2001255832 A JP2001255832 A JP 2001255832A
- Authority
- JP
- Japan
- Prior art keywords
- display panel
- glass substrate
- semiconductor elements
- semiconductor element
- display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ガラス基板に半導
体素子を実装した表示パネルに関する。The present invention relates to a display panel in which a semiconductor element is mounted on a glass substrate.
【０００２】[0002]
【従来の技術】近年、表示パネルの半導体素子の実装技
術は、高密度化、高品質化、薄型化が進行している。2. Description of the Related Art In recent years, the technology for mounting semiconductor elements on a display panel has been increasing in density, quality, and thickness.
【０００３】例えば、液晶表示装置における液晶駆動用
ＬＳＩの実装方法は、ＴＡＢ方式（Ｔａｐｅ Ａｕｔｏ
ｍａｔｅｄ Ｂｏｎｄｉｎｇ方式）から、フリップチッ
プ方式（Ｆｌｉｐ Ｃｈｉｐ Ｂｏｎｄｉｎｇ方式）の
中のＣＯＧ方式（ＣｈｉｐＯｎ Ｇｌａｓｓ方式）へ移
行している。このＣＯＧ方式は、液晶表示装置用の表示
パネルのガラス基板上の配線電極に半導体素子に設けた
突起電極（バンプ）を電気的に接続する。For example, a mounting method of a liquid crystal driving LSI in a liquid crystal display device is a TAB method (Tape Auto).
The transition from the mated bonding method) to the COG method (ChipOn Glass method) in the flip chip method (Flip Chip Bonding method) has been made. In the COG method, a projection electrode (bump) provided on a semiconductor element is electrically connected to a wiring electrode on a glass substrate of a display panel for a liquid crystal display device.
【０００４】従来の表示パネルを図５〜図７に基づいて
説明する。従来の表示パネルは、図５に示すように、ほ
ぼ矩形状に形成されたガラス基板４の一主面上の外周部
の少なくとも一辺に、複数個のほぼ矩形状の半導体素子
６を、その長側面部６ａ方向すなわち長軸方向にほぼ一
直線状に実装している。A conventional display panel will be described with reference to FIGS. As shown in FIG. 5, a conventional display panel includes a plurality of substantially rectangular semiconductor elements 6 on at least one side of an outer peripheral portion on one main surface of a substantially rectangular glass substrate 4. It is mounted almost linearly in the direction of the side surface 6a, that is, in the long axis direction.
【０００５】図６は上記のような従来の表示パネルの製
造方法を示している。すなわち表示パネルのガラス基板
４の一主面上の外周部に形成された配線電極５のうち、
半導体素子６を実装する所定の実装部に異方性導電接着
剤７を付着させる。次いで異方性導電接着剤７上に半導
体素子６を位置合わせして配置した後、ガラス基板４の
半導体素子６の実装部の裏面側から圧着ステージ１で加
圧すると共に、半導体素子６を加熱された圧着ツール２
で加圧しながら、異方性導電接着剤７を熱圧着する。こ
の熱圧着によって、図７に示すように、異方性導電接着
剤７中の導電粒子８が、半導体素子６に予め設けた突起
電極９と、ガラス基板４上に形成した配線電極５との間
に挟まれることにより、半導体素子６と配線電極５とが
電気的に接続される。またこの際、加熱によって異方性
導電接着剤７が硬化し、半導体素子６はガラス基板４に
接着固定されることにより表示パネルを形成していた。FIG. 6 shows a method of manufacturing the above-mentioned conventional display panel. That is, of the wiring electrodes 5 formed on the outer peripheral portion on one main surface of the glass substrate 4 of the display panel,
An anisotropic conductive adhesive 7 is attached to a predetermined mounting portion on which the semiconductor element 6 is mounted. Next, after the semiconductor element 6 is aligned and arranged on the anisotropic conductive adhesive 7, the semiconductor element 6 is heated while being pressed from the back surface side of the mounting portion of the semiconductor element 6 on the glass substrate 4 by the pressure bonding stage 1. Crimping tool 2
While applying pressure, the anisotropic conductive adhesive 7 is thermocompression-bonded. As a result of the thermocompression bonding, as shown in FIG. 7, the conductive particles 8 in the anisotropic conductive adhesive 7 form the protrusion electrodes 9 provided on the semiconductor element 6 in advance and the wiring electrodes 5 formed on the glass substrate 4. The semiconductor element 6 and the wiring electrode 5 are electrically connected by being sandwiched therebetween. At this time, the anisotropic conductive adhesive 7 is cured by heating, and the semiconductor element 6 is bonded and fixed to the glass substrate 4 to form a display panel.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来例に示すような表示パネルでは、表示画面上の半導体
素子の実装部周辺に表示ムラが発生するという問題があ
った。この表示ムラの発生原因としては、上記説明した
従来の表示パネルの製造方法において、半導体素子をガ
ラス基板に実装する際に、圧着ステージと圧着ツールに
よって半導体素子およびガラス基板を熱圧着するため、
半導体素子とガラス基板の熱膨張率の違いにより、半導
体素子および半導体素子の実装部周部では、圧着ツール
の加圧方向に反りが発生し、また半導体素子の非実装部
では、その逆方向に反りが発生することにより、ガラス
基板上に波打状の変形が生じ、ガラス基板内において複
屈折を生じる結果、部分的に光の透過状態が変形し、表
示ムラが発生すると考えられる。特に、近年、半導体素
子は長寸化しているため、ガラス基板の波打状の変化に
おける振幅および周期長さが大きくなり、表示ムラの影
響が大きくなっていた。またこの表示ムラの発生原因で
ある、半導体素子とガラス基板の反りを低減するため
に、圧着ツールの加熱温度を下げる等の対策はあるが、
半導体素子の接続信頼性を確保するためには限界がある
という問題を有していた。However, in the display panel as shown in the above-mentioned conventional example, there is a problem that display unevenness occurs around the mounting portion of the semiconductor element on the display screen. As a cause of the display unevenness, in the above-described conventional method of manufacturing a display panel, when a semiconductor element is mounted on a glass substrate, the semiconductor element and the glass substrate are thermocompression-bonded by a compression stage and a compression tool.
Due to the difference in the coefficient of thermal expansion between the semiconductor element and the glass substrate, warping occurs in the pressing direction of the crimping tool at the periphery of the semiconductor element and the mounting part of the semiconductor element, and in the opposite direction at the non-mounting part of the semiconductor element. It is considered that the occurrence of the warp causes a wavy deformation on the glass substrate and the occurrence of birefringence in the glass substrate. As a result, the light transmission state is partially deformed and display unevenness occurs. In particular, in recent years, since semiconductor elements have become longer, the amplitude and the period length in the wave-like change of the glass substrate have increased, and the influence of display unevenness has increased. In addition, in order to reduce the warpage between the semiconductor element and the glass substrate, which is a cause of the display unevenness, there are measures such as lowering the heating temperature of the pressure bonding tool.
There is a problem that there is a limit in securing the connection reliability of the semiconductor element.
【０００７】本発明は、上記問題点に鑑み、熱圧着する
際に生じるガラス基板の波打状の変形の振幅や周期を極
力小さくし、実装する半導体素子の接続信頼性を確保す
ると共に、表示画面上の表示ムラを低減し、表示品位の
高い表示パネルを提供することを目的とする。SUMMARY OF THE INVENTION In view of the above problems, the present invention minimizes the amplitude and cycle of the wavy deformation of a glass substrate generated during thermocompression bonding, thereby ensuring the connection reliability of the semiconductor element to be mounted and the display. It is an object to reduce display unevenness on a screen and provide a display panel with high display quality.
【０００８】[0008]
【課題を解決するための手段】本発明は上記課題を解決
するため、ほぼ矩形状に形成されたガラス基板の一主面
上の外周部の少なくとも一辺に、複数個のほぼ矩形状の
半導体素子を、その長軸方向に千鳥状に配列されるよう
にして異方性導電接着剤を介して実装したことを特徴と
する。According to the present invention, a plurality of substantially rectangular semiconductor elements are provided on at least one side of an outer peripheral portion on one principal surface of a substantially rectangular glass substrate. Are mounted via an anisotropic conductive adhesive so as to be arranged in a staggered manner in the longitudinal direction.
【０００９】本発明によれば、ガラス基板の所定の実装
部に、複数個の半導体素子を、その長軸方向に所定間隔
でほぼ一直線状に配列すると共に、この配列した複数個
の半導体素子から、その短軸方向に所定間隔の位置に、
前記と同様な複数個の半導体素子を、その長軸方向に配
列し、なおかつ、この２列にほぼ平行に配列した複数個
の半導体素子が、その短軸方向に交互に存在するように
配置して、すなわち千鳥状（２列の場合について説明し
たが、３列以上でもよい。）に配置して、ガラス基板と
半導体素子の間に異方性導電接着剤を介して、熱圧着に
より実装することにより表示パネルを形成している。表
示パネルの製造方法において、半導体素子をガラス基板
に実装する際に、熱圧着を利用するため、ガラス基板の
半導体素子の実装部周辺に波打状の変形が生ずるが、半
導体素子を千鳥状に配置することにより、熱圧着する際
にガラス基板の半導体素子の実装部と非実装部での反り
が逆方向に生じることを利用して、２列（又は３列以
上）に配列した各半導体素子の実装部周辺から、各列各
々に波打状の変形を形成させ、互いの波を打ち消し合う
ことにより、ガラス基板に生じる波打状の変形の振幅や
周期を小さくすることができる。これにより、ガラス基
板に生じる屈折を和らげ、その透過状態を良好なものと
することができる結果、表示ムラを低減した表示品位の
高い表示パネルを得ることができる。According to the present invention, a plurality of semiconductor elements are arranged on a predetermined mounting portion of a glass substrate in a substantially linear manner at a predetermined interval in a longitudinal direction of the glass element. , At positions at predetermined intervals in the short axis direction,
A plurality of semiconductor elements similar to those described above are arranged in the major axis direction, and a plurality of semiconductor elements arranged substantially parallel to the two rows are arranged so as to be alternately arranged in the minor axis direction. That is, they are arranged in a zigzag pattern (two rows are described, but three or more rows may be arranged), and mounted by thermocompression bonding between a glass substrate and a semiconductor element via an anisotropic conductive adhesive. Thus, a display panel is formed. In the method of manufacturing a display panel, when a semiconductor element is mounted on a glass substrate, thermocompression bonding is used, so that a wavy deformation occurs around the mounting portion of the semiconductor element on the glass substrate, but the semiconductor elements are staggered. Each semiconductor element is arranged in two rows (or three or more rows) by utilizing the fact that warping occurs in the mounting part and the non-mounting part of the semiconductor element of the glass substrate in the opposite direction during thermocompression bonding. By forming a wavy deformation in each of the rows from the vicinity of the mounting portion, and canceling each other's waves, the amplitude and period of the wavy deformation generated in the glass substrate can be reduced. As a result, refraction generated in the glass substrate can be reduced, and the transmission state can be improved. As a result, a display panel with reduced display unevenness and high display quality can be obtained.
【００１０】[0010]
【発明の実施の形態】以下に本発明の実施形態を図１〜
図４に基づいて詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.
This will be described in detail with reference to FIG.
【００１１】本実施形態の表示パネルは、液晶表示装置
用のものを用いており、図１に示すように、ガラス基板
１４の一主面上の外周部の少なくとも一辺に、複数個の
液晶表示駆動用ＬＳＩである半導体素子１１、１２を実
装して形成されている。The display panel of the present embodiment is used for a liquid crystal display device. As shown in FIG. 1, a plurality of liquid crystal display devices are provided on at least one side of an outer peripheral portion on one main surface of a glass substrate 14. It is formed by mounting semiconductor elements 11 and 12, which are driving LSIs.
【００１２】前記ガラス基板１４は、ほぼ矩形状に形成
されており、この一主面上の外周部の少なくとも一辺
に、半導体素子１１、１２の実装部であって、アルミニ
ウム（Ａｌ）により形成された配線電極１６を備えてい
る。The glass substrate 14 is formed in a substantially rectangular shape. At least one side of an outer peripheral portion on one main surface of the glass substrate 14 is a mounting portion of the semiconductor elements 11 and 12 and is formed of aluminum (Al). Wiring electrodes 16 are provided.
【００１３】前記半導体素子１１、１２は、ほぼ矩形状
に形成されており、配線電極１６との接続部には予め、
金（Ａｕ）により形成された突起電極１５を備えてい
る。また本実施形態の半導体素子１１、１２は同様のも
のであり、その寸法は長側面部１１ａが１６ｍｍ、短側
面部１１ｂが２ｍｍのものを用いた。The semiconductor elements 11 and 12 are formed in a substantially rectangular shape.
A protruding electrode 15 made of gold (Au) is provided. The semiconductor elements 11 and 12 of the present embodiment are the same, and the dimensions of the semiconductor elements 11 and 12 are 16 mm for the long side surface 11a and 2 mm for the short side surface 11b.
【００１４】本実施形態における半導体素子１１、１２
の配置については、ガラス基板１４の所定の実装部に、
複数個の半導体素子１１を、その長側面部１１ａ方向、
すなわち長軸方向に所定間隔でほぼ一直線状に配列する
と共に、この配列した複数個の半導体素子１１から、そ
の短側面部１１ｂ方向、すなわち短軸方向に所定間隔の
位置に、前記と同様な複数個の半導体素子１２を、その
長軸方向に配列し、なおかつ、この２列に平行に配列し
た複数個の半導体素子１１、１２が、その短軸方向に交
互に存在するように配置している。より具体的には、第
１列目に配列した隣り合う半導体素子１１の隙間を、第
２列目に配列した半導体素子１２の長さと同一（１６ｍ
ｍ）とし、側方（短軸方向）から見たとき、第１列目と
第２列目の半導体素子１１、１２が連続して見えるよう
に千鳥状に配置している。また第１列目と第２列目との
半導体素子１１、１２の短軸方向の隙間を３ｍｍとして
いる。The semiconductor elements 11 and 12 in the present embodiment
About the arrangement of, in a predetermined mounting portion of the glass substrate 14,
A plurality of semiconductor elements 11 are arranged in the direction of the long side surface 11a,
That is, the semiconductor elements 11 are arranged substantially linearly at a predetermined interval in the long axis direction, and a plurality of the same semiconductor elements 11 are arranged in a direction of the short side surface portion 11b, that is, at a predetermined interval in the short axis direction. The semiconductor elements 12 are arranged in the long axis direction, and the plurality of semiconductor elements 11 and 12 arranged in parallel with the two rows are arranged so as to be alternately arranged in the short axis direction. . More specifically, the gap between adjacent semiconductor elements 11 arranged in the first column is equal to the length of semiconductor elements 12 arranged in the second column (16 m).
m), and the semiconductor elements 11 and 12 in the first and second rows are arranged in a staggered manner so as to be seen continuously when viewed from the side (the short axis direction). The gap in the short axis direction between the semiconductor elements 11 and 12 between the first row and the second row is 3 mm.
【００１５】なお、千鳥状に配置した複数個の半導体素
子１１、１２において、効果的な配置位置としては、各
列に配列した長軸方向に隣り合う半導体素子１１、１２
の隙間を、前記半導体素子１１の短側面部１１ｂの長さ
から、長側面部１１ａの長さに至る範囲になるように配
置する。また第１列目に配列した所定の半導体素子１１
と、第２列目に配列した所定の半導体素子１２との短軸
方向における隙間を、前記半導体素子１１の短側面部１
１ｂの長さから、その倍の長さに至る範囲になるよう
に、各半導体素子１１、１２をガラス基板１４に配置す
る。In the plurality of semiconductor elements 11 and 12 arranged in a staggered manner, the effective arrangement positions are the semiconductor elements 11 and 12 adjacent to each other in the long axis direction arranged in each row.
Are arranged in a range from the length of the short side surface portion 11b of the semiconductor element 11 to the length of the long side surface portion 11a. The predetermined semiconductor elements 11 arranged in the first column
And a gap in the short axis direction between the semiconductor element 12 and the predetermined semiconductor element 12 arranged in the second row,
Each of the semiconductor elements 11 and 12 is arranged on the glass substrate 14 so as to have a range from the length of 1b to twice as long.
【００１６】次に本実施形態の表示パネルの製造方法を
図２に基づいて説明する。Next, a method for manufacturing a display panel according to this embodiment will be described with reference to FIG.
【００１７】予めガラス基板１４の実装部に、異方性導
電接着剤１３を付着させ、次いで異方性導電接着剤１３
上に半導体素子１１、１２を位置合わせするように配置
した後、ガラス基板１４の実装部の裏面側から圧着ステ
ージ２１で加圧すると共に、半導体素子１１、１２を加
熱された圧着ツール２２で加圧しながら熱圧着する。こ
の熱圧着によって、図３に示すように、異方性導電接着
剤１３中の導電粒子１７が、半導体素子１１、１２に設
けた突起電極１５と、ガラス基板１４上の配線電極１６
との間に挟まれることにより、半導体素子１１、１２と
配線電極１６が電気的に接続される。またこの際、加熱
によって異方性導電接着剤１３が硬化し、半導体素子１
１、１２はガラス基板１４に接着固定され、図４に示す
ように半導体素子１１、１２がガラス基板１４に実装さ
れ、表示パネルを形成することができる。The anisotropic conductive adhesive 13 is attached to the mounting portion of the glass substrate 14 in advance, and then the anisotropic conductive adhesive 13
After the semiconductor elements 11 and 12 are arranged so as to be aligned, the pressure is applied from the back side of the mounting portion of the glass substrate 14 by the pressure bonding stage 21 and the semiconductor elements 11 and 12 are pressed by the heated pressure bonding tool 22. Thermocompression bonding. As a result of this thermocompression bonding, as shown in FIG. 3, the conductive particles 17 in the anisotropic conductive adhesive 13 are separated from the projecting electrodes 15 provided on the semiconductor elements 11 and 12 and the wiring electrodes 16 on the glass substrate 14.
The semiconductor elements 11 and 12 are electrically connected to the wiring electrode 16 by being sandwiched between the first and second semiconductor devices. At this time, the anisotropic conductive adhesive 13 is cured by heating, and the semiconductor element 1
The substrates 1 and 12 are bonded and fixed to a glass substrate 14, and the semiconductor elements 11 and 12 are mounted on the glass substrate 14 as shown in FIG. 4 to form a display panel.
【００１８】また、半導体素子１１、１２をガラス基板
１４の所定の実装部に千鳥状に配置する手順としては、
両列の半導体素子１１、１２を同時に配置しても良く、
またはいずれか一方の列の半導体素子、例えば半導体素
子１１を先に所定の実装部に、その長軸方向に所定間隔
でほぼ一直線状に配列し、次いで他方の列の半導体素子
１２を所定の実装部に、前記と同様に配列しても良い。The procedure for arranging the semiconductor elements 11 and 12 on a predetermined mounting portion of the glass substrate 14 in a staggered manner is as follows.
The semiconductor elements 11 and 12 in both rows may be arranged at the same time,
Alternatively, one of the rows of semiconductor elements, for example, the semiconductor element 11 is first arranged on a predetermined mounting portion in a substantially linear manner at a predetermined interval in the longitudinal direction thereof, and then the other row of semiconductor elements 12 is mounted on a predetermined mounting section. It may be arranged in the same manner as above.
【００１９】このように、本実施形態の表示パネルにお
いては、半導体素子１１、１２をガラス基板１４の所定
の実装部に熱圧着を用いて実装する際に、半導体素子１
１、１２を千鳥状に配置することにより、ガラス基板１
４の半導体素子１１、１２の実装部と非実装部での反り
が逆方向に生じることを利用して、２列に配列した各半
導体素子１１、１２の実装部周辺から、各列各々に波打
状の変形を生じさせ、互いの波を打ち消し合うことによ
り、ガラス基板１４に生じる波打状の変形の振幅や周期
を極力小さくすることができる。これにより、ガラス基
板１４に生じる屈折を和らげ、その透過状態を良好なも
のとなる結果、表示ムラを低減した表示品位の高い表示
パネルを得ることができる。本実施形態の表示パネル
は、特に大画面化した場合において有効であって、この
表示パネルを搭載した液晶表示装置、および前記液晶表
示装置を搭載した画像表示機器は産業的価値の高い。As described above, in the display panel of the present embodiment, when the semiconductor elements 11 and 12 are mounted on a predetermined mounting portion of the glass substrate 14 by thermocompression bonding, the semiconductor element 1
By arranging 1 and 12 in a staggered manner, the glass substrate 1
Utilizing the fact that the warpage occurs in the mounting part and the non-mounting part of the semiconductor elements 11 and 12 in the opposite directions, a wave is applied to each row from the vicinity of the mounting parts of the semiconductor elements 11 and 12 arranged in two rows. By generating the hitting deformation and canceling each other's waves, the amplitude and the period of the hitting deformation generated on the glass substrate 14 can be minimized. As a result, the refraction generated in the glass substrate 14 is reduced, and the transmission state thereof is improved. As a result, a display panel with high display quality and reduced display unevenness can be obtained. The display panel of the present embodiment is particularly effective when the screen is enlarged, and a liquid crystal display device equipped with the display panel and an image display device equipped with the liquid crystal display device have high industrial value.
【００２０】なお本発明は上記実施形態に示すほか、種
々の形態に構成することができる。例えば、表示パネル
を液晶表示装置に用いた場合について説明したが、ＰＤ
Ｐパネル等の他の表示デバイスでも、本発明の表示パネ
ルを用いることで、同様の効果が得られる。また、図４
に示すように、長軸方向に隣り合う半導体素子１１およ
び半導体素子１２の隙間を５ｍｍに、各列に配列した短
軸方向における所定の半導体素子１１と半導体素子１２
との隙間を２ｍｍに配置することにより、半導体素子１
１、１２の長軸方向における反りを、より和らげるよう
に形成しても良い。The present invention can be configured in various forms other than the above embodiment. For example, the case where the display panel is used for a liquid crystal display device has been described.
The same effect can be obtained with other display devices such as a P panel by using the display panel of the present invention. FIG.
As shown in FIG. 3, the gap between the semiconductor elements 11 and 12 adjacent to each other in the long axis direction is set to 5 mm, and the predetermined semiconductor elements 11 and 12 in the short axis direction are arranged in each row.
Is arranged at a distance of 2 mm, the semiconductor element 1
The warp in the long axis direction of 1 and 12 may be formed to be further reduced.
【００２１】[0021]
【発明の効果】本発明によれば、表示パネルに実装する
半導体素子の接続信頼性を確保すると共に、表示画面上
の表示ムラを低減し、表示品位の高い表示パネルを提供
することができる。According to the present invention, it is possible to provide a display panel having high display quality while ensuring the connection reliability of the semiconductor element mounted on the display panel, reducing display unevenness on the display screen.
【図１】本発明の実施形態の表示パネルを示す平面図。FIG. 1 is a plan view showing a display panel according to an embodiment of the present invention.
【図２】本発明の実施形態の表示パネルの製造方法を示
す斜視図。FIG. 2 is a perspective view showing a method for manufacturing a display panel according to the embodiment of the present invention.
【図３】本発明の実施形態の表示パネルを示す構造断面
図。FIG. 3 is a structural cross-sectional view showing a display panel according to the embodiment of the present invention.
【図４】本発明の他の実施形態の表示パネルを示す平面
図。FIG. 4 is a plan view showing a display panel according to another embodiment of the present invention.
【図５】従来の表示パネルを示す平面図。FIG. 5 is a plan view showing a conventional display panel.
【図６】従来の表示パネルの製造方法を示す斜視図。FIG. 6 is a perspective view showing a conventional display panel manufacturing method.
【図７】従来の表示パネルを示す構造断面図。FIG. 7 is a structural sectional view showing a conventional display panel.
１１ 半導体素子 １１ａ 長側面部 １１ｂ 短側面部 １２ 半導体素子 １４ ガラス基板 DESCRIPTION OF SYMBOLS 11 Semiconductor element 11a Long side part 11b Short side part 12 Semiconductor element 14 Glass substrate
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 2H092 GA48 GA60 HA12 HA25 MA32 NA01 PA06 5F044 KK06 LL09 5G435 AA00 AA16 BB12 EE33 EE37 EE42 GG21 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA48 GA60 HA12 HA25 MA32 NA01 PA06 5F044 KK06 LL09 5G435 AA00 AA16 BB12 EE33 EE37 EE42 GG21
Claims (4)
主面上の外周部の少なくとも一辺に、複数個のほぼ矩形
状の半導体素子を、その長軸方向に千鳥状に配列される
ようにして異方性導電接着剤を介して実装したことを特
徴とする表示パネル。A plurality of substantially rectangular semiconductor elements are arranged on at least one side of an outer peripheral portion on one principal surface of a substantially rectangular glass substrate so as to be staggered in a longitudinal direction thereof. And a display panel mounted via an anisotropic conductive adhesive.
おいて、その長軸方向の隙間を、前記半導体素子の短側
面部の長さから長側面部の長さに至る範囲の長さとし、
かつその短軸方向の隙間を、前記半導体素子の短側面部
の長さからその倍の長さに至る範囲の長さとしたことを
特徴とする請求項１記載の表示パネル。2. In a plurality of semiconductor elements arranged in a staggered manner, a gap in a long axis direction is set to a length ranging from a length of a short side portion to a length of a long side portion of the semiconductor element.
2. The display panel according to claim 1, wherein the gap in the short axis direction has a length ranging from the length of the short side surface portion of the semiconductor element to a length twice as long.
したことを特徴とする液晶表示装置。3. A liquid crystal display device comprising the display panel according to claim 1.
ことを特徴とする画像表示機器。4. An image display device comprising the liquid crystal display device according to claim 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000066672A JP2001255832A (en) | 2000-03-10 | 2000-03-10 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000066672A JP2001255832A (en) | 2000-03-10 | 2000-03-10 | Display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001255832A true JP2001255832A (en) | 2001-09-21 |
Family
ID=18585994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000066672A Pending JP2001255832A (en) | 2000-03-10 | 2000-03-10 | Display panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001255832A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100453306B1 (en) * | 2001-02-13 | 2004-10-20 | 샤프 가부시키가이샤 | Display element driving apparatus and display using the same |
-
2000
- 2000-03-10 JP JP2000066672A patent/JP2001255832A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100453306B1 (en) * | 2001-02-13 | 2004-10-20 | 샤프 가부시키가이샤 | Display element driving apparatus and display using the same |
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