JP2001255546A - Liquid crystal device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent connection failures between the input/output terminal of a liquid crystal panel and a FPC in an electronic appliance, which uses a liquid crystal device. SOLUTION: The input/output terminal 8 is constituted by forming respectively conductive layers 81a, 81b, an indium tin oxide layer 4 on the conductive layers 81a, 81b, and an indium-tin alloy surface layer 4a through reduction treatment of the surface of the indium tin oxide layer. By forming the indium-tin alloy layer 4a having the eutectic point lower than the heating and press-fixing temperature between the input/output terminal 8 and the FPC 9 as the uppermost layer of the input/output terminal 8, the input/output terminal 8 and the metal lead 42 of the FPC 9 can be press-fixed by heating without having to use an adhesive.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal device, and more particularly to a means for preventing a connection failure of an input / output terminal of an active matrix substrate.

[0002]

2. Description of the Related Art In recent years, large-capacity matrix liquid crystal devices have been used for personal computer displays and the like. Among them, as high-quality, large-capacity liquid crystal display device,
An active matrix type liquid crystal display device in which a thin film element having a switching function is introduced between a pixel electrode and a signal wiring is mainly used. The active matrix substrates of these active matrix type liquid crystal display devices include:
A thin film transistor (ThinFilm T) is used as a pixel switching element or a switching element constituting a driving circuit.
ransistor: hereinafter abbreviated as TFT). In order to improve the withstand voltage of the TFT or reduce the off-leak current in the active matrix substrate, a technique of using the TFT with an offset gate structure or an LDD structure is often used.

An active matrix substrate has the above-mentioned TFT.
In addition, an input / output terminal for exchanging a signal current with the TFT is provided. The flexible printed circuit board (Frexible Print Cercuit: hereafter, FPC)
) Is connected, and exchanges signals with external devices. FIG. 13 schematically shows an FPC, and FIG. 13A is a perspective view showing an appearance of the FPC.
FIG. 13B is a cross-sectional view of the terminal portion of the FPC. FPC9
Is formed by arranging a plurality of metal conductors 42 made of copper or the like in parallel, and surrounding them collectively with an insulating synthetic resin layer 41, and is configured to be flat and flexible as a whole. . Then, at the connection portion at the end of the FPC 9, FIG.
As shown in FIG. 3B, the synthetic resin layer 41 on the lower surface of the metal conductor 42 is peeled off, and an adhesive tape 45 in which metal particles 43 such as copper are dispersed in an adhesive 44 is attached.

FIG. 14 shows a state in which the FPC thus configured is mounted on the active matrix substrate 2. FIG. 14A shows an active matrix substrate 102.
3 is a cross-sectional view of the input / output terminal section of FIG. I / O terminal 108
FIG. 14 is a cross-sectional view showing a state in which the FPC 9 is connected to FIG.
(B). When the metal conductor 42 of the FPC 9 is superimposed on a predetermined input / output terminal 108 on the active matrix substrate 102 and heated and pressed at a heating temperature of about 150 ° C., FP
The adhesive 44 of C9 softens and flows due to heat, and the input / output terminals 108 on the active matrix substrate 102 and the FP
The metal wire 42 of C9 comes into contact with the metal particles 43. If a sufficient number of metal particles 43 are completely in contact,
The contact resistance between the input / output terminal 108 and the metal conductor 42 of the FPC 9 is reduced, and good bonding can be achieved.

[0005]

However, the input / output terminals 108 on the active matrix substrate 102 and the FPC 9
Of the input / output terminal 10
8 and the metal conductor 42, the adhesive 44 loses its escape space and remains on the input / output terminal 108, or the adhesive 44 is pressed from a portion adjacent to the input / output terminal 108, and If the adhesive 44, which is an insulator, enters between the particles 43 or between the metal conductive wire 42 and the metal particles 43, there is a problem that the contact resistance is increased or insulation failure is caused. Further, if a large amount of metal particles 43 enter between adjacent input / output terminals 108, there is a possibility that the input / output terminals 108 may be short-circuited. The present invention has been made in view of the above circumstances.
An object of the present invention is to prevent a connection failure at an input / output terminal portion when mounting the PC 9.

[0006]

According to the present invention, there is provided a liquid crystal device comprising: a plurality of scanning lines and a plurality of data lines formed in a matrix on a substrate; What is claimed is: 1. A liquid crystal device comprising: connected switching means, a pixel electrode connected to the switching element, and an input / output terminal, wherein the input / output terminal includes a conductive layer, and indium tin formed on the conductive layer. An oxide layer;
It is characterized by comprising an indium-tin alloy surface layer obtained by reducing the surface of the indium tin oxide layer. According to the present invention, since the surface layer of the input / output terminal is made of an indium-tin alloy, the input / output terminal and the metal conductor of the FPC are firmly joined by heat compression without using an adhesive. can do. In addition, it is preferable that a peripheral portion of the input / output terminal is covered with a transparent insulating film. Specifically, the upper surface of the transparent insulating film is higher than the upper surface of the input / output terminal, and An opening without a membrane,
An indium tin oxide layer is formed on the inner wall of the transparent insulating film and the upper surface of the input / output terminal in the opening, and the surface of the indium tin oxide layer is reduced to form an indium-tin alloy surface layer. A configuration is preferably employed. By providing such a transparent insulating film around the input / output terminals, it is possible to protect the periphery of the input / output terminals in the mounting process, and to prevent debris of insulating material from adhering to the input / output terminals. And an effect of preventing poor connection between the FPC and the FPC. The liquid crystal device after mounting, in which a metal conductor of an FPC is bonded to the upper surface of the input / output terminal by heat compression, is also included in the liquid crystal device of the present invention. In addition, if a coating layer made of an indium-tin alloy is formed on the surface of the metal conductor of the FPC to be joined to the input / output terminal before joining with the input / output terminal, the joining between the input / output terminal and the metal conductor is made possible. In this case, the indium-tin alloy is heated and pressed together, so that the bonding strength is improved and the contact resistance is reduced. Alternatively, it is also possible to join the I / O terminal and the metal conductor of the FPC with an adhesive containing metal particles interposed therebetween. In this case, if a coating layer made of an indium-tin alloy is formed on the surface of the metal particles in the adhesive, the indium-tin alloy is heat-pressed between the input / output terminals and the metal particles. Strength is improved and contact resistance is reduced.
Furthermore, if a coating layer made of an indium-tin alloy is formed on the surface of the metal conductor of the FPC that is to be joined to the input / output terminal, the indium-tin alloy can be heated and pressed even when joining the metal particles and the metal conductor. Therefore, the bonding strength can be further improved, and the contact resistance can be further reduced.
Further, in the method of manufacturing a liquid crystal device according to the present invention, means for forming the input / output terminals and the transparent insulating film around the input / output terminal portions simultaneously with the formation of the TFTs on the active matrix substrate is employed. According to this manufacturing method, the input / output terminals and the transparent insulating film can be formed without increasing the number of special steps, so that the liquid crystal device of the present invention can be manufactured without lowering the production efficiency.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a block diagram schematically illustrating a configuration of an active matrix substrate in the liquid crystal device of the present embodiment. As shown in FIG. 10, data lines 90 and scanning lines 91 are formed on the active matrix substrate 2. The scanning line 91 is connected to the gate of the pixel TFT 10 connected to the pixel electrode in each pixel, and the data line 90 is connected to the source of the pixel TFT 10. Each pixel has a liquid crystal cell 94 to which an image signal is input via the pixel TFT 10. Data line 9
For 0, the shift register 48 and the level shifter 8
5, a data line driving circuit 60 including a video line 87 and an analog switch 86 is formed on the active matrix substrate 2. For the scanning line 91, a scanning line driving circuit 70 including a shift register 88 and a level shifter 89 is formed on the active matrix substrate 2.

The scanning line driving circuit 70 and the data line driving circuit 60 are composed of an N-type driving circuit TFT and a P-type driving circuit.
It is constituted by a TFT for a driving circuit of a type. These T
The FT employs an LDD structure. Each pixel has a storage capacitor 40 (capacitance element) between the capacitance line 92 and the gate electrode.
May be formed, and the storage capacitor 40 has a function of improving the charge retention characteristics of the liquid crystal cell 94.
Incidentally, the storage capacitor 40 may be formed between the scanning line 91 and the preceding stage.

The active matrix substrate 2 thus configured constitutes the liquid crystal device of the present embodiment as shown in FIGS. FIG. 11 and FIG. 12 are a plan view of the liquid crystal device and a cross-sectional view thereof along the line HH ′, respectively. The liquid crystal device 1 has a schematic configuration in which a counter substrate 3 is disposed so as to face the active matrix substrate 2, and a liquid crystal 6 is sealed and sandwiched between these substrates 2 and 3. The opposing substrate 3 is configured by forming an opposing electrode 71 and a matrix-shaped light-shielding film 98 for separating a display area on a transparent insulating substrate 300 such as a quartz substrate or a high heat-resistant glass substrate. The active matrix substrate 2 and the counter substrate 3 are bonded to each other with a predetermined gap by a seal layer 80 using a seal material containing a gap material. As the seal layer 80, a seal material containing an inorganic or organic fiber or sphere of about 2 μm to about 10 μm as a gap material in an epoxy resin or various ultraviolet curable resins can be used.

The area of the opposing substrate 3 is smaller than the area of the active matrix substrate 2, and the peripheral portion of the active matrix substrate 2 is bonded so as to protrude from the outer peripheral edge of the opposing substrate 3. On the active matrix substrate 2 outside the opposing substrate 3, the scanning line driving circuit 70, the data line driving circuit 60, the input / output terminal 8, and the scanning line driving circuit 70 and the data line driving circuit 60 are connected to the input / output terminal 8.
A routing wiring 75 for connection to the terminal is provided. A flexible printed circuit board 9 is connected to the input / output terminals 8 by wiring. The seal layer 80 is partially interrupted, and the interrupted portion serves as a liquid crystal injection port 83. Therefore, after the opposing substrate 3 and the active matrix substrate 2 are bonded to each other, the pressure inside the seal layer 80 is reduced by injecting the liquid crystal 6 from the liquid crystal inlet 83 into the seal layer 80 by reducing the pressure inside the seal layer 80. it can. Liquid crystal inlet 8
3 is sealed with a sealant 82 after sealing the liquid crystal 6. Note that reference numeral 100 in FIG. 12 denotes a pixel electrode.

FIG. 1 is an enlarged plan view showing the periphery of the input / output terminal 8 and the routing wiring 75 in the present embodiment, and FIG. 2 is a cross-sectional view taken along line AA 'in FIG. FIG. 3 and FIG. 3 are cross-sectional views along the line BB ′ in FIG. 2 and 3, reference numeral 14 denotes an insulating film made of silicon oxide. The input / output terminals 8 are arranged at one end of the active matrix substrate 2, and are routed from each of the input / output terminals 8.
5 extends to the scanning line driving circuit 70 and the data line driving circuit 60. In the present embodiment, the peripheral portions of the input / output terminals 8 of the active matrix substrate 2 and the routing wiring 75 are covered with a transparent insulating film 403. Transparent insulating film 4
Numeral 03 is formed so as to cover the peripheral portion 28 of the routing wiring 75, and is also formed on the routing wiring 75 as shown in FIG.

As shown in FIG. 3, the input / output terminal 8
A first conductive layer 81a provided on an insulating film 14 made of silicon oxide, and a second conductive layer 81 provided thereon;
b, an indium tin oxide layer 4 (hereinafter referred to as an ITO (Indium Tin Oxide) layer) provided thereon, and an indium-tin alloy surface layer 4 a (hereinafter referred to as Indium Tin Oxide) formed on the surface portion of the ITO layer 4. -Sn alloy surface layer). A transparent insulating film 403 is provided between adjacent input / output terminals 8, and the upper surface of the transparent insulating film 403 is higher than the upper surface of the input / output terminal 8.
Is formed thick. There is no transparent insulating film 403 on the input / output terminal 8, which is an opening 84 of the transparent insulating film 403. The transparent insulating film 403 in the opening 84
Of the I / O terminal 8 and the upper surface of the input / output terminal 8 are covered with an ITO layer 4, and the surface portion is an In-Sn alloy surface layer 4a. The In-Sn alloy surface layer 4a is formed of the ITO layer 4
Formed by reducing the surface portion of
It is formed on the entire surface of the O layer 4. Although the thickness of the In-Sn alloy surface layer 4a can be arbitrarily designed, as described later, the input / output terminal 8 and the metal conductor 42 of the FPC 9 are joined via the In-Sn alloy surface layer 4a. At this time, the bonding strength increases as the thickness of the In-Sn alloy surface layer 4a increases. However, if the entire ITO layer 4 is reduced, an insulating material such as an oxide is easily generated at the interface between the second conductive layer 81b and the ITO layer 4, so that at least the upper surface of the second conductive layer 81b is formed. Has a configuration in which the ITO layer 4 is in contact.

The transparent resin used for the transparent insulating film 403 is not particularly limited as long as it is a transparent and insulating material such as an acrylic resin, a polyamide resin, a polyimide resin, and a phenol resin. A flattening film or the same film as an interlayer insulating film formed at the time of manufacturing a thin film transistor on the active matrix substrate 2 can be used as a transparent insulating film. In the present embodiment, the formation of the input / output terminal 8 is
Since it was performed at the same time as the formation of T, the first conductive layer 81a made of the same material as the gate electrode of the TFT and the second conductive layer 81b made of the same material as the source / drain electrodes were used as the conductive layer of the input / output terminal 8. It has two layers. In FIG. 3, reference numeral 401 denotes a lower interlayer insulating film, and 402 denotes an upper interlayer insulating film, both of which are formed because the input / output terminals 8 were formed simultaneously with the formation of the TFT. In addition, the opening 84 of the transparent insulating film 403 is widened toward the top and is in the shape of a mortar.

Next, a method for manufacturing the liquid crystal device of the present embodiment will be described. In the present embodiment, the input / output terminals 8 and the transparent insulating film 403 are formed simultaneously with the formation of the TFT in accordance with the manufacturing process of the TFT of the active matrix substrate 2 as follows. 4 to 6 are cross-sectional views illustrating a method of manufacturing the liquid crystal device according to the present embodiment in the order of steps. Here, an example of an active matrix substrate including three types of TFTs will be described. For example, the active matrix substrate 2 of the liquid crystal device shown in FIG. 10 includes an N-type pixel switching TFT having an LDD structure, an N-type drive circuit TFT having an LDD structure, and a P-type drive circuit having a self-aligned structure. For TF
Three types of TFTs T are provided. In the following description, each impurity concentration is represented by the impurity concentration after activation annealing.

First, as shown in FIG. 4A, a base protective film 201 made of a silicon oxide film is formed on a surface of an insulating substrate 200 made of a quartz substrate, a glass substrate, or the like. Next, the amorphous silicon film 20 is formed using a CVD method or the like.
After forming 2, crystal grains are grown by laser annealing or rapid heating to form a polysilicon film. In the case of N type, phosphorus ions are implanted.

Next, as shown in FIG. 4B, the polysilicon film is patterned by photolithography to form a pixel TFT, an N-type drive circuit TFT, and a P-type drive circuit TFT. Island-like silicon film 1 in region
Leave 0a, 20a and 30a.

Next, TEOS-CVD method, plasma CV
An insulating film 14 made of a silicon oxide film having a thickness of about 30 nm to about 200 nm is formed on the entire surface of the silicon film by a method D, a thermal oxidation method, or the like (first gate insulating film forming step).
Here, when the insulating film 14 is formed by using the thermal oxidation method, the silicon films 10a, 20a, and 30a are also crystallized in this step, and these silicon films can be used as a polysilicon film. is there. When performing channel doping,
For example, at this timing, boron ions are implanted at a dose of about 1 × 10 ¹² cm ⁻² . As a result, the silicon films 10a, 20a, 30a have an impurity concentration of about 1 × 10 ¹⁷
It becomes a low-concentration P-type silicon film of cm ⁻³ .

Next, as shown in FIG.
A conductive film 150 for forming a gate electrode, such as a doped silicon, a silicide film, a metal film such as an aluminum film, a chromium film, or a tantalum film, is formed on the entire surface of the substrate 4. The thickness of the conductive film 150 for forming the gate electrode is approximately 200 nm.
It is about. Next, a patterning mask 551 is formed on the surface of the gate electrode forming conductive film 150, and patterning is performed in this state, and a gate electrode 35 is formed on the drive circuit TFT side as shown in FIG. Form (first
Gate electrode forming step). At this time, the N-type pixel TF
On the side of the T and N-type driver circuit TFTs, the conductive film 150 for forming a gate electrode is covered with the mask 551 for patterning, so that the conductive film 150 for forming a gate electrode is not patterned. Also, the input / output terminal formation region is not patterned.

Next, as shown in FIG. 4E, the gate electrode 35 on the side of the TFT for the P-type driving circuit and the TFT on the side of the TFT for the N-type pixel and the TFT for the N-type driving circuit are left. Using the conductive film 150 for forming a gate electrode as a mask, boron ions (second conductivity type / P type) are ion-implanted at a dose (high concentration) of about 1 × 10 ¹⁵ cm ⁻² (doping of high concentration second conductivity type impurities). Process). As a result, the impurity concentration becomes 1 × 10 ²⁰ c
Source / drain regions 31 and 32 having a high concentration of m ⁻³ are formed in self-alignment with the gate electrode 35. Here, the portion covered with the gate electrode 35 becomes the channel formation region 33.

Next, as shown in FIG. 5A, the P-type driving circuit TFT is completely covered, and the N-type pixel TFT and the N-type driving circuit TFT side gate are completely covered. A patterning mask 552 made of a resist mask covering an electrode formation region is formed. At this time, the input / output terminals 8
A patterning mask 553 made of a resist mask that covers the formation region of is formed.

Next, as shown in FIG. 5B, the conductive film 150 for forming the gate electrode is patterned using the patterning masks 552 and 553, and the N-type pixel TFT is formed.
And gate electrodes 15 and 25 of N-type drive circuit TFT
Then, a first conductive layer 81a for the input / output terminal 8 is formed (second gate electrode forming step, see FIG. 5C). At the time of this patterning, a patterning mask 552,
Lateral etching (side etching) occurs in the gate electrode forming conductive film 150 covered with 553. For this reason, the gate electrodes 15, 25 and the first conductive layer 81a of the input / output terminal 8 are patterned masks 552, 55.
It becomes smaller in both the width direction and the length direction than 3. In the second gate electrode forming step, from the viewpoint of actively performing side etching on the gate electrode forming conductive film 150, the second gate electrode forming step includes wet etching, plasma etching, and the like. An isotropic etching method is preferred.

Next, patterning masks 552 and 55
3 and leave phosphorus ion (1st conductivity type / N type)
Ion implantation is performed at a dose (high concentration) of 10 ¹⁵ cm ^-2 (first high concentration first conductivity type impurity introduction step). As a result, impurities are introduced into the patterning mask 552 in a self-aligned manner, and high-concentration source / drain regions 112, 122, 212, 222 are formed in 10a, 20a. Here, a region of the silicon films 10a and 20a where high-concentration phosphorus is not introduced is the gate electrode 1
It is wider than the area covered by 5, 25. That is, the gate electrodes 15, 25 of the silicon films 10a, 20a
Are formed between the high-concentration source / drain regions 112, 122, 212 and 222 on both sides of the region opposite to the region 111, 121, 211 and 221 where high-concentration phosphorus is not introduced.

Next, as shown in FIG. 5C, the patterning masks 552 and 553 are removed, and in this state, phosphorus ions are implanted at a dose (low concentration) of 1 × 10 ¹³ cm ⁻² (low concentration) (FIG. 5C). Low concentration first conductivity type impurity introduction step). As a result, the gate electrodes 1 are formed on the silicon films 10a and 20a.
Low-concentration impurities are introduced into the low-concentration source / drain regions 111 and 12 in a self-alignment manner with respect to 5 and 25.
1, 211 and 221 are formed. The gate electrode 1
Channel formation regions 13 and 23 are provided in regions overlapping with regions 5 and 25.
Is formed.

Next, as shown in FIG. 5D, a lower interlayer insulating film 401 is formed on the surface side of the gate electrodes 15, 25, 35 and the input / output terminals 8, and then patterned by photolithography. Contact holes are formed at predetermined source electrode positions, drain electrode positions, and input / output terminal positions. Next, the source electrode 1 is formed from above using a metal film such as an aluminum film, a chromium film, or a tantalum film.
6, 26, 36, a drain electrode 17, 27, and a conductive film 160 for source / drain formation to be a second conductive layer 81b of the input / output terminal 8 are formed. The thickness of the conductive film 160 for forming source / drain is approximately 200 to 300 nm. Source electrode 16, 26, 36, drain electrode 1
After patterning masks 554 and 555 are formed on the surfaces of the positions 7 and 27 and the input / output terminals 8, patterning is performed in this state, and the source / drain electrodes 16, 17, 26 and 27 shown in FIG. , 36 and the second conductive layer 81b of the input / output terminal 8 are formed.

Next, as shown in FIG. 6A, after an upper interlayer insulating film 402 made of silicon nitride or the like is formed, TF
In the T formation region, a flattening film 404 made of a transparent insulating film is formed in order to reduce the influence of the unevenness of each element and protect the element. At the same time, as shown in FIG. 6A, a transparent insulating film 403 is formed on the input / output terminal portion using the same material. The thickness of the transparent insulating film 403 is preferably about 1 to 2 μm. Next, the upper interlayer insulating film 402 on the drain electrode portion is removed by photolithography to form a contact hole. At this time, the upper interlayer insulating film 402 of the input / output terminal is also removed, and an opening 84 is provided in the input / output terminal (see FIG. 6B). Subsequently, as shown in FIG. 6C, a pixel electrode 100 connected to the drain electrode is formed in the TFT region by sputtering of ITO or the like. At the same time, the ITO layer 4 is formed on the inner wall of the opening 84 in the input / output terminal and on the upper surface of the second conductive layer 81b. Thereafter, an alignment film is applied to the TFT region, and a rubbing process is performed.

On the other hand, the surface of the ITO layer 4 formed in the opening 84 of the input / output terminal is subjected to a reduction treatment to form an In—Sn alloy surface layer 4a. As this reduction treatment method, a hydrogen plasma treatment, an alkaline solution treatment, or an electroplating treatment is preferable. This ITO
The reduction treatment for the layer 4 is performed after the ITO layer 4 is formed.
This can be performed at any timing before the FPC 9 is mounted on the input terminal 8. For example, even after the active matrix substrate 2 is assembled together with the counter substrate 3 into a liquid crystal device, the input / output terminal section is Since the ITO layer 4 is disposed outside the outer peripheral edge of the counter substrate 3 and is exposed, the ITO layer 4 can be subjected to a reduction treatment. In order to selectively perform the reduction process only in the opening portion 84 of the input / output terminal portion, a mask may be formed in other portions as necessary. As an example of the reduction treatment, the ITO layer 4
By performing a hydrogen plasma treatment on the (thickness: 100 nm) plasma plasma apparatus under the following treatment conditions, a preferable In-Sn alloy surface layer 4a can be formed. Substrate temperature 130 ° C. RF power 0.3 W / m ² H2 flow rate 50 sccm Pressure 75 Pa Time 8 minutes Gap between electrodes 25.4 mm

The active matrix substrate 2 thus manufactured is combined with the counter substrate 3, the liquid crystal 6 and the like to constitute a liquid crystal device as described above, and the FPC 9 is provided at the input / output terminal 8 of the active matrix substrate 2. Implemented. In the present embodiment, the second conductive layer 8 of the input / output terminal 8
1b, an ITO layer 4 is formed, and the ITO layer 4
Is subjected to a reduction treatment to form an In-Sn alloy surface layer 4a.
It has become. In forming the uppermost layer of the input / output terminal 8
Since the eutectic point of the —Sn alloy is 120 ° C., which is lower than 150 ° C., which is the heating temperature when the FPC 9 is heated and pressed to the active matrix substrate 2, the In—Sn alloy surface layer 4 a is easily formed in this heating and pressing step. Melts. Therefore, the metal conductor 42 of the FPC 9 and the In-
The bonding with the Sn alloy surface layer 4a can be directly performed by thermocompression bonding without using an adhesive. For example, as shown in FIG. 7, the input / output terminals 8 of the active matrix substrate 2 are
The metal wire 42 of the PC 9 is heated and pressed at about 150 ° C. so that the In-Sn alloy surface layer 4a of the input / output terminal 8 is melted, and the metal wire 42 and the input / output terminal 8 are connected to each other by In-Sn. Soldering is performed via the alloy surface layer 4a. Prior to joining the metal lead 42 of the FPC 9 and the input / output terminal 8, the surface of the metal lead 42 of the FPC 9 is
If a coating layer (not shown) made of Sn alloy is provided,
The In-Sn alloy layer on the metal conductor 42 and the In-Sn alloy surface layer 4a on the input / output terminal 8 are joined, and the same material is joined, so that the joining strength is improved. In this case, In
The coating layer made of the -Sn alloy may be provided at least on the surface of the metal conductor 42 to be joined to the input / output terminal 8.

According to the present embodiment, in the step of mounting the FPC 9 on the active matrix substrate 2, the metal conductor 42 of the FPC 9 can be connected to the input / output terminal 8 of the active matrix substrate 2 without using an adhesive. It is. Therefore, it is possible to prevent a connection failure or a high resistance caused by the insulating adhesive remaining on the input / output terminals 8, and to prevent a short circuit caused by metal particles in the adhesive. In particular, in the present embodiment, the metal conductor 42 of the FPC 9 and the conductive layers 81a and 81b of the input / output terminal 8
Since the connection is made via the conductive ITO layer 4 and the In—Sn alloy surface layer 4a, the connection is made surely electrically and the contact resistance is reduced. Further, since the periphery of the input / output terminal 8 is covered with the transparent insulating film 403, the insulating debris generated in the rubbing step of the alignment film or the cutting step of the substrate is captured by the side wall of the transparent insulating film 403. It does not reach the upper surface of the input / output terminal 8 and the connection with the FPC 9 is not hindered by such insulating debris. Further, in the present embodiment,
Since the transparent insulating film 403 is also provided on the peripheral portion 28 of the routing wiring 75, the routing wiring 75 is provided in the mounting process.
Is protected. Also, in the present embodiment, the input / output terminals 8
Since the transparent insulating film 403 and the transparent insulating film 403 are formed at the same time, the production efficiency is high.

In the above-described embodiment, the metal conductor 42 of the FPC 9 and the input / output terminal 8 are connected without using an adhesive, but the adhesive 44 in which the metal particles 43 are dispersed as in the conventional case. Can also be connected. In this case, since the In-Sn alloy surface layer 4a on the input / output terminal 8 is melted at the time of heat compression, the metal particles 43 in the adhesive 44 are strongly bonded to the In-Sn alloy surface layer 4a, and the bonding strength is increased. And the contact resistance is reduced as compared with the case where the In-Sn alloy surface layer 4a is not provided. In addition, the metal conductor 4
2 is also provided with a coating layer made of an In—Sn alloy, the coating layer is also melted at the time of thermocompression bonding to form metal particles 43.
The bonding strength is further improved, and the contact resistance is reduced. Furthermore, if a coating layer made of an In-Sn alloy is also provided on the surface of the metal particles 43 in the adhesive 44, this coating layer is also melted at the time of thermocompression bonding and the surface of the In-Sn alloy of the input / output terminal 8 is formed. The layer 4a and the In-Sn alloy coating layer on the metal conductor 42 of the FPC 9 are joined to form the same material, so that the joining strength is improved and the contact resistance is reduced. in this way,
When an adhesive is used to join the metal conductor 42 of the FPC 9 and the input / output terminal 8, the transparent insulating film 403 is provided between the adjacent input / output terminals 8. 8, the metal particles 43 in the adhesive 44
Can be prevented from being short-circuited due to the entry of a large number of pits.

FIG. 8 shows a peripheral portion of an input / output terminal according to a second embodiment of the present invention. This embodiment is different from the first embodiment in that the input / output terminals 8 and the transparent insulating film 40
The third embodiment is different from the first embodiment in that a recess 406 is provided between the first embodiment and the third embodiment. The ITO layer 4 includes an inner wall of the opening 84 of the transparent insulating film 403, an inner surface of the depression 406,
It is formed continuously on the upper surface of the input / output terminal 8. Depression 4
06 is overetched when the transparent insulating films 403 and 402 are etched to form the opening 84, so that the second conductive layer 81b remains and the second conductive layer 81b is left.
It is formed by deeply etching only the periphery of b. According to the present embodiment, the same operation and effect as those of the first embodiment can be obtained, and since the depression 406 is provided around the input / output terminal 8, the rubbing step of the alignment film and the cutting step of the substrate are performed. Of insulating material generated by
6 and is reliably captured. Therefore, when the FPC 9 is mounted, it is possible to obtain an effect of reliably preventing a contact failure or an increase in contact resistance due to the waste of the insulator.

FIG. 9 shows a peripheral portion of an input / output terminal according to a third embodiment of the present invention. This embodiment is different from the first embodiment in that a groove 407 is provided in the transparent insulating film 403, and the other configuration is the same as that of the first embodiment. The groove 407 can be formed by patterning the transparent insulating film 403 to provide the opening 84 and, at the same time, patterning and removing a portion of the transparent insulating film 403 between the input / output terminals, which becomes the groove 407. According to this embodiment, the same operation and effect as those of the first embodiment can be obtained, and the metal conductor 42 of the FPC 9 and the input / output terminal 8
When an adhesive is used for bonding with the upper part, the adhesive which is softened and flows at the time of heating and pressing is accommodated in the groove 407, and an effect of preventing the adhesive from flowing into the input / output terminal 8 of the opening 84 can be obtained. There is no particular limitation on the shape, width or depth of the groove 407, and it is preferable to make the groove as wide and deep as possible so that the adhesive can be sufficiently accommodated.

In the present invention, the conductive layer of the input / output terminal 8 corresponds to the first conductive layer 81a and the second conductive layer 81b.
Although it is composed of layers, the configuration of the conductive layer is not particularly limited, and it may be composed of one layer as long as production is possible. Input / output terminal 8
Among the metal materials listed above, Cr is particularly preferably used because it is relatively easy to process and can form a good electrical contact with ITO.

[0033]

According to the present invention, since the surface layer of the input / output terminal is made of an indium-tin alloy, the input / output terminal and the metal conductor of the FPC can be connected without using an adhesive.
Strong bonding can be achieved by thermocompression bonding. Therefore, in the mounting step of connecting the FPC to the input / output terminals, it is possible to prevent poor contact and increase in contact resistance between the input / output terminals and the FPC, and to obtain a stable quality liquid crystal device.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of an input / output terminal section of a liquid crystal device according to the present invention.

FIG. 2 is a sectional view taken along the line A-A 'of FIG.

FIG. 3 is a sectional view taken along the line B-B 'of FIG.

4A to 4E are process cross-sectional views illustrating a method of manufacturing the input / output terminal of the liquid crystal device illustrated in FIG.

5 (a) to 5 (e) are cross-sectional views showing the steps performed after the step shown in FIG. 4 in the method for manufacturing the input / output terminal of the liquid crystal device shown in FIG.

6 (a) to 6 (c) are cross-sectional views showing the steps performed after the step shown in FIG. 5 in the method for manufacturing the input / output terminal of the liquid crystal device shown in FIG.

FIG. 7 is a diagram illustrating an example of a heat compression bonding step between an input / output terminal of a liquid crystal device according to the present invention and a flexible printed circuit board.

FIG. 8 is a sectional view showing another example of the input / output terminal of the liquid crystal device according to the present invention.

FIG. 9 is a sectional view showing another example of the input / output terminal of the liquid crystal device according to the present invention.

FIG. 10 is a block diagram illustrating an example of an active matrix substrate of the liquid crystal device according to the present invention.

FIG. 11 is a plan view illustrating an example of a liquid crystal device according to the present invention.

FIG. 12 is a sectional view taken along the line HH ′ of FIG. 11;

FIG. 13 is a diagram illustrating a flexible printed circuit board.

FIG. 14 is a diagram illustrating a bonding state between an input / output terminal and a flexible printed board.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 2 ... Active matrix substrate, 4 ...
Indium tin oxide (ITO) layer, 4a: indium-tin alloy surface layer, 8: input / output terminal, 9: flexible printed circuit (FPC), 10: TFT for pixel, 1
4 ... insulating film, 41 ... synthetic resin layer, 42 ... metal conductor,
43 ... metal particles, 44 ... adhesive, 45 ... adhesive tape, 81a ... first conductive layer, 81b ... second conductive layer,
84: opening, 90: data line, 91: scanning line, 1
00: pixel electrode, 403: transparent insulating film, 551, 5
52, 553, 554: Mask for patterning.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Toru Takeguchi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 2H092 GA32 GA34 GA48 GA49 GA50 GA55 HA12 HA18 HA24 JA26 JA28 JA37 KA04 MA07 MA13 MA17 MA27 MA29 MA30 NA15 NA16 NA18 NA28 5G435 AA16 BB12 EE33 EE37 EE41 EE42 EE47 HH12 HH14 KK05

Claims (11)

[Claims] A plurality of scanning lines and a plurality of data lines formed in a matrix on a substrate; a switching element connected to the scanning line and the data line; a pixel electrode connected to the switching element; A liquid crystal device having an input / output terminal, the input / output terminal being a conductive layer, an indium tin oxide layer formed on the conductive layer, and reducing the surface of the indium tin oxide layer. Indium-
A liquid crystal device comprising a tin alloy surface layer. 2. The liquid crystal device according to claim 1, wherein a peripheral portion of said input / output terminal is covered with a transparent insulating film. 3. An upper surface of the transparent insulating film is higher than an upper surface of the input / output terminal, and the upper surface of the input / output terminal is an opening having no transparent insulating film. 3. The indium tin oxide layer is formed on an upper surface of a writing / output terminal, and the surface of the indium tin oxide layer is reduced to form an indium-tin alloy surface layer. Liquid crystal device. 4. The conductive layer of said input / output terminal is made of chrome (C
4. The liquid crystal device according to claim 1, wherein the liquid crystal device comprises: r). 5. The liquid crystal device according to claim 1, wherein a metal conductive wire of a flexible printed circuit board is joined to an upper surface of the input / output terminal by heat compression. 6. The liquid crystal device according to claim 5, wherein a coating layer made of an indium-tin alloy is formed on a surface of the flexible printed circuit board to be joined to the input / output terminal. 7. The flexible printed circuit board according to claim 1, wherein a metal wire of the flexible printed circuit board is joined to an upper surface of the input / output terminal via an adhesive containing metal particles. 3. The liquid crystal device according to claim 1. 8. The liquid crystal device according to claim 7, wherein a coating layer made of an indium-tin alloy is formed on surfaces of the metal particles. 9. The flexible printed circuit board according to claim 7, wherein a coating layer made of an indium-tin alloy is formed on a surface of the metal conductor wire to be joined to the input / output terminal. The liquid crystal device according to any one of the above. 10. A method for manufacturing a liquid crystal device in which a thin film transistor and an input / output terminal are formed on an insulating substrate, wherein a first conductive film serving as an input / output terminal is formed on the insulating substrate.
Forming a first conductive layer of the input / output terminal by patterning the first conductive film; and forming an insulating film on the substrate after forming the first conductive layer of the input / output terminal. Forming a second conductive film on the substrate after removing the insulating film in the output terminal portion and patterning the second conductive film on the substrate; Forming a transparent insulating film around the input / output terminal including the second conductive layer of the input / output terminal, and forming an opening on the input / output terminal by patterning the transparent insulating film; Forming an indium tin oxide layer on the inner surface of the opening and on the second conductive layer of the input / output terminal; and reducing a surface portion of the indium tin oxide layer to form an indium-tin alloy Forming a surface layer. Manufacturing method 11. The method according to claim 10, wherein the formation of the input / output terminals is performed simultaneously with the formation of the thin film transistors.