JP2001250842A - Semiconductor device and its manufacturing method, circuit board, and electronic equipment - Google Patents
Semiconductor device and its manufacturing method, circuit board, and electronic equipmentInfo
- Publication number
- JP2001250842A JP2001250842A JP2000061416A JP2000061416A JP2001250842A JP 2001250842 A JP2001250842 A JP 2001250842A JP 2000061416 A JP2000061416 A JP 2000061416A JP 2000061416 A JP2000061416 A JP 2000061416A JP 2001250842 A JP2001250842 A JP 2001250842A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- wiring
- hole
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法、回路基板並びに電子機器に関する。The present invention relates to a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device.
【０００２】[0002]
【発明の背景】半導体チップとインターポーザとの電気
的接続に、ワイヤーボンディングやＴＡＢ（Tape Autom
ated Bonding）のように、熱、圧力又は超音波振動等の
物理的なストレスを加える方法が行われている。これら
の方法では、拡散接合又は共晶接合によって電気的な接
続を図っていたので、熱や圧力の条件設定が難しく、狭
ピッチ化に限界があった。BACKGROUND OF THE INVENTION For electrical connection between a semiconductor chip and an interposer, wire bonding or TAB (Tape Automated) is used.
A method of applying a physical stress such as heat, pressure, or ultrasonic vibration as in the case of ated bonding. In these methods, since electrical connection is achieved by diffusion bonding or eutectic bonding, it is difficult to set conditions of heat and pressure, and there is a limit to narrow pitch.
【０００３】本発明は、この問題点を解決するものであ
り、その目的は、狭ピッチの電気的接続に対応できる半
導体装置及びその製造方法、回路基板並びに電子機器を
提供することにある。An object of the present invention is to solve this problem, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic apparatus which can cope with a narrow-pitch electrical connection.
【０００４】[0004]
【課題を解決するための手段】（１）本発明に係る半導
体装置の製造方法は、電極を有する半導体チップと基板
とが積層され、前記基板は、前記電極の少なくとも一部
と平面的に重なる位置に貫通穴を有し、かつ、前記基板
の前記半導体チップと対向する面とは反対の面に配線を
有してなる半導体装置の製造方法であって、前記貫通穴
に導電性材料を充填して、前記電極と前記配線とを電気
的に接続する。(1) In a method of manufacturing a semiconductor device according to the present invention, a semiconductor chip having electrodes is laminated on a substrate, and the substrate overlaps at least a part of the electrodes in a plane. A method of manufacturing a semiconductor device having a through hole at a position and wiring on a surface of the substrate opposite to a surface facing the semiconductor chip, wherein the through hole is filled with a conductive material. Then, the electrode and the wiring are electrically connected.
【０００５】本発明によれば、導電性材料を充填して、
電極と配線とを電気的に接続するので、熱、圧力等の物
理的なストレスを加えなくてよい。したがって、狭ピッ
チの電極に対応することができる。According to the present invention, a conductive material is filled,
Since the electrode and the wiring are electrically connected, there is no need to apply physical stress such as heat and pressure. Therefore, it is possible to correspond to an electrode having a narrow pitch.
【０００６】（２）この半導体装置の製造方法におい
て、前記基板に前記貫通穴を形成した後に、前記基板を
前記半導体チップ上に配置してもよい。(2) In this method of manufacturing a semiconductor device, the substrate may be arranged on the semiconductor chip after the through hole is formed in the substrate.
【０００７】予め基板に貫通穴を形成しておくことは容
易に行えるので、簡単な工程で、電極と配線とを電気的
に接続することができる。Since through holes can be easily formed in the substrate in advance, the electrodes and the wirings can be electrically connected in a simple process.
【０００８】（３）この半導体装置の製造方法におい
て、前記基板に前記配線を形成した後に、前記基板を前
記半導体チップ上に配置してもよい。(3) In this method of manufacturing a semiconductor device, after the wiring is formed on the substrate, the substrate may be disposed on the semiconductor chip.
【０００９】これによれば、一般的な配線基板を使用す
ることが可能である。According to this, it is possible to use a general wiring board.
【００１０】（４）この半導体装置の製造方法におい
て、前記配線を、前記貫通穴上を通って形成してもよ
い。(4) In this method of manufacturing a semiconductor device, the wiring may be formed to pass over the through hole.
【００１１】これによれば、貫通穴に充填した導電性材
料と配線とを電気的に接続しやすい。According to this, it is easy to electrically connect the conductive material filled in the through hole and the wiring.
【００１２】（５）この半導体装置の製造方法におい
て、前記導電性材料を、インクジェット方式によって充
填してもよい。(5) In this method of manufacturing a semiconductor device, the conductive material may be filled by an ink jet method.
【００１３】（６）この半導体装置の製造方法におい
て、前記半導体チップ及び前記基板を、前記導電性材料
に浸漬することで、前記導電性材料を前記貫通穴に充填
してもよい。(6) In the method of manufacturing a semiconductor device, the conductive material may be filled in the through hole by immersing the semiconductor chip and the substrate in the conductive material.
【００１４】（７）この半導体装置の製造方法におい
て、前記導電性材料を、エネルギーによって硬化させて
もよい。(7) In the method of manufacturing a semiconductor device, the conductive material may be cured by energy.
【００１５】（８）本発明に係る半導体装置は、上記方
法によって製造されたものである。(8) A semiconductor device according to the present invention is manufactured by the above method.
【００１６】（９）本発明に係る半導体装置は、電極を
有する半導体チップと基板とが積層され、前記基板は、
前記電極と平面的に重なる位置に貫通穴を有し、かつ、
前記基板の前記半導体チップと対向する面とは反対の面
に配線を有してなる半導体装置であって、前記貫通穴に
導電性材料が充填されてなり、前記電極と前記配線とが
電気的に接続されたものである。(9) In a semiconductor device according to the present invention, a semiconductor chip having electrodes and a substrate are laminated, and the substrate is
Having a through hole at a position overlapping the electrode in a plane, and
A semiconductor device having a wiring on a surface of the substrate opposite to a surface facing the semiconductor chip, wherein the through hole is filled with a conductive material, and the electrode and the wiring are electrically connected to each other. Is connected to
【００１７】本発明によれば、電極と配線とを電気的に
接続する導電性材料は、貫通穴に充填されているので、
横方向に大きく拡がることがなく、狭ピッチの電極に対
応できる。According to the present invention, since the conductive material for electrically connecting the electrode and the wiring is filled in the through hole,
It is possible to cope with a narrow-pitch electrode without greatly expanding in the lateral direction.
【００１８】（１０）この半導体装置において、前記配
線は、前記貫通穴上を通って形成されていてもよい。(10) In this semiconductor device, the wiring may be formed to pass over the through hole.
【００１９】これによれば、貫通穴の開口部から横に拡
げずに、導電性材料と配線とを電気的に接続することが
できる。According to this, the conductive material and the wiring can be electrically connected without expanding laterally from the opening of the through hole.
【００２０】（１１）本発明に係る回路基板は、上記半
導体装置が実装されたものである。(11) A circuit board according to the present invention has the above-described semiconductor device mounted thereon.
【００２１】（１２）本発明に係る電子機器は、上記半
導体装置を有する。(12) An electronic apparatus according to the present invention includes the above semiconductor device.
【００２２】[0022]
【発明の実施の形態】以下、本発明の好適な実施の形態
について図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.
【００２３】（第１の実施の形態）図１〜図４は、本発
明を適用した第１の実施の形態に係る半導体装置の製造
方法を示す図である。本実施の形態では、半導体チップ
１０と、基板２０と、が使用される。(First Embodiment) FIGS. 1 to 4 show a method of manufacturing a semiconductor device according to a first embodiment of the present invention. In the present embodiment, a semiconductor chip 10 and a substrate 20 are used.
【００２４】半導体チップ１０の平面形状は一般的には
矩形である。半導体チップ１０の一方の面に、複数の電
極１２が形成されている。電極１２は、半導体チップ１
０の面の少なくとも１辺（多くの場合、平行な２辺又は
４辺）に沿って並んでいる。また、電極１２は、半導体
チップ１０の面の端部に並んでいる場合と、図１に示す
ように中央部に並んでいる場合がある。各電極１２は、
アルミニウムなどで薄く平らに形成されたパッドであ
る。電極１２の少なくとも一部を避けて半導体チップ１
０には、パッシベーション膜１４が形成されている。パ
ッシベーション膜１４は、例えば、ＳｉＯ2、ＳｉＮ、
ポリイミド樹脂などで形成することができる。The planar shape of the semiconductor chip 10 is generally rectangular. A plurality of electrodes 12 are formed on one surface of the semiconductor chip 10. The electrode 12 is a semiconductor chip 1
They are arranged along at least one side (often two or four parallel sides) of the 0 plane. The electrodes 12 may be arranged at the end of the surface of the semiconductor chip 10 or may be arranged at the center as shown in FIG. Each electrode 12
The pad is formed thin and flat with aluminum or the like. Semiconductor chip 1 avoiding at least part of electrode 12
At 0, a passivation film 14 is formed. The passivation film 14 is made of, for example, SiO 2 , SiN,
It can be formed of a polyimide resin or the like.
【００２５】電極１２には、バンプを設けてもよいが、
本発明では必須ではない。なお、バンプは、銀ペースト
などの導電ペーストや、金、ニッケル、銅、銀などの金
属で形成することができる。バンプは、無電解メッキで
形成してもよいし、ワイヤボンディングによるバンプで
あってもよい。The electrode 12 may be provided with a bump,
It is not essential in the present invention. Note that the bump can be formed using a conductive paste such as a silver paste or a metal such as gold, nickel, copper, or silver. The bump may be formed by electroless plating, or may be a bump formed by wire bonding.
【００２６】基板２０の一方の面には、配線２２が形成
されている。なお、配線２２とは、少なくとも２点間の
電気的接続を図るものを指し、独立した複数の配線２２
を配線パターンと称してもよい。配線２２は、銅（Ｃ
ｕ）、クローム（Ｃｒ）、チタン（Ｔｉ）、ニッケル
（Ｎｉ）、チタンタングステン（Ｔｉ−Ｗ）のうちのい
ずれかを積層して、あるいはいずれかの一層で形成する
ことができる。配線２２が接着剤（図示せず）を介して
基板２０に貼り付けられて、３層基板を構成してもよ
い。この場合、フォトリソグラフィを適用した後にエッ
チングして配線２２を形成する。The wiring 22 is formed on one surface of the substrate 20. Note that the wiring 22 refers to one that establishes electrical connection between at least two points, and includes a plurality of independent wirings 22.
May be referred to as a wiring pattern. The wiring 22 is made of copper (C
u), chromium (Cr), titanium (Ti), nickel (Ni), and titanium tungsten (Ti-W). The wiring 22 may be attached to the substrate 20 via an adhesive (not shown) to form a three-layer substrate. In this case, the wiring 22 is formed by etching after applying photolithography.
【００２７】あるいは、配線２２を、接着剤なしで基板
２０に形成して２層基板を構成してもよい。例えば、ス
パッタリング等によって配線２２を形成してもよいし、
メッキで配線２２を形成するアディティブ法を適用して
もよい。Alternatively, the wiring 22 may be formed on the substrate 20 without an adhesive to form a two-layer substrate. For example, the wiring 22 may be formed by sputtering or the like,
An additive method of forming the wiring 22 by plating may be applied.
【００２８】配線２２は、ハンダ、スズ、金、ニッケル
などでメッキされていることが好ましい。共晶が作られ
るような金属メッキが施されていてもよい。配線２２の
一部は、引き回した部分よりも面積の大きいランドとな
っていてもよい。このランドには、ハンダボールなどの
外部端子を設けてもよい。The wiring 22 is preferably plated with solder, tin, gold, nickel or the like. Metal plating such that a eutectic may be formed may be applied. A part of the wiring 22 may be a land having an area larger than that of the routing part. External terminals such as solder balls may be provided on the lands.
【００２９】基板２０には、貫通穴２４が形成されてい
る。貫通穴２４の平面形状は、円形であっても矩形であ
ってもよい。貫通穴２４は、テーパが付されて形成され
ていてもよい。例えば、基板２０の配線２２が形成され
た面の方向に貫通穴２４が拡がっていてもよい。貫通穴
２４は、電極１２の表面（例えばパッシベーション膜１
４からの露出面）よりも小さく形成されていてもよい。
こうすることで、貫通穴２４に導電性材料３０（図３参
照）を充填したときに、導電性材料３０が電極１２から
はみ出さない。もっとも、パッシベーション膜１４の電
気的絶縁の信頼性が高ければ、パッシベーション膜１４
上に導電性材料３０が載るように、電極１２の表面（例
えばパッシベーション膜１４からの露出面）よりも貫通
穴２４を大きく形成してもよい。The substrate 20 has a through hole 24 formed therein. The planar shape of the through hole 24 may be circular or rectangular. The through hole 24 may be tapered. For example, the through hole 24 may extend in the direction of the surface of the substrate 20 where the wiring 22 is formed. The through hole 24 is formed on the surface of the electrode 12 (for example, the passivation film 1).
4 (exposed surface from 4).
By doing so, when the conductive material 30 (see FIG. 3) is filled in the through hole 24, the conductive material 30 does not protrude from the electrode 12. However, if the reliability of the electrical insulation of the passivation film 14 is high, the passivation film 14
The through-hole 24 may be formed larger than the surface of the electrode 12 (for example, the surface exposed from the passivation film 14) so that the conductive material 30 is placed thereon.
【００３０】図２は、基板２０の配線２２が形成された
面の平面図である。配線２２は、貫通穴２４の少なくと
も一部を開口させて（塞がないで）形成されている。例
えば、図１に示すように、配線２２を、貫通穴２４の開
口よりも小さい幅で形成し、貫通穴２４上を通して形成
してもよい。あるいは、配線２２を貫通穴２４の開口よ
りも大きい幅で、貫通穴２４を塞いで形成しても良い。
その際、配線２２に穴を形成して、貫通穴２４の一部を
開口させておけば、導電性材料３０を貫通穴２４に充填
させることができる。配線２２を、貫通穴２４を避けて
（貫通穴２４上を通さずに）形成するときには、貫通穴
２４に接近して配線２２を形成する。あるいは、配線２
２の側端と貫通穴２４の内面とを面一にしてもよい。FIG. 2 is a plan view of the surface of the substrate 20 on which the wiring 22 is formed. The wiring 22 is formed by opening at least a part of the through hole 24 (without closing). For example, as shown in FIG. 1, the wiring 22 may be formed with a width smaller than the opening of the through hole 24 and formed on the through hole 24. Alternatively, the wiring 22 may be formed to have a width larger than the opening of the through hole 24 and close the through hole 24.
At this time, if a hole is formed in the wiring 22 and a part of the through hole 24 is opened, the conductive material 30 can be filled in the through hole 24. When forming the wiring 22 avoiding the through hole 24 (not passing over the through hole 24), the wiring 22 is formed close to the through hole 24. Alternatively, wiring 2
2 and the inner surface of the through hole 24 may be flush.
【００３１】基板２０の少なくとも配線２２上には、保
護膜２６（例えばソルダーレジスト）を形成しておくこ
とが好ましい。また、基板２０の、配線２２が形成され
た面とは反対側の面には、接着剤２８を設けておいても
よい。接着剤２８は、液状で用意して基板２０に塗布し
てもよいし、シート状で用意して基板２０に貼り付けて
もよい。It is preferable that a protective film 26 (for example, a solder resist) is formed on at least the wiring 22 of the substrate 20. Further, an adhesive 28 may be provided on the surface of the substrate 20 opposite to the surface on which the wirings 22 are formed. The adhesive 28 may be prepared in a liquid state and applied to the substrate 20, or may be prepared in a sheet form and adhered to the substrate 20.
【００３２】本実施の形態では、上述した基板２０を、
半導体チップ１０上に配置する。詳しくは、基板２０の
貫通穴２４を、電極１２上に配置する。そして、図３に
示すように、基板２０を半導体チップ１０に貼り付け
る。続いて、図３及び図４に示すように、導電性材料３
０を貫通穴２４に充填する。導電性材料３０は、変形可
能なもの（例えば流動体）であればよく、例えばペース
ト状、液状、ゲル状で用意する。具体的には、導電粒子
を含有した樹脂、ハンダ等を導電性材料３０とすること
ができる。なお、樹脂が使用される場合には、熱、紫外
線、光等で硬化するものであってもよい。In the present embodiment, the above-described substrate 20 is
It is arranged on the semiconductor chip 10. Specifically, the through hole 24 of the substrate 20 is arranged on the electrode 12. Then, as shown in FIG. 3, the substrate 20 is attached to the semiconductor chip 10. Subsequently, as shown in FIG. 3 and FIG.
0 is filled in the through hole 24. The conductive material 30 may be any material that can be deformed (for example, a fluid), and is prepared, for example, in the form of a paste, a liquid, or a gel. Specifically, resin, solder, or the like containing conductive particles can be used as the conductive material 30. When a resin is used, the resin may be cured by heat, ultraviolet light, light, or the like.
【００３３】導電性材料３０は、貫通穴２４に注入すれ
ばよい。また、スクリーン印刷によって導電性材料３０
を設けてもよい。あるいは、インクジェット方式（ハン
ダジェット方式）によって、導電性材料３０を充填して
もよい。あるいは、導電性材料３０を容器に溜めて、半
導体チップ１０及び基板２０を導電性材料３０に浸漬さ
せることで、導電性材料３０を充填してもよい。The conductive material 30 may be injected into the through hole 24. Further, the conductive material 30 is formed by screen printing.
May be provided. Alternatively, the conductive material 30 may be filled by an ink jet method (solder jet method). Alternatively, the conductive material 30 may be filled in a container, and the semiconductor chip 10 and the substrate 20 may be immersed in the conductive material 30.
【００３４】導電性材料３０は、電極１２及び配線２２
に接触させて設ける。貫通穴２４内に隙間が形成されな
いように導電性材料３０を設けることが好ましい。ま
た、導電性材料３０は、貫通穴２４から盛り上がってい
てもよい。なお、配線２２が貫通穴２４上を通らないと
きには、貫通穴２４の開口から拡げて導電性材料３０を
設ける。The conductive material 30 includes the electrode 12 and the wiring 22.
Provided in contact with It is preferable to provide the conductive material 30 so that no gap is formed in the through hole 24. Further, the conductive material 30 may be raised from the through hole 24. When the wiring 22 does not pass over the through hole 24, the conductive material 30 is provided so as to expand from the opening of the through hole 24.
【００３５】こうして、図４に示すように、貫通穴２４
に充填された導電性材料３０によって、電極１２と配線
２２とが電気的に接続される。また、導電性材料３０の
性質に応じて、熱、紫外線、光等のエネルギーを加え
て、導電性材料３０を硬化させてもよい。Thus, as shown in FIG.
The electrode 12 and the wiring 22 are electrically connected by the conductive material 30 filled in the substrate. Further, depending on the properties of the conductive material 30, the conductive material 30 may be cured by applying energy such as heat, ultraviolet light, or light.
【００３６】本実施の形態によれば、導電性材料３０を
貫通穴２４に充填して、電極１２と配線２２とを電気的
に接続するので、熱、圧力等の物理的なストレスを加え
なくてよい。したがって、電極１２の配列やピッチにか
かわらず、電気的な接続を行うことができる。According to the present embodiment, since the conductive material 30 is filled in the through holes 24 and the electrodes 12 and the wirings 22 are electrically connected, no physical stress such as heat and pressure is applied. May be. Therefore, electrical connection can be made regardless of the arrangement and pitch of the electrodes 12.
【００３７】本実施の形態に係る半導体装置は、上述し
た半導体チップ１０、基板２０、導電性材料３０を含
む。本実施の形態によれば、電極１２と配線２２とを電
気的に接続する導電性材料３０は、貫通穴２４に充填さ
れている。したがって、配線２２が貫通穴２４上を通っ
て形成されていれば、導電性材料３０が横方向に大きく
拡がらない。そのため、狭ピッチの電極１２であって
も、隣同士の電極１２がショートすることなく、電気的
な接続が図られる。The semiconductor device according to the present embodiment includes the above-described semiconductor chip 10, substrate 20, and conductive material 30. According to the present embodiment, the through hole 24 is filled with the conductive material 30 that electrically connects the electrode 12 and the wiring 22. Therefore, if the wiring 22 is formed over the through-hole 24, the conductive material 30 does not greatly spread in the lateral direction. Therefore, even if the electrodes 12 have a narrow pitch, electrical connection is achieved without short-circuiting between adjacent electrodes 12.
【００３８】本発明は、上記実施の形態に限定されるも
のではなく、種々の変形が可能である。例えば、上記実
施の形態では、予め配線２２及び貫通穴２４が形成され
た基板２０を、半導体チップ１０に貼り付けた。その代
わりに、貫通穴２４が形成されていない基板２０を半導
体チップ１０上に配置した後に、基板２０に貫通穴２４
を形成してもよい。また、配線２２が形成されていない
基板２０を半導体チップ１０上に配置した後に、基板２
０に配線２２を形成してもよい。The present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above embodiment, the substrate 20 in which the wiring 22 and the through hole 24 are formed in advance is attached to the semiconductor chip 10. Instead, after arranging the substrate 20 on which the through hole 24 is not formed on the semiconductor chip 10,
May be formed. After arranging the substrate 20 on which the wiring 22 is not formed on the semiconductor chip 10,
The wiring 22 may be formed at 0.
【００３９】（第２の実施の形態）本発明は、リール・
トゥ・リールの工程に対応させることができる。図５
は、リール・トゥ・リールが適用された第２の実施の形
態を示す図である。(Second Embodiment) The present invention relates to a reel
It can correspond to a to-reel process. FIG.
FIG. 9 is a diagram showing a second embodiment to which a reel-to-reel is applied.
【００４０】基板４０には、図示しないリールに巻き取
るため、複数のスプロケットホール４２が形成されてい
てもよい。基板４０は、ＴＡＢ技術が適用される場合に
は、ＴＡＢ用基板（フィルムキャリアテープ）である
が、これに限定されるものではなく、ＣＯＦ（Chip On
Film）用基板や、ＣＯＢ（Chip On Board）用基板であ
ってもよい。A plurality of sprocket holes 42 may be formed in the substrate 40 for winding on a reel (not shown). When the TAB technology is applied, the substrate 40 is a TAB substrate (film carrier tape), but is not limited thereto, and may be a COF (Chip On Chip).
Film) substrate or COB (Chip On Board) substrate.
【００４１】基板４０は、長尺状（テープ状）をなす基
材であり、配線４４の支持部材である。１つの半導体装
置に使用される複数の配線４４によって１つの配線パタ
ーンが構成され、長尺状の基板４０には、図示しない複
数の配線パターンが形成されている。基板４０は、フレ
キシブル性を有する。基板４０は、ポリイミド樹脂で形
成されることが多いがそれ以外の周知の材料を使用する
ことができる。The substrate 40 is a long (tape-shaped) base material, and is a support member for the wiring 44. One wiring pattern is formed by a plurality of wirings 44 used for one semiconductor device, and a plurality of wiring patterns (not shown) are formed on the long substrate 40. The substrate 40 has flexibility. The substrate 40 is often formed of a polyimide resin, but other known materials can be used.
【００４２】図５に示す基板４０にも貫通穴４６が形成
されており、貫通穴４６上を配線４４が通るようになっ
ている。また、配線４４は、ランド部４８を有する。ラ
ンド部４８には、ハンダボール等の外部端子を設けるこ
とができる。ランド部４８は、複数の配線２２からなる
１つの配線パターンの中央部に位置する。A through hole 46 is also formed in the substrate 40 shown in FIG. 5, and the wiring 44 passes over the through hole 46. Further, the wiring 44 has a land portion 48. External terminals such as solder balls can be provided on the land portions 48. The land portion 48 is located at the center of one wiring pattern including a plurality of wirings 22.
【００４３】本実施の形態で使用する半導体チップ１０
０は、端部に図示しない電極が形成されている。配線２
２は、半導体チップ１００の端部から中央部に引き回さ
れており、中央部に外部端子を設けるためのランド部４
８が形成されている。すなわち、本実施の形態では、外
部端子が半導体チップ１０の搭載領域内のみに設けられ
たＦＡＮ−ＩＮ型の半導体装置を製造する。Semiconductor chip 10 used in this embodiment
Reference numeral 0 indicates that an electrode (not shown) is formed at the end. Wiring 2
Reference numeral 2 denotes a land portion 4 extending from the end of the semiconductor chip 100 to the center, and providing an external terminal at the center.
8 are formed. That is, in this embodiment, a FAN-IN type semiconductor device in which external terminals are provided only in the mounting region of the semiconductor chip 10 is manufactured.
【００４４】本実施の形態でも、基板４０と半導体チッ
プ１００とを貼り付けて、第１の実施の形態で説明した
工程を行う。基板４０が長尺状をなすので、複数の半導
体チップ１００を連続的に基板４０に貼り付けて、リー
ル・ツゥ・リールで工程を行うことができる。Also in the present embodiment, the steps described in the first embodiment are performed by attaching the substrate 40 and the semiconductor chip 100. Since the substrate 40 has a long shape, a plurality of semiconductor chips 100 can be continuously attached to the substrate 40, and the process can be performed on a reel-to-reel.
【００４５】（第３の実施の形態）図６は、本発明を適
用した第３の実施の形態に係る半導体装置を示す図であ
る。本実施の形態に係る半導体装置は、半導体チップ５
０及び基板６０を有する。基板６０に形成された配線６
２と、半導体チップ５０の電極５２とは、導電性材料７
０によって電気的に接続されている。基板６０は、半導
体チップ５０よりも大きい。(Third Embodiment) FIG. 6 is a view showing a semiconductor device according to a third embodiment to which the present invention is applied. The semiconductor device according to the present embodiment includes a semiconductor chip 5
0 and the substrate 60. Wiring 6 formed on substrate 60
2 and the electrode 52 of the semiconductor chip 50 are electrically conductive materials 7
0 is electrically connected. The substrate 60 is larger than the semiconductor chip 50.
【００４６】配線６２には、複数の外部端子８０が設け
られている。外部端子８０はハンダや金属などの、導電
性の部材で形成すればよい。本実施の形態では、外部端
子８０は、ハンダボールである。ハンダボールの形成に
は、配線６２上に盛り上がった状態でクリームハンダを
設け、これをリフロー工程で溶融させてボール状の端子
を形成してもよい。ハンダからなる外部端子８０を設け
るには、配線６２にハンダのメッキを施すことが好まし
い。The wiring 62 is provided with a plurality of external terminals 80. The external terminal 80 may be formed of a conductive member such as solder or metal. In the present embodiment, the external terminals 80 are solder balls. To form the solder balls, cream solder may be provided in a state of being raised on the wiring 62, and the solder may be melted in a reflow process to form ball-shaped terminals. In order to provide the external terminals 80 made of solder, it is preferable that the wiring 62 be plated with solder.
【００４７】なお、ハンダボールは必ずしも必要ではな
く、基板６０の延出部をコネクタとしたり、コネクタを
実装するなどの手段で配線６２を外部へ拡張させてもよ
いし、半導体チップ５０及びそれ以外の実装部品を基板
６０上に実装して、半導体モジュールを構成してもよ
い。The solder balls are not always necessary. The wiring 62 may be extended to the outside by means such as connecting the extension of the board 60 to a connector or mounting a connector. May be mounted on the substrate 60 to form a semiconductor module.
【００４８】さらに、ハンダボールを形成せず、マザー
ボード実装時にマザーボード側に塗布されるハンダクリ
ームを利用し、その溶融時の表面張力で電気的接続部を
形成してもよい。その半導体装置は、いわゆるＬＧＡ
（Land Grid Array）型の半導体装置である。Further, instead of forming the solder balls, the electric connection portion may be formed by using the surface tension at the time of melting, using a solder cream applied to the motherboard at the time of mounting the motherboard. The semiconductor device is a so-called LGA
(Land Grid Array) type semiconductor device.
【００４９】本実施の形態に係る半導体装置は、半導体
チップの搭載領域内及びその外に外部端子が設けられた
ＦＡＮ−ＩＮ／ＯＵＴ型の半導体装置であるが、半導体
チップの搭載領域外にのみ外部端子が設けられたＦＡＮ
−ＯＵＴ型の半導体装置に本発明を適用することもでき
る。The semiconductor device according to the present embodiment is a FAN-IN / OUT type semiconductor device in which external terminals are provided inside and outside the semiconductor chip mounting area, but only outside the semiconductor chip mounting area. FAN with external terminals
The present invention can be applied to a -OUT type semiconductor device.
【００５０】図７には、外部端子を有する半導体装置１
を実装した回路基板１０００が示されている。回路基板
１０００には例えばガラスエポキシ基板等の有機系基板
を用いることが一般的である。回路基板１０００には例
えば銅などからなる配線パターンが所望の回路となるよ
うに形成されていて、それらの配線パターンと半導体装
置１の外部端子とを機械的に接続することでそれらの電
気的導通を図る。FIG. 7 shows a semiconductor device 1 having external terminals.
Is mounted on the circuit board 1000. Generally, an organic substrate such as a glass epoxy substrate is used for the circuit board 1000. Wiring patterns made of, for example, copper or the like are formed on the circuit board 1000 so as to form a desired circuit, and these wiring patterns are electrically connected to external terminals of the semiconductor device 1 by mechanical connection. Plan.
【００５１】そして、本発明を適用した半導体装置１を
有する電子機器として、図８にはノート型パーソナルコ
ンピュータ２０００、図９には携帯電話３０００が示さ
れている。FIG. 8 shows a notebook personal computer 2000 and FIG. 9 shows a mobile phone 3000 as an electronic apparatus having the semiconductor device 1 to which the present invention is applied.
【００５２】なお、上述した実施の形態の「半導体チッ
プ」を「電子素子」に置き換えて、電子部品を製造する
こともできる。このような電子素子を使用して製造され
る電子部品として、例えば、光素子、抵抗器、コンデン
サ、コイル、発振器、フィルタ、温度センサ、サーミス
タ、バリスタ、ボリューム又はヒューズなどがある。Note that an electronic component can be manufactured by replacing the “semiconductor chip” in the above-described embodiment with an “electronic element”. Electronic components manufactured using such electronic devices include, for example, optical devices, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes or fuses.
【図１】図１は、本発明を適用した第１の実施の形態に
係る半導体装置の製造方法を示す図である。FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment to which the present invention is applied.
【図２】図２は、本発明を適用した第１の実施の形態に
係る基板の平面図である。FIG. 2 is a plan view of a substrate according to a first embodiment to which the present invention is applied.
【図３】図３は、本発明を適用した第１の実施の形態に
係る半導体装置の製造方法を示す図である。FIG. 3 is a diagram illustrating a method of manufacturing the semiconductor device according to the first embodiment to which the present invention is applied.
【図４】図４は、第１の実施の形態に係る半導体装置を
示す図である。FIG. 4 is a diagram illustrating the semiconductor device according to the first embodiment;
【図５】図５は、本発明を適用した第２の実施の形態に
係る半導体装置の製造方法を示す図である。FIG. 5 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment to which the present invention is applied.
【図６】図６は、本発明を適用した第２の実施の形態に
係る半導体装置を示す図である。FIG. 6 is a diagram showing a semiconductor device according to a second embodiment to which the present invention is applied.
【図７】図７は、本実施の形態に係る半導体装置が実装
された回路基板を示す図である。FIG. 7 is a diagram showing a circuit board on which the semiconductor device according to the present embodiment is mounted;
【図８】図８は、本実施の形態に係る半導体装置を有す
る電子機器を示す図である。FIG. 8 is a diagram illustrating an electronic device including the semiconductor device according to the embodiment;
【図９】図９は、本実施の形態に係る半導体装置を有す
る電子機器を示す図である。FIG. 9 is a diagram illustrating an electronic device including the semiconductor device according to the embodiment;
１０ 半導体チップ １２ 電極 ２０ 基板 ２２ 配線 ２４ 貫通穴 ３０ 導電性材料 ４０ 基板 ４４ 配線 ４６ 貫通穴 ５０ 半導体チップ ５２ 電極 ６０ 基板 ６２ 配線 ７０ 導電性材料 ８０ 外部端子 １００ 半導体チップ Reference Signs List 10 semiconductor chip 12 electrode 20 substrate 22 wiring 24 through hole 30 conductive material 40 substrate 44 wiring 46 through hole 50 semiconductor chip 52 electrode 60 substrate 62 wiring 70 conductive material 80 external terminal 100 semiconductor chip
Claims (12)
層され、前記基板は、前記電極の少なくとも一部と平面
的に重なる位置に貫通穴を有し、かつ、前記基板の前記
半導体チップと対向する面とは反対の面に配線を有して
なる半導体装置の製造方法であって、 前記貫通穴に導電性材料を充填して、前記電極と前記配
線とを電気的に接続する半導体装置の製造方法。1. A semiconductor chip having electrodes and a substrate are stacked, the substrate has a through hole at a position overlapping at least a part of the electrodes in a plane, and faces the semiconductor chip of the substrate. A method of manufacturing a semiconductor device having a wiring on a surface opposite to a surface to be formed, wherein the through hole is filled with a conductive material to electrically connect the electrode and the wiring. Production method.
おいて、 前記基板に前記貫通穴を形成した後に、前記基板を前記
半導体チップ上に配置する半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein said substrate is arranged on said semiconductor chip after said through hole is formed in said substrate.
の製造方法において、 前記基板に前記配線を形成した後に、前記基板を前記半
導体チップ上に配置する半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring is formed on the substrate, and then the substrate is disposed on the semiconductor chip.
の半導体装置の製造方法において、 前記配線を、前記貫通穴上を通って形成する半導体装置
の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring is formed over the through hole.
の半導体装置の製造方法において、 前記導電性材料を、インクジェット方式によって充填す
る半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive material is filled by an ink jet method.
の半導体装置の製造方法において、 前記半導体チップ及び前記基板を、前記導電性材料に浸
漬することで、前記導電性材料を前記貫通穴に充填する
半導体装置の製造方法。6. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip and the substrate are immersed in the conductive material to penetrate the conductive material. A method of manufacturing a semiconductor device for filling a hole.
の半導体装置の製造方法において、 前記導電性材料を、エネルギーによって硬化させる半導
体装置の製造方法。7. The method for manufacturing a semiconductor device according to claim 1, wherein the conductive material is cured by energy.
の方法によって製造された半導体装置。8. A semiconductor device manufactured by the method according to claim 1.
層され、前記基板は、前記電極と平面的に重なる位置に
貫通穴を有し、かつ、前記基板の前記半導体チップと対
向する面とは反対の面に配線を有してなる半導体装置で
あって、 前記貫通穴に導電性材料が充填されてなり、前記電極と
前記配線とが電気的に接続された半導体装置。9. A semiconductor chip having electrodes and a substrate are stacked, wherein the substrate has a through hole at a position overlapping the electrodes in a plane, and a surface of the substrate facing the semiconductor chips. A semiconductor device having a wiring on an opposite surface, wherein the through hole is filled with a conductive material, and the electrode and the wiring are electrically connected.
体装置。10. The semiconductor device according to claim 9, wherein said wiring is formed over said through hole.
装置が実装された回路基板。11. A circuit board on which the semiconductor device according to claim 9 is mounted.
装置を有する電子機器。12. An electronic apparatus comprising the semiconductor device according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000061416A JP3654113B2 (en) | 2000-03-07 | 2000-03-07 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000061416A JP3654113B2 (en) | 2000-03-07 | 2000-03-07 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001250842A true JP2001250842A (en) | 2001-09-14 |
| JP3654113B2 JP3654113B2 (en) | 2005-06-02 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6720645B2 (en) | 2002-05-16 | 2004-04-13 | Oki Electric Industry Co., Ltd. | Semiconductor device |
| JP2007511091A (en) * | 2003-11-05 | 2007-04-26 | カリフォルニア インスティチュート オブ テクノロジー | Method for integrating off-the-shelf chip structures into functional electronic systems |
| EP1976355A2 (en) | 2007-03-28 | 2008-10-01 | Brother Kogyo Kabushiki Kaisha | Method for connecting two objects electrically |
| US7781324B2 (en) | 2005-06-30 | 2010-08-24 | Brother Kogyo Kabushiki Kaisha | Method of producing wire-connection structure, and wire-connection structure |
| US7847406B2 (en) | 2002-11-06 | 2010-12-07 | Ricoh Company, Ltd. | Solder alloy material layer composition, electroconductive and adhesive composition, flux material layer composition, solder ball transferring sheet, bump and bump forming process, and semiconductore device |
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| US8985734B2 (en) | 2012-08-31 | 2015-03-24 | Brother Kogyo Kabushiki Kaisha | Liquid jetting apparatus, piezoelectric actuator, and method for producing the liquid jetting apparatus |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6720645B2 (en) | 2002-05-16 | 2004-04-13 | Oki Electric Industry Co., Ltd. | Semiconductor device |
| US7847406B2 (en) | 2002-11-06 | 2010-12-07 | Ricoh Company, Ltd. | Solder alloy material layer composition, electroconductive and adhesive composition, flux material layer composition, solder ball transferring sheet, bump and bump forming process, and semiconductore device |
| JP2007511091A (en) * | 2003-11-05 | 2007-04-26 | カリフォルニア インスティチュート オブ テクノロジー | Method for integrating off-the-shelf chip structures into functional electronic systems |
| JP4854514B2 (en) * | 2003-11-05 | 2012-01-18 | カリフォルニア インスティチュート オブ テクノロジー | Method for integrating off-the-shelf chip structures into functional electronic systems |
| US7781324B2 (en) | 2005-06-30 | 2010-08-24 | Brother Kogyo Kabushiki Kaisha | Method of producing wire-connection structure, and wire-connection structure |
| US7888807B2 (en) | 2005-06-30 | 2011-02-15 | Brother Kogyo Kabushiki Kaisha | Method of producing wire-connection structure, and wire-connection structure |
| EP1976355A2 (en) | 2007-03-28 | 2008-10-01 | Brother Kogyo Kabushiki Kaisha | Method for connecting two objects electrically |
| US8166646B2 (en) | 2007-03-28 | 2012-05-01 | Brother Kogyo Kabushiki Kaisha | Method for connecting two objects electrically |
| US9545015B2 (en) | 2007-03-28 | 2017-01-10 | Brother Kogyo Kabushiki Kaisha | Method for connecting two objects electrically |
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| JP3654113B2 (en) | 2005-06-02 |
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