JP2001249737A - 変換回路 - Google Patents
変換回路Info
- Publication number
- JP2001249737A JP2001249737A JP2000062483A JP2000062483A JP2001249737A JP 2001249737 A JP2001249737 A JP 2001249737A JP 2000062483 A JP2000062483 A JP 2000062483A JP 2000062483 A JP2000062483 A JP 2000062483A JP 2001249737 A JP2001249737 A JP 2001249737A
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- signal group
- cpu
- type
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Landscapes
- Multi Processors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000062483A JP2001249737A (ja) | 2000-03-07 | 2000-03-07 | 変換回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000062483A JP2001249737A (ja) | 2000-03-07 | 2000-03-07 | 変換回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001249737A true JP2001249737A (ja) | 2001-09-14 |
| JP2001249737A5 JP2001249737A5 (enExample) | 2007-04-26 |
Family
ID=18582491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000062483A Abandoned JP2001249737A (ja) | 2000-03-07 | 2000-03-07 | 変換回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001249737A (enExample) |
-
2000
- 2000-03-07 JP JP2000062483A patent/JP2001249737A/ja not_active Abandoned
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5805929A (en) | Multiple independent I/O functions on a PCMCIA card share a single interrupt request signal using an AND gate for triggering a delayed RESET signal | |
| JP2005514595A5 (enExample) | ||
| JP2007095276A (ja) | 直列入/出力インターフェスを有するマルチポートメモリ素子 | |
| KR900005287A (ko) | 데이타 제어 장치 및 그것을 사용하는 시스템 | |
| US6145044A (en) | PCI bus bridge with transaction forwarding controller for avoiding data transfer errors | |
| US6874049B1 (en) | Semaphores with interrupt mechanism | |
| TW482955B (en) | High speed cyclical redundancy check system. | |
| US7054979B2 (en) | Method and apparatus for routing configuration accesses from a primary port to a plurality of secondary ports | |
| JP2001249737A (ja) | 変換回路 | |
| US6529979B1 (en) | Method and apparatus for a high-speed serial communications bus protocol with positive acknowledgement | |
| JP3988340B2 (ja) | 画像処理装置およびそれを備えた複写装置 | |
| US5867673A (en) | Universal operator station module for a distributed process control system | |
| US6216189B1 (en) | Error master detector | |
| US20060136611A1 (en) | Chipset feature detection and configuration by an I/O device | |
| JP2001166643A (ja) | 複写機 | |
| CN109976670B (zh) | 支持数据保护功能的串行非易失性存储控制器设计方法 | |
| JPH0528104A (ja) | マルチプロセツサシステム | |
| US20240004803A1 (en) | Secure element and electronic device including the same | |
| JPH0916411A (ja) | 割込み制御システム | |
| KR100209192B1 (ko) | I2c 버스의 인터럽트 발생장치 | |
| JPH04369064A (ja) | 割込処理制御方法及びその装置 | |
| US9753765B1 (en) | Multi-processor integrated circuits | |
| KR100382466B1 (ko) | 피포를 이용한 비동기 시스템의 인터페이스 | |
| JPH04257957A (ja) | バス切替制御におけるエラー処理方式 | |
| JPS63311469A (ja) | 記憶装置アドレス変換制御方式 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20060324 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070302 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070302 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070302 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20071129 |
|
| A762 | Written abandonment of application |
Free format text: JAPANESE INTERMEDIATE CODE: A762 Effective date: 20080218 |