JP2001249151A - Capacity detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a period to stably detecting capacity by reducing a chip area of a capacity detection circuit and at switching on or resetting a power supply. SOLUTION: A feedback capacitor 3 is connected between an output terminal and a reversing input terminal of an operational amplifier 1, the reversing input terminal being connected to a sensor capacitor 20, and a MOS transistor 5 is also connected in parallel with feedback capacitor 3. When the MOS transistor 5 is turned on at switching on or resetting a power supply, the sensor capacitor 20 is charged quickly via the MOS transistor 5. When the MOS transistor 5 is turned off, a resistance component of a pn-connection between a substrate and a drain of the MOS transistor 5 is connected to a capacitor 3 in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance detecting circuit used in a capacitive sensor device for detecting a physical quantity.

[0002]

2. Description of the Related Art In recent years, for the purpose of miniaturization and cost reduction, various capacitive sensor devices for detecting a physical quantity using micromachine technology have been proposed. This capacitive sensor device detects a change in physical quantity as a change in capacitance. In this case, a capacitance detection circuit as shown in FIG. 15 is used to detect the capacitance.

[0003] This capacitance detection circuit comprises an operational amplifier 1, a DC power supply 2, a capacitor (hereinafter referred to as a feedback capacitance) 3, and a resistor 4. Operational amplifier 1
Are connected to a sensor capacitor 20, and a non-inverting input terminal is connected to a reference power supply 2. A feedback capacitor 3 is connected between the output terminal of the operational amplifier 1 and the inverting input terminal.
Is connected. The sensor capacitance 20 is composed of differential capacitances 20a and 20b whose capacitance values change according to physical quantities. One ends of the capacitors 20a and 20b are commonly connected, and the other ends are connected to DC power supplies 21 and 22, respectively. The voltage of the reference power supply 2 is １ ／ of the difference between the voltages V1 and V2 of the DC power supplies 21 and 22, that is, (V1−V2)
/ 2.

In such a configuration, when the capacitance value of the sensor capacitor 20 changes due to the action of the physical quantity, the charge generated from the sensor capacitor 20 moves to the feedback capacitor 3, whereby the voltage Vo is output from the operational amplifier 1. .

The resistor 4 connected in parallel with the feedback capacitor 3 is necessary for biasing the sensor capacitor 20 to an intermediate potential. The resistor 4 is required to have a high resistance value so that all the electric charges due to the change in the capacitance value of the sensor capacitor 20 are sent to the feedback capacitor 3.

[0006]

In the above-mentioned conventional configuration, if the high-resistance resistor 4 is formed only on the semiconductor substrate by the diffusion layer, a large chip area is required.

In addition, the above configuration has a problem in that it takes time to charge the sensor capacitor 20 at the time of power-on or resetting, and it takes time to detect the capacitance stably. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a capacitance detection circuit having a configuration in which the above-described high-resistance resistor is eliminated.

It is another object of the present invention to shorten the time required to stably detect the capacitance when the power is turned on or at the time of reset.

[0010]

The present invention employs the technical means described in the claims to achieve any of the above objects.

According to the first aspect of the present invention, there is provided an operational amplifier (1) in which a sensor capacitor (20) is connected to an inverting input terminal, and a capacitor (1) is provided between the output terminal and the inverting input terminal of the operational amplifier (1). 3) and a resistance (4) connected in parallel with the capacitor (3) in a capacitance detection circuit between the output terminal and the inverting input terminal of the operational amplifier (1) in parallel with the resistance (4). Transistor (5)
Is connected, and the MOS transistor (5) is turned on to rapidly charge the sensor capacitor (20).

According to the present invention, when the sensor is turned on or reset, the sensor capacitor (20) is rapidly charged, and the time required for detecting the capacity stably can be shortened.

According to the second aspect of the present invention, there is provided an operational amplifier (1) in which a sensor capacitor (20) is connected to an inverting input terminal, and a capacitor (1) is provided between the output terminal and the inverting input terminal of the operational amplifier (1). In the capacitance detection circuit connected to 3), a MOS transistor (5) is connected in parallel with the capacitor (3) between the output terminal and the inverting input terminal of the operational amplifier (1), and the drain of the MOS transistor (5) is connected. The terminal is connected to the inverting input terminal of the operational amplifier (1), and the gate terminal, the source terminal, and the substrate terminal are connected to the output terminal of the operational amplifier (1).

According to the present invention, by utilizing the resistance component of the pn junction formed between the substrate and the drain of the MOS transistor (5), the high resistance (between the output terminal and the inverting input terminal of the operational amplifier (1)) is obtained. 4) can be made unnecessary.

According to the third aspect of the present invention, there is provided an operational amplifier (1) in which a sensor capacitor (20) is connected to an inverting input terminal, and a capacitor (1) is provided between the output terminal and the inverting input terminal of the operational amplifier (1). In the capacitance detection circuit connected to 3), a MOS transistor (5) is connected in parallel with the capacitor (3) between the output terminal and the inverting input terminal of the operational amplifier (1), and the drain of the MOS transistor (5) is connected. The terminal and the source terminal are connected to the inverting input terminal of the operational amplifier (1), and the gate terminal and the substrate terminal are connected to the output terminal of the operational amplifier (1).

Also in the present invention, by using the resistance component of the pn junction formed between the substrate and the drain of the MOS transistor (5), the high resistance (4) between the output terminal and the inverting input terminal of the operational amplifier (1) is obtained. ) Can be eliminated.

According to the fourth aspect of the present invention, the operational amplifier (1) in which the sensor capacitor (20) is connected to the inverting input terminal.
And a MOS transistor (5) connected between the output terminal and the inverting input terminal of the operational amplifier (1).
The drain terminal, the source terminal, and the gate terminal of the OS transistor (5) are connected to the inverting input terminal of the operational amplifier (1), and the substrate terminal is connected to the output terminal of the operational amplifier (1).

According to the present invention, by using the resistance component of the pn junction formed between the substrate and the drain of the MOS transistor (5), the high resistance (between the output terminal and the inverting input terminal of the operational amplifier (1)) is obtained. 4) can be made unnecessary. Further, the capacitor (3) between the output terminal and the inverting input terminal of the operational amplifier (1) can be made unnecessary by the gate capacitance of the MOS transistor (5).

According to the fifth aspect of the present invention, the operational amplifier (1) having the sensor capacitance (20) connected to the inverting input terminal is provided, and the capacitor (1) is provided between the output terminal and the inverting input terminal of the operational amplifier (1). In the capacitance detection circuit connected to 3), a MOS transistor (5) is connected in parallel with the capacitor (3) between the output terminal and the inverting input terminal of the operational amplifier (1), and the drain of the MOS transistor (5) is connected. The terminal is connected to the inverting input terminal of the operational amplifier (1), and the source terminal and the substrate terminal are connected to the output terminal of the operational amplifier (1). When the MOS transistor (5) is turned on, the MOS transistor (5) is connected. When the MOS transistor (5) is turned off, the pn between the substrate and the drain of the MOS transistor (5) is rapidly charged. Resistance component of the coupling is characterized in that it is adapted to be connected in parallel to the capacitor (3).

According to the present invention, when the power is turned on or reset, the sensor capacitor (20) is rapidly charged,
The time until the capacitance can be detected stably can be shortened. Further, by using the resistance component of the pn junction formed between the substrate and the drain of the MOS transistor (5), the high resistance (4) between the output terminal and the inverting input terminal of the operational amplifier (1) is not required. Can be.

According to a sixth aspect of the present invention, a non-inverting amplifier (6) is connected to the output side of the operational amplifier (1), and the output of the non-inverting amplifier (6) is connected to a capacitor (7) or a MOS transistor ( It is characterized in that it is connected to the inverting input terminal of the operational amplifier (1) via the gate capacitance of 8).

According to the present invention, even when the amplitude of the output of the operational amplifier (1) fluctuates greatly, the operational amplifier (1) can be used.
Is transmitted to the inverting input terminal of the operational amplifier (1), the amplitude of the output of the operational amplifier (1) can be suppressed, and a forward current flows through the parasitic diode of the MOS transistor (5). And the diode can always be kept at a high resistance.

It should be noted that MOS is used instead of the capacitor (7).
When the gate capacitance of the transistor (8) is used, a thin and high-quality gate oxide film can be used, so that the area can be reduced as compared with the case where the capacitor (7) is used.

According to the seventh aspect of the present invention, the sensor capacitor (20) is of a variable capacitance type having a vibrator, and a drive signal for vibrating the vibrator has a predetermined amplitude,
It is characterized in that it is converted into a phase shift and applied to the inverting input terminal of the operational amplifier (1) via the capacitor (10) or the gate capacitance of the MOS transistor (11).

According to the present invention, it is possible to prevent the drive signal from leaking to the output of the capacitance detection circuit due to unbalance of the sensor capacitance or parasitic capacitance.

In the invention according to claim 8, the sensor capacitance (20) is of a variable capacitance type to which a carrier is applied, wherein the carrier is converted into a predetermined amplitude and a phase shift, and the capacitor (20) is It is characterized in that the voltage is applied to the inverting input terminal of the operational amplifier (1) via the gate capacitance of the MOS transistor (11).

According to the present invention, it is possible to prevent the carrier wave from leaking to the output of the capacitance detection circuit due to unbalance of the sensor capacitance or parasitic capacitance.

When the gate capacitance of the MOS transistor (11) is used instead of the capacitor (10) in the present invention, a thin and high quality gate oxide film can be used. The area can be made smaller than using the capacitor (10).

According to the ninth aspect of the present invention, the MO connected between the output terminal and the inverting input terminal of the operational amplifier (1).
The S transistor (5) is characterized in that it has a round gate shape with the drain at the center.

According to the present invention, unnecessary leakage due to surface defects can be reduced by hiding the periphery of the drain of the MOS transistor (5) under the gate.

Note that the reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0032]

FIG. 1 shows a configuration of a capacitance detection circuit according to a first embodiment of the present invention.

This capacitance detection circuit comprises an operational amplifier 1, a DC power supply 2, a feedback capacitance 3, a resistor 4,
It comprises an S transistor 5. A sensor capacitor 20 is connected to an inverting input terminal of the operational amplifier 1, and a reference power supply 2 is connected to a non-inverting input terminal. Operational amplifier 1
, A feedback capacitor 3 is connected between the output terminal and the inverting input terminal, and a resistor 4 is connected in parallel with the feedback capacitor 3. Further, a MOS transistor 5 is connected in parallel with the resistor 4. The sensor capacitance 20 is composed of differential capacitances 20a and 20b whose capacitance values change according to physical quantities such as pressure, acceleration, and angular velocity. Capacity 20
a and 20b have one end commonly connected and the other ends connected to DC power supplies 21 and 22, respectively. Note that the reference power source 2
Is set to の of the difference between the voltages V1 and V2 of the DC power supplies 21 and 22, that is, (V1−V2) / 2.

The MOS transistor 5 has a configuration in which the drain terminal is connected to the inverting input terminal of the operational amplifier 1, and the source terminal and the substrate terminal having a substrate potential are connected to the output terminal of the operational amplifier 1. FIG. 2 shows a schematic cross-sectional configuration of the MOS transistor 5, and FIG. 3 shows an equalizing circuit of the MOS transistor 5. In addition, A in FIGS.
B and C indicate connection points of the drain terminal, the source terminal, the gate terminal, and the substrate terminal of the MOS transistor 5, respectively.

The MOS transistor 5 normally functions as a diode 51 as shown in the equalizer circuit of FIG. 3, but operates so that a switch 52 is turned on when a high level signal is applied to the gate. I do.

When power is turned on or reset, etc., FIG.
As shown in FIG.
When a high-level switch control signal for temporarily turning on the S transistor 5 is applied, electric charges move from the output terminal of the operational amplifier 1 to the sensor capacitor 20 via the MOS transistor 5, and the sensor capacitor 20 changes the voltage (V1- V2) /
Start charging at 2.

As a result, the sensor capacitor 20 can be rapidly charged when the power is turned on or reset, and the charging of the charge to the sensor capacitor 20 is completed quickly, and the detection of the sensor capacitor 20 is performed quickly. You can do so.

Normally, a low-level signal is applied to the gate of the MOS transistor 5. In this state,
When the capacitance value of the sensor capacitor 20 changes due to the action of the physical quantity, the electric charge generated from the sensor capacity 20 moves to the feedback capacity 3, whereby the operational amplifier 1 outputs a voltage Vo corresponding to the physical quantity. (Second Embodiment) FIG. 4 shows a configuration of a capacitance detection circuit according to a second embodiment of the present invention.

In this embodiment, the resistor 4 is eliminated from the configuration shown in FIG.
To have it. Therefore, in the MOS transistor 5, the drain terminal is connected to the inverting input terminal of the operational amplifier 1, and the source terminal, the gate terminal, and the substrate terminal are connected to the output terminal of the operational amplifier 1.

Thus, the same function as the resistor 4 shown in FIG. 1 can be provided by utilizing the resistance component of the diode due to the pn junction between the substrate and the drain of the MOS transistor 5. Since the MOS transistor 5 can have a smaller chip area than the case where the resistor 4 is formed of only the diffusion layer on the semiconductor substrate, the chip area of the capacitance detection circuit can be reduced. (Third Embodiment) FIG. 5 shows a configuration of a capacitance detection circuit according to a third embodiment of the present invention.

In this embodiment, the terminal connection portion of the MOS transistor 5 is different from the configuration shown in FIG. That is, the substrate terminal and the gate terminal of the MOS transistor 5 are connected to the output terminal of the operational amplifier 1, and the drain terminal and the source terminal are connected to the inverting input terminal of the operational amplifier 1.

As a result, the same function as the resistor 4 shown in FIG. 1 can be provided by utilizing the resistance component of the diode due to the pn junction between the substrate and the drain and between the substrate and the source of the MOS transistor 5. . (Fourth Embodiment) FIG. 6 shows a configuration of a capacitance detection circuit according to a fourth embodiment of the present invention.

In this embodiment, the feedback capacitor 3 is eliminated from the configuration shown in FIGS. 3 and 4, and the MOS transistor 5 has the functions of the resistor 4 and the feedback capacitor 3. Therefore, the MOS transistor 5
Then, the board terminal is connected to the output terminal of the operational amplifier 1,
The source terminal, the drain terminal, and the gate terminal are connected to the inverting input terminal of the operational amplifier 1, respectively. FIG.
8 shows a schematic cross-sectional configuration of the MOS transistor 5 in this embodiment, and FIG. 8 shows an equalizing circuit thereof.

With such a configuration, a diode (the diode 53 shown in FIG. 8) is formed by the pn junction between the source and the drain of the MOS transistor 5, so that the resistance component can have the same function as the resistor 4. In addition, the same function as the feedback capacitor 3 can be provided by the gate capacitance of the MOS transistor 5 (the capacitor 54 shown in FIG. 8).

Therefore, since the feedback capacitor 3 required in the second and third embodiments can be eliminated, the chip area can be further reduced.

In this embodiment, a configuration in which the feedback capacitor 3 is separately provided may be adopted. (Fifth Embodiment) FIG. 9 shows a configuration of a capacitance detection circuit according to a fifth embodiment of the present invention.

In this embodiment, the configuration shown in FIG. 1 is such that the resistor 4 is eliminated. Since a diode (the diode 51 shown in FIG. 3) is formed by the pn junction between the substrate and the drain in the MOS transistor 5, the same function as the resistor 4 can be provided by the resistance component. Also, at the time of power-on, at the time of reset, or the like, a high-level switch control signal is applied to the gate of the MOS transistor 5 as in the first embodiment, and the sensor capacitor 20 is rapidly charged. Sixth Embodiment FIG. 10 shows a configuration of a capacitance detection circuit according to a sixth embodiment of the present invention.

When the MOS transistor 5 is provided between the output terminal and the inverting input terminal of the operational amplifier 1 as in the above-described first to fifth embodiments, between the input / output terminals of the capacitance detection circuit, that is, the operational amplifier 1 When a voltage exceeding the forward bias of the diode formed in the MOS transistor 5 is applied between the inverting input terminal and the output terminal of the MOS transistor 5, the diode does not operate as a high resistance.

Therefore, in this embodiment, as shown in FIG. 10, a non-inverting amplifier circuit 6 is provided on the output side of the operational amplifier 1, and its output terminal is connected to the inverting input terminal of the operational amplifier 1 via the capacitor 7. Configuration.

As a result, the output of the operational amplifier 1 is amplified by the non-inverting amplifier circuit 6, and the output is input to the inverting input terminal of the operational amplifier 1 via the capacitor 7. For this reason, a charge proportional to the output voltage of the operational amplifier 1 is input to the inverting input terminal of the operational amplifier 1, and fluctuations in the output of the operational amplifier 1 can be suppressed. In this embodiment, the non-inverting amplifier circuit 6 outputs the output voltage Vo of the capacitance detection circuit.
Is output.

The capacitance provided between the output terminal of the non-inverting amplifier circuit 6 and the inverting input terminal of the operational amplifier 1 may be the gate capacitance of the MOS transistor 8 as shown in FIG. In this case, M
As shown in FIG. 11, the OS transistor 8 has a gate terminal connected to the inverting input terminal of the operational amplifier 1, a source terminal, a drain terminal, and a substrate terminal connected to the non-inverting amplifier circuit 6.
, The source terminal, the drain terminal, and the substrate terminal are connected to the inverting input terminal of the operational amplifier 1, and the gate terminal is connected to the output terminal of the non-inverting amplifier circuit 6. You can also.

FIGS. 10 and 11 show this embodiment applied to the second embodiment shown in FIG. 4. Similarly, the first embodiment, the third to fifth embodiments are shown in FIGS. Can also be applied. Seventh Embodiment FIG. 12 shows a configuration of a capacitance detection circuit according to a seventh embodiment of the present invention.

As the capacitance sensor 20 connected to the inverting input terminal of the operational amplifier 1, the movable electrode is constituted by a vibrator as in the case of detecting an angular velocity, and the differential capacitance between the vibrator and two fixed electrodes is detected. (Variable capacity type having a vibrator). In this case, a drive signal for vibrating the vibrator is applied to the vibrator. Also,
There is also a configuration (variable-capacity type in which a carrier is applied) in which a carrier having an opposite phase is applied to the other end of each of the differential capacitors to detect a static capacitance change. When an AC signal such as a drive signal or a carrier wave is used as described above, the drive signal or the carrier wave may leak to the output of the capacitance detection circuit due to the unbalance or the parasitic capacitance of the sensor capacitor 20. This embodiment is designed to solve such a problem.

This embodiment will be described by taking a case where a carrier is applied to the sensor capacitor 20 as shown in FIG. As shown in the figure, carrier waves having opposite phases are applied to the sensor capacitor 20. Due to the application of the carrier wave, electric charges corresponding to the physical quantity move from the sensor capacitor 20 to the feedback capacitor 3, whereby the operational amplifier 1
Outputs a voltage Vo corresponding to the physical quantity.

One carrier is applied to the inverting input terminal of the operational amplifier 1 via the converter 9 and the capacitor 10. The converter 9 converts the carrier into a predetermined amplitude and phase shift with respect to the original signal. As described above, one carrier is converted by the converter 9 so as to have a predetermined amplitude and a phase shift relationship, and is applied to the inverting input terminal of the operational amplifier 1 via the capacitor 10, so that the imbalance of the sensor capacitor 20 and the parasitic The capacitance can prevent the carrier from leaking to the output of the capacitance detection circuit.

It should be noted that the present invention is not limited to the case where a carrier wave is applied to the sensor capacitor 20, and the same applies to a configuration using a movable electrode to which an AC drive signal is applied as the sensor capacitor 20.
In this case, the drive signal is applied to the inverting input terminal of the operational amplifier 1 via the converter 9 and the capacitor 10.

In place of the capacitor 10, FIG.
As shown in (1), the configuration may be such that the gate capacitance of the MOS transistor 11 is used.

FIGS. 12 and 13 show this embodiment applied to the second embodiment shown in FIG. 4. Similarly, the first embodiment, the third to fifth embodiments are shown in FIGS. Can also be applied. (Other Embodiments) The MOS transistor 5 used in the first to seventh embodiments generally has a rectangular gate, but may have another shape. In particular, as shown in FIG. 14, if the gate is formed in a donut shape (round gate shape) with the drain at the center, the peripheral portion of the drain is hidden under the gate, so that a pn junction is formed on the substrate surface. In comparison, unnecessary leaks due to surface defects and the like can be suppressed. Further, since the peripheral length and the junction area can be reduced as compared with the case where the gate is formed in a rectangular shape, the resistance component of the pn junction can be increased.

Further, M in the various embodiments described above.
The OS transistor 5 is not limited to the n-channel type, and may be implemented similarly even if it is a p-channel type.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a capacitance detection circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional configuration diagram of a MOS transistor 5 shown in FIG.

FIG. 3 is an equivalent circuit diagram of the MOS transistor 5 shown in FIG.

FIG. 4 is a diagram illustrating a configuration of a capacitance detection circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a capacitance detection circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of a capacitance detection circuit according to a fourth embodiment of the present invention.

7 is a schematic cross-sectional configuration diagram of the MOS transistor 5 shown in FIG.

8 is an equivalent circuit diagram of the MOS transistor 5 shown in FIG.

FIG. 9 is a diagram illustrating a configuration of a capacitance detection circuit according to a fifth embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration of a capacitance detection circuit according to a sixth embodiment of the present invention.

FIG. 11 is a view showing a modification of the sixth embodiment of the present invention.

FIG. 12 is a diagram illustrating a configuration of a capacitance detection circuit according to a seventh embodiment of the present invention.

FIG. 13 is a view showing a modification of the seventh embodiment of the present invention.

FIG. 14 is a diagram showing an embodiment in which the MOS transistor 5 has a round gate shape centering on the drain.

FIG. 15 is a diagram showing a configuration of a conventional capacitance detection circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Operation amplifier, 2 ... DC power supply, 3 ... Feedback capacity, 4 ... Resistance, 5 ... MOS transistor, 6 ... Non-inverting amplifier circuit, 7 ... Capacitor, 8 ... MOS transistor, 9
... Converter, 10 ... Capacitor, 11 ... MOS transistor.

Continued on the front page F-term (reference) 2F077 HH00 TT06 2G028 AA03 BB06 CG07 DH06 EJ10 MS03 5J069 AA01 AA47 AA48 AC02 CA65 CA92 FA17 FA20 HA10 HA19 HA25 HA29 HA30 HA38 KA11 KA16 KA18 MA11 QA02 FA01 A06 A92 HA19 HA25 HA29 HA30 HA38 HA42 KA11 KA16 KA18 MA11 MN01 NN11 QA02 TA01 TA06

Claims (9)

[Claims] An operational amplifier (1) having a sensor capacitance (20) connected to an inverting input terminal, and a capacitor (3) connected between an output terminal and an inverting input terminal of the operational amplifier (1). In a capacitance detection circuit having a resistor (4) connected in parallel with a capacitor (3), a MOS transistor (5) is connected in parallel with the resistor (4) between an output terminal and an inverting input terminal of the operational amplifier (1). A capacitance detection circuit connected to the MOS transistor (5) to turn on the MOS transistor (5) to rapidly charge the sensor capacitance (20). 2. An operational amplifier (1) having a sensor capacitor (20) connected to an inverting input terminal, and a capacitor (3) connected between an output terminal and an inverting input terminal of the operational amplifier (1). In the capacitance detection circuit, a MOS transistor (5) is connected in parallel with the capacitor (3) between an output terminal and an inverting input terminal of the operational amplifier (1), and a drain terminal of the MOS transistor (5) is connected to the operational amplifier ( A capacitance detection circuit, wherein a substrate terminal connected to the inverting input terminal of (1) and having a gate potential, a source terminal, and a substrate potential is connected to an output terminal of the operational amplifier (1). 3. An operational amplifier (1) having a sensor capacitance (20) connected to an inverting input terminal, and a capacitor (3) connected between an output terminal and an inverting input terminal of the operational amplifier (1). In the capacitance detecting circuit, a MOS transistor (5) is connected in parallel with the capacitor (3) between an output terminal and an inverting input terminal of the operational amplifier (1), and a drain terminal and a source terminal of the MOS transistor (5) are connected. A capacitance detection circuit, wherein a substrate terminal connected to an inverting input terminal of the operational amplifier (1) and having a gate terminal and a substrate potential is connected to an output terminal of the operational amplifier (1). 4. An operational amplifier (1) having a sensor capacitor (20) connected to an inverting input terminal, and a MOS transistor (5) connected between an output terminal and the inverting input terminal of the operational amplifier (1). And the MOS transistor (5)
A drain terminal, a source terminal, and a gate terminal of the operational amplifier (1) are connected to an inverting input terminal of the operational amplifier (1), and a substrate terminal for obtaining a substrate potential is connected to an output terminal of the operational amplifier (1). circuit. 5. An operational amplifier (1) having a sensor capacitance (20) connected to an inverting input terminal, and a capacitor (3) connected between an output terminal and an inverting input terminal of the operational amplifier (1). In the capacitance detection circuit, a MOS transistor (5) is connected in parallel with the capacitor (3) between an output terminal and an inverting input terminal of the operational amplifier (1), and a drain terminal of the MOS transistor (5) is connected to the operational amplifier ( The substrate terminal connected to the inverting input terminal of 1) and having a source potential and a substrate potential is connected to the output terminal of the operational amplifier (1). When the MOS transistor (5) is turned on, the MO transistor is turned on.
The sensor capacitance (20) via an S transistor (5)
Is rapidly charged, and when the MOS transistor (5) is turned off, a resistance component of a pn junction between a substrate and a drain of the MOS transistor (5) is connected in parallel with the capacitor (3). A capacitance detection circuit. 6. A non-inverting amplifier (6) is connected to an output side of the operational amplifier (1), and the non-inverting amplifier (6) is connected to the operational amplifier (1).
2. An output of the operational amplifier (1) is connected to an inverting input terminal of the operational amplifier (1) via a capacitor (7) or a gate capacitance of a MOS transistor (8).
6. The capacitance detection circuit according to any one of items 5 to 5. 7. The sensor capacity (20) is a variable capacity type having a vibrator, and a drive signal for vibrating the vibrator is converted into a predetermined amplitude and a phase shift, and a capacitor (10) is provided. 6. The capacitor according to claim 1, wherein the voltage is applied to an inverting input terminal of the operational amplifier (1) via a gate capacitance of a MOS transistor (11). Detection circuit. 8. The sensor capacitance (20) is of a variable capacitance type to which a carrier is applied, wherein the carrier is converted into a predetermined amplitude and a phase shift, and a capacitor (10) or a MOS transistor (11). The capacitance detection circuit according to claim 1, wherein the voltage is applied to an inverting input terminal of the operational amplifier (1) via the gate capacitance. 9. The MOS transistor (5) connected between an output terminal and an inverting input terminal of the operational amplifier (1) has a round gate shape centered on a drain. 9. The capacitance detection circuit according to any one of 1 to 8.