JP2001245007A - Receiver with direct current offset correction function and method for correcting direct current offset in receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the sensitivity deterioration of a receiver by accurately correcting a baseband direct current offset voltage. SOLUTION: A radio signal from an antenna 1 is converted into an intermediate frequency signal by a high frequency block 2, transmitted to an orthogonal mixer 8 through an impedance compensation block 7, converted into a baseband signal and transmitted to a baseband signal processing block 10. Direct current offset voltage detection blocks 16a and 16b detect a direct current offset voltage existing in the block 10 on the basis of an output of an orthogonal modulator 11 at a time when the block 2 is off, and direct current offset voltage cancel control blocks 17a and 17b correct the direct current offset voltage based on the detected offset voltage. The block 7 compensates the fluctuation of output impedance at on/off of the block 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio equipment using a high-frequency block, such as a PHS or a portable telephone, in a mobile communication system, and more particularly to a correction of a DC offset of a received signal.

[0002]

2. Description of the Related Art In recent years, a zero-IF receiver typified by a direct conversion receiver has attracted attention as a means for realizing miniaturization and low cost of a wireless terminal.

A first conventional example will be described based on a general direct conversion receiver shown in FIG.
The wireless signal is input to the quadrature mixers 102a and 102b via the antenna 100 and the low noise amplifier 101, respectively. Then, in the mixer 102b, the local oscillator 103
, And multiplied by the quadrature component generated by the 90-degree phase shifter 104 in the mixer 102a, and output as I and Q baseband signals. Thereafter, the band is limited by the low-pass filters 105a and 105b of the baseband signal processing block 110, the signals are amplified by the amplifiers 106a and 106b, and the analog signals are converted into digital signals by the A / D converters 107a and 107b. Then data processing block 1
At 08, demodulation is performed.

[0004] In such a direct conversion receiving system, a DC offset voltage is generated in the baseband signal processing block 110. The main causes of the generation of the DC offset voltage are the self-mixing of the quadrature mixer and the mismatch between the elements constituting the baseband signal processing block.

The reason why the DC offset voltage is generated by the self-mixing of the quadrature mixer is as follows. The wireless signal and the local oscillation frequency of the local oscillator 103 are substantially equal,
In a direct conversion receiver that performs quadrature demodulation directly to baseband, the input level of the LO ports 102c and 102d of the integrated quadrature mixer 102 is normally 100
More than dBu VEMF is required. L of the quadrature mixer 102
Isolation due to spatial coupling between the ports from the O ports 102c and 102d to the RF boat 102e is 20
About 40 to 40 dB can be obtained. Therefore, RF port 1
02e is always 60 from LO port 102c, 102d
Local oscillator 10 of dBuVEMF to 80dBuVEMF
The output signal of No. 3 is leaking. Further, the LO ports 102c and 102d and the RF port 102
The isolation and phase between d changes. Therefore, the phase detection signal of the quadrature mixer 102 due to the self-mixing includes a DC offset caused by the leakage.

In the example of FIG. 6, the DC offset voltage generated in the baseband signal processing block 110 is corrected by providing capacitors 109a and 109b for cutting DC between the blocks.

[0007] Such a problem relating to the DC offset is caused not only in the above-mentioned zero-IF receiver, but also in a so-called superheterodyne receiving system in which a received frequency is once converted to an intermediate frequency and then converted to a baseband again. Occurs similarly. A receiver shown in FIG. 7 will be described as a second conventional example (Japanese Patent Laid-Open No. 10-936).
No. 47). The radio signal received by the antenna 200 passes through a switch block 201 that cuts off the radio signal, is amplified by a low noise amplifier 202, is mixed with a signal from a local oscillator 203 by a mixer 204, and an unnecessary wave is removed by a filter 205. Further, a signal from the local oscillator 206 having substantially the same frequency as the intermediate frequency and a signal obtained by shifting the output thereof by the phase shifter 207 and the quadrature mixer 20
8 and converted into I and Q baseband signals in orthogonal relation. Baseband signal processing block 2
In step 09, unnecessary bands are removed by band limitation by the channel selection filters 210a and 210b.
At 1a and 211b, the received signal is amplified to a desired level. Then, quantization is performed by the AD converters 212a and 212b, and detection and demodulation are performed by the detection block 213.

In this receiver as well, a DC offset voltage is generated as in the first example, but its correction is made by a digital signal processing block 214 by an AD converter 212.
The DC offset voltage is detected and held from the outputs of the signals a and 212b, converted into an analog value by the DA converters 215a and 215b, output, and subtracted by the subtracters 216a and 216b.

DC offset voltage correction FIGS. 7 and 8
This will be described in more detail based on FIG. 8 shows a switch block 201 for cutting off the radio signal of FIG. 2
01a and 201b are switches, and 201c is a terminator. When performing DC offset voltage correction of the I and Q baseband signals of the baseband signal processing block, the switch 201a of the switch block 201 causes the antenna 200
Release the low noise amplifier 202 and switch 201
At b, the input of the low-noise amplifier is terminated by the terminator 201c to create a non-input state, and the DC offset voltage generated in the baseband signal processing unit is held as digital information. Then, at the time of reception, this digital offset value is converted into an analog amount by the DA converters 215a and 215b, sent to the subtracters 216a and 216b, and the DC offset voltage is corrected.

[0010]

However, in the first prior art, when the receiver is started after the power supply is cut off during the intermittent receiving operation, the DC voltage across the capacitive coupling is stable and the voltage can be received. Time constant becomes longer in proportion to the coupling capacitance value. In a signal format system having a long frame length such as a pager, a sufficient start-up time can be secured when the receiver is turned off at the time of intermittent reception operation, but the frame length of the TDMA system represented by PDC, PHS, etc. In a short signal format system, there is a problem that a start-up time from power-off during intermittent reception operation cannot be secured.

In the second conventional example, when the DC offset voltage of the baseband signal processing block is corrected, the antenna 200 and the low noise amplifier 202 are released by the switch 201a of the switch block 201, and the low noise amplifier 202 is changed by the switch 201b. Noise amplifier input is terminator 201c
And terminate the wireless signal. But T
In the antenna switch used in the DMA system,
The input-output isolation at the time of release can be secured only about 30 dB, and it is difficult to completely cut off the radio signal even if the input of the low-noise amplifier 202 is terminated. However, there is a problem that the receiving sensitivity is deteriorated.

An object of the present invention is to solve such a conventional problem, and an object of the present invention is to correct a DC offset voltage of a baseband signal processing block correctly without deteriorating a starting characteristic.

[0013]

The invention according to claim 1 of the present application comprises a receiving section for receiving a radio signal, a frequency converting section for converting a received signal input from the receiving section into a baseband signal, A DC offset detection unit that detects a DC offset generated in the baseband signal in a non-input state of the received signal; and a unit that corrects the DC offset generated in the baseband signal based on the detected DC offset. In a receiver having a DC offset correction function, an impedance compensator for maintaining a constant output impedance of a reception signal processor for processing the reception signal is provided at a stage preceding the frequency converter.

According to a second aspect of the present invention, in the receiver with the DC offset correction function according to the first aspect, the supply of power to the receiving unit is cut off to set the received signal in a non-input state. Things.

According to a third aspect of the present invention, in the receiver having the DC offset correction function according to the first or second aspect, the impedance compensating unit is provided when the output impedance of the received signal processing unit changes. The first pseudo load corresponding to the change is electrically connected.

According to a fourth aspect of the present invention, in the receiver with the DC offset correction function according to the third aspect, the connection of the first pseudo load is performed by using a power supply control signal for the receiving unit. It is what you do. As a result, a circuit for generating a control signal for the circuit to which the pseudo load is added can be omitted.

According to a fifth aspect of the present invention, in the receiver having the DC offset correction function according to the first or second aspect, the impedance compensator is constituted by a buffer amplifier. Since the buffer amplifier is easy to integrate,
The size can be reduced.

According to a sixth aspect of the present invention, in the receiver with the DC offset correction function according to the first or second aspect, the impedance compensating unit is configured to change the output compensating unit when the output impedance of the received signal processing unit changes. In this configuration, a second pseudo load equivalent to the output impedance of the reception signal processing unit is switched and connected. This simplifies the adjustment of the dummy load.

According to a seventh aspect of the present invention, in the receiver with a DC offset correction function according to the sixth aspect, the connection of switching the pseudo load is performed using a power supply control signal for the receiving unit. Things. As a result, a circuit for generating a control signal for the circuit to which the pseudo load is added can be omitted.

[0020] The invention according to claim 8 of the present application is directed to a DC offset in a receiver comprising a receiving section for receiving a radio signal, and a frequency converting section for converting a received signal input from the receiving section into a baseband signal. A correction method,
The receiver further includes an impedance compensating unit that keeps an output impedance of a reception signal processing unit that processes the reception signal at a stage preceding the frequency conversion unit, and sets the reception signal from the reception unit to a non-input state. And detecting a DC offset generated in a baseband signal based on the output of the frequency conversion unit in the non-input state, and when the reception signal is not input, based on the detected DC offset, Correcting the DC offset generated in the band signal and setting the band signal to the reception state.

According to a ninth aspect of the present invention, in the DC offset correction method for a receiver according to the eighth aspect, the step of setting a reception signal from the receiving unit to a non-input state is performed by using a power supply to the receiving unit. This includes shutting off the supply.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing one embodiment of the present invention. In the receiver shown in FIG. 1, the radio signal from the antenna 1 is converted into an intermediate frequency signal by the high frequency block 2 and sent to the quadrature mixer 8 via the impedance compensation block 7. The high-frequency block 2 includes a low-noise amplifier 3 for amplifying a radio signal, a first mixer 4 for obtaining an intermediate frequency signal from the amplified radio signal and a local oscillation signal of a first local oscillator 5, and a power supply 6. , The operation is controlled on / off. The impedance compensation block 7 has a function of keeping the output impedance constant irrespective of whether the high-frequency block 2 is on or off, and will be described later in detail.

The quadrature mixer 8 obtains a baseband signal from the intermediate frequency signal and the quadrature phase output signal. The obtained baseband signal is sent to the baseband signal processing block 10. The second local oscillator 9 outputs a signal having a frequency substantially equal to the intermediate frequency signal, and the output and a signal whose phase is shifted by 90 degrees by the phase shifter 9a are sent to the quadrature mixer 8.

The baseband signal processing block 10 includes low-pass filters 10a and 10b, amplifiers 10c and
d, including subtractors 10e and 10f,
The output of f is sent to quadrature modulator 11. Subtractor 10
Reference numerals e and 10f denote DC offset corrections based on signals from the DC offset voltage cancel control blocks 17a and 17b.

The quadrature modulator 11 quadrature-modulates the corrected baseband signal with the output of the third local oscillator 12, and outputs the band-pass filter 13,
The signal is sent to the demodulator 15 via the limiter amplifier 14. The output of the quadrature modulator 11 is sent to DC offset voltage detection blocks 16a and 16b, and the DC offset voltage existing in the baseband signal processing block is detected.

Next, the correction of the DC offset will be described. DC offset voltage detection blocks 16a, 16
“b” detects the DC offset voltage existing in the baseband signal processing block based on the output of the quadrature modulator 11 when the input signal to the quadrature mixer 8 is in a non-input state. The state in which the input signal to the quadrature mixer 8 is not input is created by turning off the high-frequency block under the control of the power supply 6, and the offset voltage obtained in that state is used as the DC offset voltage cancellation control blocks 17a and 17b.
Sent to and retained. The DC offset voltage cancellation control blocks 17a and 17b control signals sent to the subtracters 10e and 10f based on the held offset voltage, and correct the DC offset voltage existing in the baseband signal processing block. The timing for operating the DC offset voltage detection blocks 16a and 16b is as follows.
It may be at the time of shipment, when the power of the receiver is turned on, or at a predetermined cycle after the power of the receiver is turned on. Also, subtracters 10e, 10f
Is provided after the amplifiers 10c and 10d,
It may be provided before the amplifiers 10c and 10d, or may be provided before the low-pass filters 10a and 10b.

The DC offset correction signal can also be obtained by forming a negative feedback loop with no input signal to the quadrature mixer 8. Specifically, the correction signal sent from the DC offset voltage cancellation control blocks 17a, 17b to the subtracters 10e, 10f is controlled so that the DC offset voltage detected by the DC offset voltage detection blocks 16a, 16b becomes zero. Holding the correction signal such that the DC offset voltage becomes zero,
This configuration is used as a correction signal at the time of normal reception.

Next, the operation of the impedance compensation block 7 will be described. When the power supply 6 of the high-frequency block is turned on and off, the output impedance of the first mixer 4 changes. FIG. 2 shows the output impedance of the first mixer 4 in a Smith chart. FIG. 2A shows the case where the power of the high frequency block is turned on, and FIG. 2B shows the case where the power of the mixer high frequency block is turned off.

If the impedance compensating block 7 is not provided, the impedance change becomes the input impedance variation of the quadrature mixer 8 as it is. When the impedance compensation block 7 is provided, the output impedance fluctuation of the first mixer 4 can be suppressed, and the input impedance of the quadrature mixer 8 can be kept constant.

The input levels of the LO ports 8b and 8c of the quadrature mixer 8 formed as an integrated circuit are usually 100 dBuVE.
MF or more is required, and the isolation due to spatial coupling between the ports from the LO ports 8b and 8c of the quadrature mixer 8 to the RF port 8a is about 20 to 40 dB. Therefore, the RF port 8a is always connected to the LO ports 8b and 8c from the 60 dBu VEMF to the 80 dBu VE.
This means that the output signal of the local oscillator 9 of the MF is leaking.

Therefore, when the impedance compensation block 7 is not provided, the input impedance of the quadrature mixer 8 changes, so that the coupling state between the LO ports 8b and 8c of the quadrature mixer 8 and the RF port 8a changes, and the local oscillator 9 Changes the amount of output signal leakage. And RF
Since the signals at the port 8a and the LO ports 8b and 8c have the same frequency, the quadrature mixer 8 performs a phase detection operation by self-mixing and outputs a DC component corresponding to the phase difference to the baseband processing block 10, and The DC offset voltage of the baseband signal processing block 10 changes between the ON state and the OFF state of the second power supply 6.

In this case, when the high-frequency block power supply 6 is off, the DC offset voltage existing in the baseband signal processing block 10 is detected by the DC offset voltage detection block 1.
6a and 16b, and based on the detected values, the DC offset voltage cancellation control blocks 17a and 17b subtract the subtracters 10e and 1b of the baseband signal processing block 10.
Even if the DC offset voltage is corrected using 0f, the DC offset voltage of the baseband signal processing block 10 is not accurately corrected in the reception state where the power supply 6 of the high frequency block is turned on.

However, when the impedance compensating block 7 is provided, since the input impedance of the quadrature mixer 8 does not change, the LO port 8b,
The spatial coupling state between the RF port 8c and the RF port 8a does not change, the output signal leakage of the local oscillator 9 is kept constant, the phase detection amount does not change due to the self-mixing of the quadrature mixer 8, and the power supply of the high-frequency block Irrespective of ON / OFF of 6, the DC offset voltage of the baseband signal does not change.

Therefore, the DC offset voltage present in the baseband signal processing block 10 is detected by the DC offset voltage detection blocks 16a and 16b when the power supply 6 of the high frequency block is off, and the DC offset voltage is detected based on the detected value. Cancel control blocks 17a, 17b
In the subtractor 10e of the baseband signal processing block 10,
Even if the DC offset voltage is corrected using 10f, the correction of the DC offset voltage of the baseband signal processing block 10 is correctly performed.

Although the high-frequency block is turned off under the control of the power supply 6, the input signal to the quadrature mixer 8 is set to a non-input state.
The same applies to the case where on / off control of the oscillation signal is performed.

Next, the configuration of the impedance compensation block 7 will be described with reference to FIGS. The same parts as those in FIG. 1 are denoted by the same reference numerals.

FIG. 3 shows a first configuration example of the impedance compensating block 7. When the output impedance of the high-frequency block 2 changes, a means for electrically connecting a first pseudo load corresponding to the change is provided. I am taking. Specifically, it is composed of a resistor 7a as a first pseudo load, a resistor 7d and a diode 7c for controlling the first pseudo load, and DC cut capacitors 7b, 7e and 7f.

Next, the operation of the first configuration example will be described. When the power supply 6 of the high-frequency block is in the ON state, the control terminal 7g for controlling the resistor 7a, which is the first pseudo addition, is set to “HI”, so that the first mixer 4
The effect of the resistor 7a, which is a pseudo load added to the output, can be ignored. When the power supply 6 of the high-frequency block is in the off state, the control terminal 7g is set to "LOW" so that the impedance is determined by the impedance of the output of the first mixer 4 and the resistor 7a which is a pseudo load. This impedance depends on the power supply 6 of the high-frequency block.
Is adjusted by the value of the resistor 7d so as to be the output impedance of the first mixer 4 at the time of turning on. The level of the control terminal 7g can be controlled by connecting the terminal 7g to the power supply 6 of the high frequency block.

FIG. 4 shows a second configuration example of the impedance compensation block 7. The impedance compensation block 7 has a function of maintaining the output impedance of the high-frequency block 2 constant by being constituted by a buffer amplifier.

A buffer amplifier constituted by a differential amplifier is connected to the output of the first mixer 4 provided in the high frequency block 2. The differential amplifier includes transistors 7h, 7i,
7j, resistors 7m, 7l, 7k, a current source 7n, and a reference power source 7o. The transistor 7j works as a common base amplifier, and the resistor 7k works as a load for a differential amplifier. The change in the output impedance of the first mixer 4 due to the turning on and off of the power supply 6 of the high-frequency block 2 is transmitted to the base 7h of the differential amplifier, but is not transmitted to the differential amplifier output 7q, and has a constant output impedance. The buffer amplifier is not limited to the above-described differential amplifier circuit, but may have any circuit configuration as long as it buffers input impedance fluctuations and keeps output impedance constant.

FIG. 5 shows a third example of the configuration of the impedance compensating block 7, in which a second pseudo load is connected using the signal changeover switch 7r when the power of the high frequency block 2 is off. The second dummy load is constituted by a third mixer 7s having the same configuration as the first mixer, and is always supplied with power.

When the power supply 6 of the high frequency block is on, the impedance compensation block of FIG. 5 switches the signal changeover switch 7r to the first mixer 4 of the high frequency block 2.
The output and the quadrature mixer 8 are connected. When the output is off, the signal changeover switch 7r opens the connection between the first mixer 4 output of the high-frequency block 2 and the quadrature mixer 8, and the third mixer 7s in the power-on state And the quadrature mixer 8. Therefore, regardless of whether the power supply 6 of the high-frequency block 2 is on or off, the mixers 4 and 7 s in the power-on state are connected to the input of the quadrature mixer 8, and the output impedance of the high-frequency block 2 is kept constant.

[0043]

As is apparent from the above description, an impedance compensator for maintaining a constant output impedance of a received signal processing unit for processing a received signal is provided before the frequency converter for converting the received signal to a baseband signal. Since it is provided, there is an excellent effect that the DC offset voltage generated in the baseband section can be corrected correctly and good reception performance can be obtained.

[Brief description of the drawings]

FIG. 1 shows a receiver with a DC offset correction function according to an embodiment of the present invention.

FIG. 2 is a Smith chart showing the output impedance of the mixer of FIG. 1;

FIG. 3 shows an example in which an impedance compensation block is configured by a first pseudo load.

FIG. 4 is an example in which the impedance compensation block is configured by a buffer amplifier.

FIG. 5 is an example in which an impedance compensation block is configured by a second pseudo load.

FIG. 6: General direct conversion receiver

FIG. 7 is a conventional example of a receiver with a DC offset correction function.

FIG. 8 is an example of a switch block in the receiver of FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Antenna 2 ... High frequency block 3 ... Low noise amplifier 4 ... First mixer 5 ... First local oscillator 6 ... Power supply of high frequency block 7 ... Impedance compensation block 8 Quadrature mixer 8a RF input port 8b, 8c LO input port 9 Second local oscillator 9a Phase shifter 10 Baseband signal processing block 10e, 10f ... Subtractor 11 Quadrature modulator 12 Third local oscillator 12a Phase shifter 13 Bandpass filter 14 Limiter amplifier 15 Demodulator 16a 16b: DC offset voltage detection block 17a, 17b: DC offset voltage cancel control block

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04L 27/38 H04L 27/00 G (72) Inventor Takashi Ui 4-3 Tsunashimahigashi, Kohoku-ku, Yokohama-shi, Kanagawa-ken No. 1 Matsushita Communication Industrial Co., Ltd. F term (reference) 5K004 AA01 AA05 AA08 BD01 FH03 JH02 5K020 AA08 DD05 EE05 FF00 LL06 5K029 AA04 DD05 HH08 HH13

Claims (9)

[Claims] A receiving unit that receives a radio signal; a frequency converting unit that converts a received signal input from the receiving unit into a baseband signal; and a direct current generated in a baseband signal in a non-input state of the received signal. A DC offset detection unit that detects an offset; and a unit that corrects a DC offset generated in a baseband signal based on the detected DC offset. A receiver provided with a DC offset correction function, which is provided at an earlier stage to maintain an impedance compensator for keeping the output impedance of the reception signal processor for processing the reception signal constant. 2. The receiver with a DC offset correction function according to claim 1, wherein the supply of power to the receiving section is cut off so that the received signal is in a non-input state. 3. The apparatus according to claim 1, wherein said impedance compensator electrically connects a first dummy load corresponding to the change when the output impedance of said received signal processor changes. 3. The receiver with a DC offset correction function according to 1 or 2. 4. The receiver with a DC offset correction function according to claim 3, wherein the connection of the first pseudo load is performed by using a power supply control signal for the receiving unit. 5. The receiver with a DC offset correction function according to claim 1, wherein said impedance compensator comprises a buffer amplifier. 6. The impedance compensator switches and connects a second dummy load equivalent to the output impedance of the received signal processing unit when the output impedance of the received signal processor changes. The receiver with a DC offset correction function according to claim 1 or 2. 7. The receiver with a DC offset correction function according to claim 6, wherein the switching connection of the pseudo load is performed by using a power supply control signal for the receiving unit. 8. A method for correcting a DC offset in a receiver, comprising: a receiver for receiving a radio signal; and a frequency converter for converting a received signal input from the receiver into a baseband signal. Further comprises an impedance compensating unit for maintaining the output impedance of the received signal processing unit for processing the received signal constant at a stage preceding the frequency conversion unit, and setting the received signal from the receiving unit to a non-input state. Detecting a DC offset generated in a baseband signal based on an output of the frequency conversion unit in the non-input state; and detecting a baseband signal based on the detected DC offset when the received signal is not input. Correcting the generated DC offset to make it in a receiving state. 9. The method according to claim 8, wherein the step of setting the received signal from the receiving unit to a non-input state includes shutting off the supply of power to the receiving unit.