JP2001244383A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001244383A JP2001244383A JP2000052810A JP2000052810A JP2001244383A JP 2001244383 A JP2001244383 A JP 2001244383A JP 2000052810 A JP2000052810 A JP 2000052810A JP 2000052810 A JP2000052810 A JP 2000052810A JP 2001244383 A JP2001244383 A JP 2001244383A
- Authority
- JP
- Japan
- Prior art keywords
- group
- bis
- lead frame
- silane coupling
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、耐半田性に優れた
半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having excellent solder resistance.
【０００２】[0002]
【従来の技術】ＩＣ、ＬＳＩ等の半導体素子は、熱硬化
性樹脂組成物であるエポキシ樹脂組成物で、主に封止さ
れ半導体装置とされている。近年の電子機器の小型化、
軽量化、高性能化の市場動向において、半導体素子の高
集積化が年々進み、又半導体装置の表面実装化が促進さ
れるなかで、半導体装置への要求は益々厳しいものとな
ってきている。特に半導体装置の表面実装化が一般的に
なってきている現状では、吸湿した半導体装置が半田処
理時に高温にさらされ、気化した水蒸気の爆発的応力に
より半導体装置にクラックが発生したり、或いは半導体
素子やリードフレームと樹脂組成物の硬化物との界面に
剥離が発生することにより、電気的信頼性を大きく損な
う不良が生じ、これらの不良の防止、即ち耐半田性の向
上が大きな課題となっている。2. Description of the Related Art Semiconductor devices such as ICs and LSIs are mainly encapsulated with an epoxy resin composition, which is a thermosetting resin composition, to form a semiconductor device. Recent downsizing of electronic devices,
In the market trend of lighter weight and higher performance, demands for semiconductor devices are becoming more and more severe as semiconductor devices become more highly integrated year by year and surface mounting of semiconductor devices is promoted. In particular, in the current situation where surface mounting of semiconductor devices is becoming common, a semiconductor device that has absorbed moisture is exposed to a high temperature during soldering, and cracks occur in the semiconductor device due to the explosive stress of vaporized water vapor. The occurrence of peeling at the interface between the element or the lead frame and the cured product of the resin composition causes defects that greatly impair the electrical reliability, and prevention of these defects, that is, improvement of solder resistance has become a major issue. ing.
【０００３】耐半田性を向上させる手段として、種々の
提案がなされており、代表的なものとしては、（１）エ
ポキシ樹脂組成物に低粘度の樹脂成分を用いて無機充填
材を高充填化し、樹脂成分を減少させて、エポキシ樹脂
組成物の硬化物を低熱膨張化、低吸湿化させる。（２）
吸湿性が少なく可撓性を有する樹脂の使用等による樹脂
組成物での改善が行われている。しかし低粘度樹脂成分
として用いる低粘度のエポキシ樹脂や結晶性エポキシ樹
脂、硬化剤としての低粘度のフェノール樹脂等は一般的
に低分子量であり、このため成形時の加熱により３次元
化して得られる架橋構造の架橋密度は低くなり、機械的
強度や熱時弾性率が低い硬化物となるため、金型からの
離型時に硬化物が金型に付着したり、或いは成形品の割
れ・欠けが発生する等の離型性に劣るという欠点があ
り、半導体装置の改良として十分に満足できるものでは
ない。[0003] Various means have been proposed as means for improving the soldering resistance. Representative examples are (1) a method of using a low-viscosity resin component in an epoxy resin composition to highly fill an inorganic filler. By reducing the resin component, the cured product of the epoxy resin composition has low thermal expansion and low moisture absorption. (2)
Improvements have been made in resin compositions by using resins having low hygroscopicity and having flexibility. However, low-viscosity epoxy resins and crystalline epoxy resins used as low-viscosity resin components, and low-viscosity phenolic resins as curing agents generally have low molecular weights, and are thus obtained by heating to three-dimensionality during molding. The crosslinked density of the crosslinked structure is low, and the cured product has low mechanical strength and low elasticity when heated.Therefore, the cured product adheres to the mold when it is released from the mold, or cracks or chips in the molded product. There is a drawback that the releasability is poor such as generation, and it is not sufficiently satisfactory as an improvement of a semiconductor device.
【０００４】耐半田性を向上させるために、半導体素子
に予めエポキシ樹脂組成物の硬化物との密着性に優れた
ポリイミド樹脂を塗布したり、或いはエポキシ樹脂組成
物の硬化物との密着性に優れたＬｅａｄ Ｏｎ Ｃｈｉ
ｐテープを設ける等のことによる改良や、封止前の半導
体素子にプラズマ処理を施し密着性を付与する等の手法
が実用化されているが、十分な密着性付与と耐半田性が
得られなかったり、或いはは処理装置自体が高価である
といった問題もあり、より簡便に耐半田性を向上させる
手法の開発が望まれていた。In order to improve the solder resistance, a semiconductor element is coated in advance with a polyimide resin having excellent adhesion with a cured product of an epoxy resin composition, or the adhesiveness with a cured product of an epoxy resin composition is improved. Excellent Lead On Chi
Improvements such as the provision of a p-tape, and methods of applying plasma treatment to a semiconductor element before encapsulation to impart adhesiveness have been put to practical use. However, sufficient adhesion and solder resistance can be obtained. There is also a problem that the processing apparatus itself is expensive, or there is a problem that the processing apparatus itself is expensive. Therefore, it has been desired to develop a method for easily improving the solder resistance.
【０００５】[0005]
【発明が解決しようとする課題】本発明は、耐半田性及
び電気的信頼性に優れた半導体装置を提供するものであ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having excellent solder resistance and electrical reliability.
【０００６】[0006]
【課題を解決するための手段】本発明は、リードフレー
ムに搭載された半導体素子を熱硬化性樹脂組成物で封止
してなる半導体装置において、予めγ―（２―アミノエ
チル）アミノプロピルトリメトキシシラン、１，６―ビ
ス（トリメトキシシリル）ヘキサン、ビス（３―トリメ
トキシシリル）アミン、１，３，５−トリス（トリメト
キシシリルプロピル）イソシアヌレート、（アミノエチ
ルアミノメチル）フェネチルトリメトキシシラン、ビス
［３―（トリメトキシシリル）プロピル］エチレンジア
ミン、ビス（３―トリエトキシシリルプロピル）テトラ
スルファン、一般式（１）で示されるポリエチレンイミ
ン変性シランカップリング剤、一般式（２）で示される
ポリエーテル変性シランカップリング剤から選ばれる一
種以上を沸点１５０℃以下の有機溶媒で希釈した溶液で
処理されたリードフレーム、又は半導体素子とリードフ
レームを用いることを特徴とする半導体装置である。SUMMARY OF THE INVENTION The present invention relates to a semiconductor device having a semiconductor element mounted on a lead frame sealed with a thermosetting resin composition. Methoxysilane, 1,6-bis (trimethoxysilyl) hexane, bis (3-trimethoxysilyl) amine, 1,3,5-tris (trimethoxysilylpropyl) isocyanurate, (aminoethylaminomethyl) phenethyltrimethoxy Silane, bis [3- (trimethoxysilyl) propyl] ethylenediamine, bis (3-triethoxysilylpropyl) tetrasulfane, a polyethyleneimine-modified silane coupling agent represented by the general formula (1), represented by the general formula (2) One or more selected from the polyether-modified silane coupling agents shown ℃ is a semiconductor device characterized by using the following lead frame treated with diluted solution in an organic solvent, or a semiconductor element and the lead frame.
【化３】 （Ｒ1は炭素数１〜１０のアルコキシ基、Ｒ2は炭素数１
〜１０のアルキル基である。ｎは１〜３の整数、Ｒ3は
水素原子、フェニル基、炭素数１〜１０のアルキル基、
又はアミノ基であり、ｍは１〜５の整数。ｑは平均値で
１〜１０の正数）Embedded image (R 1 is an alkoxy group having 1 to 10 carbon atoms, R 2 is an alkoxy group having 1 carbon atom
10 to 10 alkyl groups. n is an integer of 1 to 3, R 3 is a hydrogen atom, a phenyl group, an alkyl group having 1 to 10 carbon atoms,
Or an amino group, and m is an integer of 1 to 5. q is an average and a positive number of 1 to 10)
【０００７】[0007]
【化４】 （Ｒ4は炭素数１〜１０のアルコキシ基、Ｒ5は炭素数１
〜１０のアルコキシ基、又は炭素数１〜１０のアルキル
基。Ｒ6は炭素数１〜１０のアルキレン基である。Ｒ7は
グリシジルエーテル基、メルカプト基、アミノ基、ビニ
ル基、アクリル基、又はメタクリル基である。ｎは平均
値で１〜３の正数。ｍ＋ｑは平均値で１〜１０の正数で
ある）Embedded image (R 4 is an alkoxy group having 1 to 10 carbon atoms, and R 5 is an alkoxy group having 1 carbon atom.
An alkoxy group having 10 to 10 or an alkyl group having 1 to 10 carbon atoms. R 6 is an alkylene group having 1 to 10 carbon atoms. R 7 is a glycidyl ether group, a mercapto group, an amino group, a vinyl group, an acryl group, or a methacryl group. n is an average value and a positive number of 1 to 3. m + q is a positive number from 1 to 10 on average)
【０００８】[0008]
【発明の実施の形態】本発明で用いられるシランカップ
リング剤としては、特に半導体素子や金属リードフレー
ムとの反応性に優れているγ―（２―アミノエチル）ア
ミノプロピルトリメトキシシラン、１，６―ビス（トリ
メトキシシリル）ヘキサン、ビス（３―トリメトキシシ
リル）アミン、１，３，５−トリス（トリメトキシシリ
ルプロピル）イソシアヌレート、（アミノエチルアミノ
メチル）フェネチルトリメトキシシラン、ビス［３―
（トリメトキシシリル）プロピル］エチレンジアミン、
ビス（３―トリエトキシシリルプロピル）テトラスルフ
ァン、一般式（１）で示されるポリエチレンイミン変性
シランカップリング剤、一般式（２）で示されるポリエ
ーテル変性シランカップリング剤から選ばれる１種以上
のシランカップリング剤が好ましい。有機溶媒で希釈す
る濃度については、特に限定しないが好ましくは０．０
５〜２重量％、更に好ましくは０．１〜１重量％であ
る。０．０５重量％未満だと、半導体素子、リードフレ
ームの処理が不十分で本来の密着性の付与、耐半田性の
向上が得られず、２重量％を越えると十分な密着性の付
与による耐半田性は得られるが、処理コストが高く、更
に処理した後にカップリング剤同士の縮合物が付着し白
点が発生し電気的信頼性が低下するので好ましくない。BEST MODE FOR CARRYING OUT THE INVENTION As the silane coupling agent used in the present invention, γ- (2-aminoethyl) aminopropyltrimethoxysilane, which has excellent reactivity with a semiconductor element and a metal lead frame, 6-bis (trimethoxysilyl) hexane, bis (3-trimethoxysilyl) amine, 1,3,5-tris (trimethoxysilylpropyl) isocyanurate, (aminoethylaminomethyl) phenethyltrimethoxysilane, bis [3 ―
(Trimethoxysilyl) propyl] ethylenediamine,
At least one selected from bis (3-triethoxysilylpropyl) tetrasulfane, a polyethyleneimine-modified silane coupling agent represented by the general formula (1), and a polyether-modified silane coupling agent represented by the general formula (2) Are preferred. The concentration for dilution with an organic solvent is not particularly limited, but is preferably 0.0
The content is 5 to 2% by weight, more preferably 0.1 to 1% by weight. If the content is less than 0.05% by weight, the treatment of the semiconductor element and the lead frame is insufficient, so that the original adhesion and the improvement of the solder resistance cannot be obtained. Although solder resistance is obtained, the processing cost is high, and condensates of the coupling agents adhere to each other after further processing, causing white spots, which is not preferable because electrical reliability is reduced.
【０００９】本発明で用いられる一般式（１）で示され
るシランカップリング剤としては、例えば、下記のもの
が挙げられるが、これらに限定されるものではない。The silane coupling agent represented by the general formula (1) used in the present invention includes, for example, the following, but is not limited thereto.
【化５】 （各構造ともｑは平均値で、いずれも５）Embedded image (In each structure, q is the average value, all of which are 5.)
【００１０】本発明で用いられる一般式（２）で示され
るシランカップリング剤としては、例えば、下記のもの
が挙げられるが、これらに限定されるものではない．Examples of the silane coupling agent represented by the general formula (2) used in the present invention include the following, but are not limited thereto.
【化６】 （各構造ともｍ＋ｑは平均値で５）Embedded image (M + q is 5 on average for each structure)
【００１１】本発明で用いられる沸点１５０℃以下の有
機溶媒は、トルエン、キシレン、メチルイソブチルケト
ン、メタノール、アセトン等が挙げられるが、リードフ
レーム、又は半導体素子とリードフレームに、より密着
性を付与し易い極性溶媒が好ましく、例えばメタノー
ル、アセトン等が挙げられる。有機溶媒の沸点が１５０
℃を越えると、リードフレームに搭載された半導体素子
を封止成形する際の温度では、有機溶媒が十分に揮発せ
ず半導体装置内に残存し、耐半田性を低下したり、予め
有機溶媒を揮発させる温度を１５０℃を越える温度とす
る必要があり半導体素子自体にダメージを与えたり、予
め処理に用いたシランカップリング剤が揮発してしまい
十分な効果が発現できないおそれがあり好ましくない。Examples of the organic solvent having a boiling point of 150 ° C. or lower used in the present invention include toluene, xylene, methyl isobutyl ketone, methanol, and acetone. The organic solvent imparts more adhesiveness to the lead frame or the semiconductor element and the lead frame. A polar solvent which is easy to use is preferable, and examples thereof include methanol and acetone. The boiling point of the organic solvent is 150
If the temperature exceeds ℃, at the temperature at which the semiconductor element mounted on the lead frame is sealed and molded, the organic solvent does not volatilize sufficiently and remains in the semiconductor device, lowering the solder resistance, or causing the organic solvent to be removed in advance. The temperature for volatilization needs to be higher than 150 ° C., which is not preferable because the semiconductor element itself may be damaged, or the silane coupling agent used in advance may volatilize and a sufficient effect may not be exhibited.
【００１２】本発明で用いられるリードフレーム、又は
半導体素子とリードフレームの両方を、予めシランカッ
プリング剤を有機溶媒で希釈した溶液に浸漬したり、ス
プレーをしたりして処理したものは、処理後直ちに成形
しても常温で放置して有機溶媒を揮発させても、加熱し
て有機溶媒を揮発させてから用いてもよいが、極力有機
溶媒を揮発させてから成形することが望ましい。加熱温
度は有機溶媒の沸点を越える温度が望ましいが、好まし
くは室温〜１００℃程度である。In the case where the lead frame used in the present invention or both the semiconductor element and the lead frame are treated by dipping or spraying in a solution obtained by previously diluting a silane coupling agent with an organic solvent, the treated Immediately afterwards, the organic solvent may be volatilized by standing at room temperature to evaporate the organic solvent, or the organic solvent may be heated and then volatilized before use. The heating temperature is desirably a temperature exceeding the boiling point of the organic solvent, but is preferably room temperature to about 100 ° C.
【００１３】本発明で用いられる熱硬化性樹脂組成物と
しては、エポキシ樹脂組成物、不飽和ポリエステル樹脂
組成物、ジアリルフタレート樹脂組成物、ポリブタジエ
ン系液状樹脂組成物、ウレタン系液状樹脂組成物、シリ
コーン系液状樹脂組成物等が挙げられる。本発明でのリ
ードフレームに搭載された半導体素子を熱硬化性樹脂組
成物で封止する方法については、特に限定されるもので
はなく、従来のトランスファー成形、射出成形、キャス
ティング、ポッティング、ディッピングを適用すれば良
い。The thermosetting resin composition used in the present invention includes an epoxy resin composition, an unsaturated polyester resin composition, a diallyl phthalate resin composition, a polybutadiene-based liquid resin composition, a urethane-based liquid resin composition, and a silicone. Liquid resin compositions and the like. The method for sealing a semiconductor element mounted on a lead frame with a thermosetting resin composition according to the present invention is not particularly limited, and conventional transfer molding, injection molding, casting, potting, and dipping are applied. Just do it.
【００１４】以下，本発明を実施例で具体的に説明す
る。 実施例１ γ―（２―アミノエチル）アミノプロピルトリメトキシシラン １重量部 アセトン ９９重量部 を混合した溶液に、１００ピンＴＱＦＰリードフレーム
（４２アロイリードフレームに８．０×８．０ｍｍの抵
抗回路付き半導体素子を搭載し金線ボンディングしたも
の）を浸漬処理し、その後７０℃で、５分間乾燥し下記
の評価用に供した。評価結果を表１に示す。Hereinafter, the present invention will be described specifically with reference to examples. Example 1 A solution obtained by mixing 1 part by weight of γ- (2-aminoethyl) aminopropyltrimethoxysilane with 99 parts by weight of acetone was mixed with a 100-pin TQFP lead frame (a 8.0 × 8.0 mm resistor circuit in a 42 alloy lead frame). The semiconductor device with the attached semiconductor chip and gold wire bonding was immersed, and then dried at 70 ° C. for 5 minutes and used for the following evaluation. Table 1 shows the evaluation results.
【００１５】評価方法 耐半田性：トランスファー成形品は、エポキシ樹脂組成
物を用い前記処理品を金型温度１７５℃、成形圧力７５
ｋｇｆ／ｃｍ2、２分間で成形し（パッケージの厚み
１．４ｍｍ）、１７５℃、８時間で後硬化させた。得ら
れた半導体装置１０個を８５℃、相対湿度８５％の環境
下で７２時間及び１６８時間放置し、その後２４０℃の
半田槽に１０秒間浸漬した。顕微鏡で外部クラックを観
察し、クラック数［（クラック発生パッケージ数）／
（全パッケージ数）×１００］を％で表示した。又チッ
プとエポキシ樹脂組成物の硬化物の界面での剥離面積の
割合を超音波探傷装置を用いて測定し、剥離率［（剥離
面積）／（チップ面積）×１００］として、１０個のパ
ッケージの平均値を求め、％で表示した。射出成形品
は、ジアリルフタレート樹脂組成物を用い前記処理品を
金型温度１６５℃、成形圧力８０ｋｇｆ／ｃｍ2、１分
間で成形したトランスファー成形と同様の１００ピンＴ
ＱＦＰを、１７５℃、４時間で後硬化させた。得られた
半導体装置１０個を前記したエポキシ樹脂組成物を用い
た場合と同様にして評価した。 電気的信頼性：上記と同様にして成形し、後硬化した２
０×１４×２．７ｍｍ厚さの８０ｐＱＦＰ半導体装置１
０個を８５℃、相対湿度６０％にて１０００時間吸湿処
理をして、初期の抵抗値に対して２０％以上増加したも
のを不良と判定し、５個が不良になった時点を時間で示
した。１０００時間まで不良が発生しなかったものは１
０００時間以上と表記した。Evaluation method Solder resistance: The transfer molded product was prepared by using an epoxy resin composition and treating the treated product with a mold temperature of 175 ° C. and a molding pressure of 75.
It was molded in kgf / cm 2 for 2 minutes (package thickness: 1.4 mm) and post-cured at 175 ° C. for 8 hours. The obtained 10 semiconductor devices were left in an environment of 85 ° C. and 85% relative humidity for 72 hours and 168 hours, and then immersed in a 240 ° C. solder bath for 10 seconds. Observe the external cracks with a microscope and check the number of cracks [(number of packages with cracks) /
(The total number of packages) × 100] in%. The ratio of the peeled area at the interface between the chip and the cured product of the epoxy resin composition was measured using an ultrasonic flaw detector, and the peeling rate was determined as [(peeled area) / (chip area) × 100]. Was calculated and expressed in%. The injection-molded article was made of the diallyl phthalate resin composition, and was treated at a mold temperature of 165 ° C. under a molding pressure of 80 kgf / cm 2 for 1 minute.
The QFP was post-cured at 175 ° C. for 4 hours. Ten semiconductor devices obtained were evaluated in the same manner as in the case where the above-mentioned epoxy resin composition was used. Electrical reliability: molded and post-cured as described above 2
80pQFP semiconductor device 1 having a thickness of 0x14x2.7mm
0 pieces were subjected to a moisture absorption treatment at 85 ° C. and a relative humidity of 60% for 1000 hours, and those which increased by 20% or more with respect to the initial resistance value were determined to be defective. Indicated. If no failure occurred up to 1000 hours, 1
000 hours or more.
【００１６】実施例２〜９、比較例１〜５ 表１、表２に示す組み合わせで、実施例１と同様にして
半導体装置を得、実施例１と同様にして評価した。評価
結果を表１、表２に示す。なお、表１、表２中のＴｒは
トランスファー成形、Ｉｎｊは射出成形を表し、封止材
料のＥＭＣはエポキシ樹脂組成物、ＤＡＰはジアリルフ
タレート樹脂組成物を表す。又実施例８、９で用いたシ
ランカップリング剤の構造を下記に示す。Examples 2 to 9 and Comparative Examples 1 to 5 By using the combinations shown in Tables 1 and 2, a semiconductor device was obtained in the same manner as in Example 1, and evaluated in the same manner as in Example 1. The evaluation results are shown in Tables 1 and 2. In Tables 1 and 2, Tr represents transfer molding, Inj represents injection molding, EMC of the sealing material represents an epoxy resin composition, and DAP represents a diallyl phthalate resin composition. The structures of the silane coupling agents used in Examples 8 and 9 are shown below.
【００１７】[0017]
【化７】 （以下、ポリエチレンイミン変性アミノシランという）Embedded image (Hereinafter referred to as polyethyleneimine-modified aminosilane)
【００１８】[0018]
【化８】 （以下、ポリエーテル変性アミノシランという）Embedded image (Hereinafter referred to as polyether-modified aminosilane)
【００１９】[0019]
【表１】 [Table 1]
【００２０】[0020]
【表２】 [Table 2]
【００２１】[0021]
【発明の効果】本発明の半導体装置は、耐半田性及び電
気的信頼性に優れている。The semiconductor device of the present invention has excellent solder resistance and electrical reliability.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） // Ｈ０１Ｌ 23/50 Ｈ０１Ｌ 23/50 Ｅ Ｆターム(参考） 4J038 CA021 DB001 DD181 DG001 DL031 DL051 DL081 DL091 DL121 GA01 GA02 GA07 GA09 GA13 GA15 JC31 JC32 JC34 JC35 JC36 KA03 KA06 NA14 NA17 PA11 PB09 4J040 CA041 EC001 ED111 EF001 EK031 EK051 EK071 EK101 GA01 GA04 GA11 GA14 GA24 GA31 HD30 HD32 HD35 HD36 HD37 KA16 KA23 LA08 LA09 NA20 PA07 4M109 AA01 BA01 FA06 5F061 AA01 BA01 CB12 5F067 AA00 AA04 DA00 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (reference) // H01L 23/50 H01L 23/50 EF term (reference) 4J038 CA021 DB001 DD181 DG001 DL031 DL051 DL081 DL091 DL121 GA01 GA02 GA07 GA09 GA13 GA15 JC31 JC32. 5F067 AA00 AA04 DA00
Claims (1)
を熱硬化性樹脂組成物で封止してなる半導体装置におい
て、予めγ―（２―アミノエチル）アミノプロピルトリ
メトキシシラン、１，６―ビス（トリメトキシシリル）
ヘキサン、ビス（３―トリメトキシシリル）アミン、
１，３，５−トリス（トリメトキシシリルプロピル）イ
ソシアヌレート、（アミノエチルアミノメチル）フェネ
チルトリメトキシシラン、ビス［３―（トリメトキシシ
リル）プロピル］エチレンジアミン、ビス（３―トリエ
トキシシリルプロピル）テトラスルファン、一般式
（１）で示されるポリエチレンイミン変性シランカップ
リング剤、一般式（２）で示されるポリエーテル変性シ
ランカップリング剤から選ばれる一種以上のシランカッ
プリング剤を沸点１５０℃以下の有機溶媒で希釈した溶
液で処理されたリードフレーム、又は半導体素子とリー
ドフレームを用いることを特徴とする半導体装置。 【化１】 （Ｒ1は炭素数１〜１０のアルコキシ基、Ｒ2は炭素数１
〜１０のアルキル基である。ｎは１〜３の整数、Ｒ3は
水素原子、フェニル基、炭素数１〜１０のアルキル基、
又はアミノ基であり、ｍは１〜５の整数。ｑは平均値で
１〜１０の正数） 【化２】 （Ｒ4は炭素数１〜１０のアルコキシ基、Ｒ5は炭素数１
〜１０のアルコキシ基、又はアルキル基。Ｒ6は炭素数
１〜１０のアルキレン基である。Ｒ7はグリシジルエー
テル基、メルカプト基、アミノ基、ビニル基、アクリル
基、又はメタクリル基である。ｎは平均値で１〜３の正
数。ｍ＋ｑは平均値で１〜１０の正数である）In a semiconductor device in which a semiconductor element mounted on a lead frame is sealed with a thermosetting resin composition, γ- (2-aminoethyl) aminopropyltrimethoxysilane, 1,6-bis (Trimethoxysilyl)
Hexane, bis (3-trimethoxysilyl) amine,
1,3,5-tris (trimethoxysilylpropyl) isocyanurate, (aminoethylaminomethyl) phenethyltrimethoxysilane, bis [3- (trimethoxysilyl) propyl] ethylenediamine, bis (3-triethoxysilylpropyl) tetra Sulfane, one or more silane coupling agents selected from polyethyleneimine-modified silane coupling agents represented by the general formula (1) and polyether-modified silane coupling agents represented by the general formula (2) are used. A semiconductor device using a lead frame treated with a solution diluted with an organic solvent, or a semiconductor element and a lead frame. Embedded image (R 1 is an alkoxy group having 1 to 10 carbon atoms, R 2 is an alkoxy group having 1 carbon atom
10 to 10 alkyl groups. n is an integer of 1 to 3, R 3 is a hydrogen atom, a phenyl group, an alkyl group having 1 to 10 carbon atoms,
Or an amino group, and m is an integer of 1 to 5. (q is a positive number of 1 to 10 on average) (R 4 is an alkoxy group having 1 to 10 carbon atoms, and R 5 is an alkoxy group having 1 carbon atom.
10 to 10 alkoxy groups or alkyl groups. R 6 is an alkylene group having 1 to 10 carbon atoms. R 7 is a glycidyl ether group, a mercapto group, an amino group, a vinyl group, an acryl group, or a methacryl group. n is an average value and a positive number of 1 to 3. m + q is a positive number from 1 to 10 on average)
Priority Applications (1)
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|---|---|---|---|
| JP2000052810A JP2001244383A (en) | 2000-02-29 | 2000-02-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000052810A JP2001244383A (en) | 2000-02-29 | 2000-02-29 | Semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2001244383A true JP2001244383A (en) | 2001-09-07 |
Family
ID=18574267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000052810A Pending JP2001244383A (en) | 2000-02-29 | 2000-02-29 | Semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP2001244383A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6716771B2 (en) * | 2002-04-09 | 2004-04-06 | Intel Corporation | Method for post-CMP conversion of a hydrophobic surface of a low-k dielectric layer to a hydrophilic surface |
| EP1411081A1 (en) * | 2002-10-18 | 2004-04-21 | National Starch and Chemical Investment Holding Corporation | Curable compounds containing reactive groups: triazine/isocyanurates, cyanate esters and blocked isocyanates |
| DE10332567A1 (en) * | 2003-07-11 | 2005-02-17 | Infineon Technologies Ag | A compound for forming a layer on a substrate, a method of forming a layer on a substrate, and a semiconductor device |
| US7256496B2 (en) | 2004-06-02 | 2007-08-14 | Casio Computer Co., Ltd. | Semiconductor device having adhesion increasing film to prevent peeling |
| JP2008542495A (en) * | 2005-05-30 | 2008-11-27 | コリア リサーチ インスティチュート オブ ケミカル テクノロジー | Method for surface modification of polyimide film using ethyleneimine coupling agent, method for producing copper foil laminated film using the same, and copper foil laminated film having a two-layer structure produced by the method |
| JP2010016398A (en) * | 2009-09-11 | 2010-01-21 | Casio Comput Co Ltd | Method of manufacturing semiconductor device |
| JP2013008889A (en) * | 2011-06-27 | 2013-01-10 | Bridgestone Corp | Sealing film for solar cell and solar cell using the same |
| WO2023102567A3 (en) * | 2021-12-05 | 2023-10-12 | Debogy Molecular, Inc. | Graftable biocidal linkers and polymers and uses thereof |
-
2000
- 2000-02-29 JP JP2000052810A patent/JP2001244383A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6716771B2 (en) * | 2002-04-09 | 2004-04-06 | Intel Corporation | Method for post-CMP conversion of a hydrophobic surface of a low-k dielectric layer to a hydrophilic surface |
| EP1411081A1 (en) * | 2002-10-18 | 2004-04-21 | National Starch and Chemical Investment Holding Corporation | Curable compounds containing reactive groups: triazine/isocyanurates, cyanate esters and blocked isocyanates |
| US7057264B2 (en) | 2002-10-18 | 2006-06-06 | National Starch And Chemical Investment Holding Corporation | Curable compounds containing reactive groups: triazine/isocyanurates, cyanate esters and blocked isocyanates |
| DE10332567A1 (en) * | 2003-07-11 | 2005-02-17 | Infineon Technologies Ag | A compound for forming a layer on a substrate, a method of forming a layer on a substrate, and a semiconductor device |
| US7256496B2 (en) | 2004-06-02 | 2007-08-14 | Casio Computer Co., Ltd. | Semiconductor device having adhesion increasing film to prevent peeling |
| CN100459125C (en) * | 2004-06-02 | 2009-02-04 | 卡西欧计算机株式会社 | Semiconductor device and method of fabricating the same |
| US7910405B2 (en) | 2004-06-02 | 2011-03-22 | Casio Computer Co., Ltd. | Semiconductor device having adhesion increasing film to prevent peeling |
| JP2008542495A (en) * | 2005-05-30 | 2008-11-27 | コリア リサーチ インスティチュート オブ ケミカル テクノロジー | Method for surface modification of polyimide film using ethyleneimine coupling agent, method for producing copper foil laminated film using the same, and copper foil laminated film having a two-layer structure produced by the method |
| JP2010016398A (en) * | 2009-09-11 | 2010-01-21 | Casio Comput Co Ltd | Method of manufacturing semiconductor device |
| JP2013008889A (en) * | 2011-06-27 | 2013-01-10 | Bridgestone Corp | Sealing film for solar cell and solar cell using the same |
| WO2023102567A3 (en) * | 2021-12-05 | 2023-10-12 | Debogy Molecular, Inc. | Graftable biocidal linkers and polymers and uses thereof |
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