JP2001237376A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a high power efficiency and a low power consumption and can realize a small high frequency power amplifier. SOLUTION: The semiconductor device is composed of a GaAs substrate 1, an active element, i.e., comb-like gate structure field effect transistor 3A formed on the surface of the GaAs substrate 1, and a plurality of serial resonator circuits 7 formed on a multilayer wiring layer on the surface of the GaAs substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency semiconductor device, and more particularly to a semiconductor device suitable for high efficiency.

[0002]

2. Description of the Related Art Conventionally, in order to reduce the power consumption of a high-frequency power amplifier, a series resonance circuit is added to the output side of a power amplification element, and the power is terminated by terminating the second harmonic of the operating frequency with low impedance. Means for improving efficiency are well known. As a conventional example, there is a high-frequency power amplifier shown in FIG. 4, and in FIG.
1 output bonding pad 42 and dielectric chip 44
Are connected by a metal wire 43 to form a series resonance circuit for the second harmonic by the inductance of the metal wire 43 and the capacitance of the capacitor 45, so that the power efficiency is improved. I have.

[0003]

However, in the above-mentioned conventional example, the series resonance circuit for the second harmonic is composed of the capacitor 45 and the metal wire 43 external to the transistor chip 41, Line 43
In this case, the output bonding pad 42 and the capacitor 45 must be arranged at a distance from each other, which increases the power loss and increases the mounting area as an amplifier. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device which has high power efficiency, consumes low power, and can realize a small-sized high-frequency power amplifier.

[0005]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device comprising a semiconductor substrate, an active element formed on a surface of the semiconductor substrate, and a multilayer wiring layer formed on the surface, wherein an inductor and a capacitor are connected in series in the multilayer wiring layer. A series resonance circuit is formed,
The series resonance circuit is installed near an output terminal of the active element, one end of the series resonance circuit is connected to the output terminal, and the other end of the series resonance circuit is connected to a power supply.

Further, in the semiconductor device according to the present invention, the electrode of the capacitor is formed of a wiring metal of a first layer and a wiring metal of a second layer in the multilayer wiring layer.

Further, the semiconductor device of the present invention is characterized in that one of the electrodes is connected to a back electrode of the semiconductor substrate via a via hole provided in the semiconductor substrate.

Further, in the semiconductor device according to the present invention, the inductor is formed of a wiring metal of a third layer in the multilayer wiring layer.

Further, the semiconductor device according to the present invention is characterized in that one end of the inductor is connected to the output terminal.

A semiconductor device according to the present invention is a semiconductor device comprising a semiconductor substrate, an active element formed on a surface of the semiconductor substrate, and a multilayer wiring layer formed on the surface. A series resonance circuit in which an inductor and a capacitor are connected in series is formed in the layer, the series resonance circuit is installed near an output terminal of the active element, one end of the series resonance circuit is connected to the output terminal, The other end of the series resonance circuit is connected to a power supply, and an electrode of the capacitor is formed of a wiring metal of a first layer and a wiring metal of a second layer in the multilayer wiring layer, and one of the electrodes is
The inductor is connected to a back surface electrode of the semiconductor substrate through a via hole provided in the semiconductor substrate,
One end of the inductor is connected to the output terminal, and the inductor, the capacitor, and the via hole are formed on a surface of the semiconductor substrate. It is characterized by being arranged to overlap.

[0011]

Next, the structure of a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a main part of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a structural diagram of a series resonance circuit of the semiconductor device according to the first embodiment of the present invention. , FIG. 2
FIG. 2A is a sectional view taken along line AA ′ of FIG.
FIG. 3B is a top view for explaining the spiral inductor 18 included in the series resonance circuit 7.

As shown in FIGS. 1 and 2A, a semiconductor device according to a first embodiment of the present invention
A comb-type field effect transistor (hereinafter referred to as FET) 3A as an active element formed on the surface of the GaAs substrate 1; a multilayer wiring layer 22 formed on the surface of the GaAs substrate 1; And a plurality of series resonance circuits 7 formed therein.

The comb-type gate structure FET 3A has a plurality of unit cells 3 in which a plurality of FET fingers 2 as the minimum unit active elements are arranged in parallel, and further includes a drain bus 6, a source bus 5, and a gate. A bus 4 is provided.

The FET finger 2 is a MESFET having a drain electrode 2D, a gate electrode 2G, and a source electrode 2S formed on a GaAs substrate 1.

The drain electrodes 2D of all the FET fingers 2 are connected to the drain bus 6, the gate electrodes 2G of all the FET fingers 2 are connected to the gate bus 4, and the source electrodes 2S of all the FET fingers 2 are connected to the source bus 5 It is connected to the.

Each unit cell 3 has a drain bus 6
And a drain bonding pad 6A as a signal output terminal connected to the gate bus 4 and a gate bonding pad 4A as a signal input terminal connected to the gate bus 4.

A series resonance circuit 7 is arranged near the drain bonding pad 6A of each unit cell 3.

One end of a metal wire 10 is bonded to the drain bonding pad 6A by bonding, and
0 is connected to a capacitor 9 having an electrode formed on a dielectric substrate 8 by bonding. The metal wire 10 and the capacitor 9 are output-side matching for extracting signal power from a drain bonding pad 6A which is an output terminal. A circuit is configured to perform impedance matching for the fundamental wave of the operating frequency.

Next, the structure of the series resonance circuit 7 will be described with reference to FIG. As shown in FIG. 2A, the series resonance circuit 7 includes a spiral inductor 18, an MIM capacitor 21, and a via hole 11, and has a GaAs structure.
The lower electrode 13 of the MIM capacitor 21 is formed on the surface of the s-substrate 1 by the first-layer wiring metal, the surface of the lower electrode 13 is covered by the interlayer insulating film 14, and the upper layer of the interlayer insulating film 14 is formed by the second-layer wiring metal. The upper electrode 15 of the MIM capacitor 21 is formed, the surface of the upper electrode 15 is covered with an interlayer insulating film 16, and a third layer wiring metal is formed on the interlayer insulating film 16 by a third-layer wiring metal as shown in FIG. The spiral inductor 18 is formed, the surface of the spiral inductor 18 is covered with an interlayer insulating film 19, and the drain bus 6 is formed on the interlayer insulating film 19 by using a fourth-layer wiring metal.

Further, one end of the spiral inductor 18 is connected to the upper electrode 15 through a through hole 17 provided in the interlayer insulating film 16, and the spiral inductor 18
The other end of through hole 20 provided in interlayer insulating film 19
Is connected to the drain bus 6 via the.

The interlayer insulating films 14, 16, and 19 are formed of a dielectric such as a silicon nitride film and a silicon oxide film.

A via hole 11 is formed from the back surface of the GaAs substrate 1 so that the lower electrode 13 is exposed. A back electrode 12 also serving as a heat sink is formed on the entire back surface of the GaAs substrate 1 including the via hole 11. The electrode 12 is fixed to a metal surface (not shown) and connected to a power supply for supplying a ground potential (not shown).

Further, the GaAs substrate 1 of the series resonance circuit 7
The spiral inductor 18, the MIM capacitor 21, and the via hole 11 are arranged so as to overlap on the surface of the GaAs substrate 1 so that the occupied area on the surface of the GaAs substrate 1 is minimized.

In the semiconductor device of the present embodiment, one end of the series resonance circuit 7 is connected to the drain bus 6, but the connection position is at the drain bonding pad 6A.
As long as it is in the vicinity, any arrangement may be used. For example, the series resonance circuit 7 may be arranged so as to overlap with the drain bonding pad 6A and directly connected to the drain bonding pad 6A.

With the above configuration, one end of the series resonance circuit 7 is connected to the drain bonding pad 6A which is the output terminal of the comb-type gate structure FET 3A via the drain bus 6, and the other end of the series resonance circuit 7 is grounded. A termination operation by series resonance is performed on the second harmonic of the operating frequency.

Here, in the comb-type gate structure FET 3A as a whole, a plurality of series resonance circuits 7 are connected in parallel by the drain bus 6, so that the impedance of the series resonance circuit group including all the series resonance circuits 7 is equal to the first impedance. The inductance of the spiral inductor 18 and the capacitance of the MIM capacitor 21 are set for each series resonance circuit 7 so as to have an optimum value for the second harmonic.

As described above, according to the semiconductor device of the first embodiment of the present invention, the series resonance circuit for the second harmonic of the operating frequency is provided near the drain bonding pad of the comb-gate type FET. As a result, power efficiency can be improved and power consumption can be reduced, and an external series resonance circuit is not required, so that the mounting area of the high-frequency power amplifier can be reduced.

Further, since the series resonant circuit is formed in the multilayer wiring layer on the GaAs substrate in a cascade, the size of the GaAs substrate can be reduced, and the mounting area of the high frequency power amplifier can be further reduced.

Further, by installing a series resonance circuit for each unit cell and dispersing and installing the series resonance circuit as a whole comb gate FET, it is possible to suppress the imbalance in operation between the unit cells. The resonance characteristics such as the resonance bandwidth can be changed by adjusting the constants of the series resonance circuits.

FIG. 3 is a plan view of a main part of a semiconductor device according to a second embodiment of the present invention. In the configuration of the semiconductor device according to the second embodiment of the present invention shown in FIG. 3, the configuration different from that of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1 is that the FET 3A in FIG. Changed to the drain bonding pad 6A of the FET 3A.
Is a part which is changed to a drain bonding pad 36 integrated with a drain bus.

The drain bonding pad 36 has a shape in which the drain bonding pads 6A in FIG. 1 are connected in a line, the series resonance circuit 7 is disposed below the drain bonding pad 36, and one end of the inductor of the series resonance circuit 7 is connected to the drain. It is connected to a bonding pad 36.

In FIG. 3, the same components as those of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

With the above configuration, the metal wire 1 shown in FIG.
It is possible to strike a metal line 37 having the same function as 0 at an arbitrary position on the drain bonding pad 36,
Since the drain bonding pad 36 and the series resonance circuit 7 are always near each other, the degree of freedom in mounting the amplifier can be remarkably improved.

In the semiconductor device according to the embodiment of the present invention, an ME formed on a GaAs substrate is used as an active element.
Although the SFET is taken as an example, the substrate may be changed to a MOSFET or a bipolar transistor.

[0036]

As described above, the first effect of the semiconductor device of the present invention is that the power loss can be reduced, the power efficiency can be improved, and the power consumption can be reduced. The series resonance circuit is unnecessary, and the mounting area of the high frequency power amplifier can be reduced.
The third effect is that the mounting area of the high-frequency power amplifier can be further reduced by forming the series resonance circuit in the multilayer wiring layer in a cascade, and the fourth effect is that the series resonance circuit is provided for each unit cell. With the provision, the imbalance of the operation of each unit cell can be suppressed, and the resonance characteristic, that is, the termination condition can be changed.

[Brief description of the drawings]

FIG. 1 is a main part plan view of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a structural diagram of a series resonance circuit of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a main part plan view of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is an explanatory diagram of a conventional high-frequency power amplifier.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 GaAs substrate 2 FET finger 2D drain electrode 2G gate electrode 2S source electrode 3 unit cell 3A, 3B comb gate FET 4 gate bus 4A gate bonding pad 5 source bus 6 drain bus 6A, 36 drain bonding pad 7 series resonance circuit 8 Dielectric substrate 9 Capacitor 10, 37 Metal wire 11 Via hole 12 Back electrode 13 Lower electrode 14, 16, 19 Interlayer insulating film 15 Upper electrode 17, 20 Through hole 18 Spiral inductor 21 MIM capacitor 22 Multilayer wiring layer 41 Transistor chip 42 Output Bonding pad 43 Metal wire 44 Dielectric chip 45 Capacitor

Claims (6)

[Claims] 1. A semiconductor device comprising: a semiconductor substrate; an active element formed on a surface of the semiconductor substrate; and a multilayer wiring layer formed on the surface, wherein an inductor and a capacitor are provided in the multilayer wiring layer. Are formed in series, a series resonance circuit is provided near the output terminal of the active element, one end of the series resonance circuit is connected to the output terminal, and the other end of the series resonance circuit is A semiconductor device which is connected to a power supply. 2. The semiconductor device according to claim 1, wherein the electrode of the capacitor is formed of a wiring metal of a first layer and a wiring metal of a second layer in the multilayer wiring layer. 3. The semiconductor device according to claim 2, wherein one of said electrodes is connected to a back surface electrode of said semiconductor substrate through a via hole provided in said semiconductor substrate. 4. The semiconductor device according to claim 1, wherein said inductor is formed of a wiring metal of a third layer in said multilayer wiring layer. 5. The semiconductor device according to claim 4, wherein one end of said inductor is connected to said output terminal. 6. A semiconductor device comprising a semiconductor substrate, an active element formed on a surface of the semiconductor substrate, and a multilayer wiring layer formed on the surface, wherein an inductor and a capacitor are provided in the multilayer wiring layer. Are formed in series, a series resonance circuit is provided near the output terminal of the active element, one end of the series resonance circuit is connected to the output terminal, and the other end of the series resonance circuit is The capacitor is connected to a power supply, and the electrode of the capacitor is formed of a wiring metal of a first layer and a wiring metal of a second layer in the multilayer wiring layer, and one of the electrodes is a via provided on the semiconductor substrate. The inductor is connected to a back surface electrode of the semiconductor substrate through a hole, the inductor is formed of a wiring metal of a third layer in the multilayer wiring layer, and one end of the inductor is
A semiconductor device connected to the output terminal, wherein the inductor, the capacitor, and the via hole are arranged so as to overlap on a surface of the semiconductor substrate.