JP2001237266A - Semiconductor chip and its mounting method - Google Patents
Semiconductor chip and its mounting methodInfo
- Publication number
- JP2001237266A JP2001237266A JP2000045689A JP2000045689A JP2001237266A JP 2001237266 A JP2001237266 A JP 2001237266A JP 2000045689 A JP2000045689 A JP 2000045689A JP 2000045689 A JP2000045689 A JP 2000045689A JP 2001237266 A JP2001237266 A JP 2001237266A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- electrode
- ferromagnetic material
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/95053—Bonding environment
- H01L2224/95085—Bonding environment being a liquid, e.g. for fluidic self-assembly
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体チップ及びそ
の実装方法に関する。より詳しくは、基板電極に半導体
チップを接合する半導体チップの実装方法に関するもの
である。The present invention relates to a semiconductor chip and a method for mounting the same. More specifically, the present invention relates to a method for mounting a semiconductor chip for bonding a semiconductor chip to a substrate electrode.
【0002】[0002]
【従来の技術】ディスプレイ用の発光素子等の半導体チ
ップを基板に実装する場合、所定面積の基板面に効率よ
く且つ歩留まりよく実装する必要があり、またコスト面
も考慮する必要がある。また、半導体チップの微小化に
より、実装の際のハンドリングも困難になってきてい
る。そこでこのような点に効果的に対処できる半導体チ
ップ構造やその実装方法が求められている。2. Description of the Related Art When a semiconductor chip such as a light emitting element for a display is mounted on a substrate, it is necessary to mount the semiconductor chip on a substrate having a predetermined area efficiently and with good yield, and it is necessary to consider cost. In addition, due to miniaturization of semiconductor chips, handling during mounting is becoming difficult. Therefore, there is a demand for a semiconductor chip structure and a mounting method thereof that can effectively deal with such points.
【0003】従来の半導体チップ実装方法が、米国特許
第5545291号、同第5824186号、同第59
04545号、特表平9−506742,特開平9−1
20943等に開示されている。これらに記載された実
装方法は、半導体チップにテーパを設けて上下を定め、
基板の窪みに埋め込む方法である。この際、水やアルコ
ールなどの溶液中に半導体チップを混ぜスラリー状にし
て、これを基板上に流している。Conventional semiconductor chip mounting methods are disclosed in US Pat. Nos. 5,545,291, 5,824,186, and 59.
04545, Japanese Translation of PCT International Publication No. 9-506742, and JP-A-9-19-1
20943 and the like. In the mounting methods described in these, the upper and lower sides are determined by providing a taper to the semiconductor chip,
This is a method of embedding in the depression of the substrate. At this time, the semiconductor chip is mixed with a solution such as water or alcohol to form a slurry, and the slurry is flown over the substrate.
【0004】別の従来の半導体チップの実装方法とし
て、静電力により集積回路を基板上に組付ける方法が米
国特許出願第07/902986号に記載されている。
この方法は、静電力により粒子を振動させ、位置エネル
ギーが最小になる状態で半導体チップを配列するもので
ある。As another conventional method for mounting a semiconductor chip, a method of assembling an integrated circuit on a substrate by electrostatic force is described in US Patent Application No. 07/902986.
In this method, particles are vibrated by electrostatic force, and semiconductor chips are arranged in a state where potential energy is minimized.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上記半
導体チップにテーパを設ける方法では、チップ外形が数
百μm程度までの構造では歩留まりは十分大きいが、数
十μmからそれ以下の寸法のものでは歩留まりが低下し
て実用化には問題がある。However, in the above-described method of providing a taper in a semiconductor chip, the yield is sufficiently large for a structure having a chip outer shape of about several hundred μm, but the yield is small for a structure having a size of several tens μm or less. And there is a problem in practical use.
【0006】また、上記従来の静電力を用いる方法で
は、粒子を静電力で振動させるための装置を必要とす
る。また、この方法では、半導体チップを機械的に振動
させるため、半導体チップ同士が衝突して一部が損傷す
るおそれがあり、実用化に適さない。Further, the above-mentioned conventional method using electrostatic force requires a device for vibrating particles with electrostatic force. Further, in this method, since the semiconductor chips are mechanically vibrated, the semiconductor chips may collide with each other and may be partially damaged, which is not suitable for practical use.
【0007】本発明は上記従来技術を考慮したものであ
り、微小な半導体チップを効率よく又歩留まりよく基板
の所望の位置に実装できる半導体チップ及びその実装方
法の提供を目的とする。SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-mentioned prior art, and has as its object to provide a semiconductor chip capable of efficiently mounting a minute semiconductor chip at a desired position on a substrate with good yield and a method of mounting the semiconductor chip.
【0008】[0008]
【課題を解決するための手段】前記目的を達成するた
め、本発明では、基板への接合面を含む一部が強磁性体
またはフェリ磁性体で構成されたことを特徴とする半導
体チップを提供する。According to the present invention, there is provided a semiconductor chip characterized in that a part including a bonding surface to a substrate is made of a ferromagnetic material or a ferrimagnetic material. I do.
【0009】この構成によれば、基板側に設けた磁性体
からなる電極に対し前記強磁性体またはフェリ磁性体が
磁気的に作用して磁気的吸着により半導体チップが基板
上に接合される。According to this structure, the ferromagnetic material or ferrimagnetic material magnetically acts on the electrode made of a magnetic material provided on the substrate side, and the semiconductor chip is joined to the substrate by magnetic attraction.
【0010】好ましい構成例では、前記半導体チップ
は、半導体素子を搭載して基板に接合される支持材を有
し、この支持材の基板への接合面に露出して前記強磁性
体またはフェリ磁性体を設けたことを特徴としている。In a preferred configuration example, the semiconductor chip has a supporting member mounted with a semiconductor element and joined to a substrate, and the ferromagnetic material or the ferrimagnetic material is exposed at a joining surface of the supporting material to the substrate. It is characterized by having a body.
【0011】この構成によれば、半導体素子が支持材上
に搭載され、その支持材の半導体素子搭載面とは反対側
の基板への接合面に露出する強磁性体またはフェリ磁性
体が基板電極との間で磁気的に作用し、支持材が基板に
磁気吸着される。According to this structure, the semiconductor element is mounted on the supporting material, and the ferromagnetic material or the ferrimagnetic material exposed on the bonding surface of the supporting material to the substrate opposite to the semiconductor device mounting surface is formed on the substrate electrode. And the support material is magnetically attracted to the substrate.
【0012】本発明ではさらに、基板の表面に形成され
た電極に半導体チップを接合する半導体チップの実装方
法において、前記半導体チップの所定の一部を強磁性体
またはフェリ磁性体で構成し、この強磁性体またはフェ
リ磁性体と前記基板の電極との間の磁気的吸引力により
前記半導体チップを基板上に吸着して接合することを特
徴とする半導体チップの実装方法を提供する。Further, according to the present invention, in a semiconductor chip mounting method for bonding a semiconductor chip to an electrode formed on a surface of a substrate, a predetermined part of the semiconductor chip is made of a ferromagnetic material or a ferrimagnetic material. A method for mounting a semiconductor chip, wherein the semiconductor chip is attracted to and joined to a substrate by magnetic attraction between a ferromagnetic or ferrimagnetic material and an electrode of the substrate.
【0013】この構成によれば、半導体チップの一部に
設けた強磁性体またはフェリ磁性体の磁気的作用により
半導体チップが基板に吸着されて接合されるため、基板
面に半導体チップを近づけるだけで微小な半導体チップ
を容易に確実に基板上に接合することができる。According to this structure, the semiconductor chip is attracted to and bonded to the substrate by the magnetic action of the ferromagnetic or ferrimagnetic material provided on a part of the semiconductor chip. Thus, a very small semiconductor chip can be easily and reliably bonded onto a substrate.
【0014】好ましい構成例では、複数の前記半導体チ
ップを流体の循環経路中に分散させ、この循環経路中に
前記基板を配置することにより、循環している半導体チ
ップを基板電極に吸着させることを特徴としている。In a preferred configuration example, a plurality of the semiconductor chips are dispersed in a circulation path of a fluid, and the substrate is disposed in the circulation path, so that the circulating semiconductor chips are adsorbed on the substrate electrode. Features.
【0015】この構成によれば、流体循環経路中に基板
を配置するとともにこの流体循環経路中に半導体チップ
を分散させて流すことにより、半導体チップは循環経路
途中の基板に磁気的に吸着されて接合されるため、半導
体チップの保持機構や搬送機構等を用いることなく、半
導体チップを基板に接合することができ接合時の取扱い
性が向上する。According to this configuration, the substrate is arranged in the fluid circulation path and the semiconductor chips are dispersed and flowed in the fluid circulation path, so that the semiconductor chip is magnetically attracted to the substrate in the circulation path. Since the semiconductor chips are joined, the semiconductor chips can be joined to the substrate without using a holding mechanism or a transport mechanism for the semiconductor chips, and the handling at the time of joining is improved.
【0016】[0016]
【発明の実施の形態】以下図面を参照して本発明の実施
の形態について説明する。図1は、本発明の実施の形態
に係る半導体チップの断面図である。半導体チップ1
は、例えばAlGaInPからなるLED素子2と、こ
のLED素子2を上面に搭載する例えばn−GaAsか
らなる支持材3とにより構成される。支持材3の下面側
には保磁力が比較的弱い磁気的ソフト材からなる強磁性
体4の層を介してソフト材に比べ保磁力が強い磁気的ハ
ード材からなる強磁性体5が埋設される。支持材3の下
面全体にわたってハード材強磁性体5およびその周囲の
ソフト材強磁性体4が露出してこの支持材3の下面を覆
う。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor chip according to an embodiment of the present invention. Semiconductor chip 1
Is composed of an LED element 2 made of, for example, AlGaInP and a support member 3 made of, for example, n-GaAs, on which the LED element 2 is mounted. A ferromagnetic material 5 made of a magnetic hard material having a stronger coercive force than the soft material is embedded on the lower surface side of the support member 3 via a layer of a ferromagnetic material 4 made of a magnetic soft material having a relatively weak coercive force. You. The hard ferromagnetic material 5 and the surrounding soft ferromagnetic material 4 are exposed over the entire lower surface of the support member 3 to cover the lower surface of the support member 3.
【0017】ソフト材強磁性体4は、鉄(Fe)または
パーマロイその他の強磁性体あるいはフェリ磁性体で構
成され、支持材(n−GaAs)3との界面にはオーミ
ックコンタクトと密着性向上のため、GaAs側から、
Pd層10nm、AuGe合金層150nm、Ti層5
0nmが順番に成膜され、さらに、Fe層が1μm、酸
化防止膜が100nm成膜される。The soft ferromagnetic material 4 is made of a ferromagnetic material such as iron (Fe) or permalloy or a ferrimagnetic material, and has an ohmic contact at the interface with the support material (n-GaAs) 3 to improve adhesion. Therefore, from the GaAs side,
Pd layer 10 nm, AuGe alloy layer 150 nm, Ti layer 5
0 nm is formed in order, and further, an Fe layer is formed in a thickness of 1 μm and an antioxidant film is formed in a thickness of 100 nm.
【0018】ハード材強時磁性体5は、図2に示すよう
に、表面酸化処理が施された長軸300nm、短軸10
0nmの楕円形状の鉄(Fe)粒子6が光硬化樹脂7中
に分散された構造である。この鉄粒子6は、単磁区構造
をとり、長軸方向に磁化している。鉄粒子6の長軸は支
持材3の表面に垂直に配向しているため、ハード材強磁
性体5全体としては、支持材表面に垂直方向(上下方
向)が磁化容易軸となる。鉄以外でも他の強磁性体又は
フェリ磁性体で構成してもよい。As shown in FIG. 2, the hard magnetic material 5 has a long axis 300 nm and a short axis 10
It has a structure in which iron (Fe) particles 6 having an elliptical shape of 0 nm are dispersed in a photocurable resin 7. The iron particles 6 have a single magnetic domain structure and are magnetized in the long axis direction. Since the major axis of the iron particles 6 is oriented perpendicular to the surface of the support 3, the direction (vertical direction) perpendicular to the surface of the support is the easy axis of magnetization of the hard ferromagnetic material 5 as a whole. It may be made of other ferromagnetic material or ferrimagnetic material other than iron.
【0019】半導体チップ1の大きさは、例えば支持材
3が20μm×20μm×10μmであり、磁性体4,
5部分の寸法は、14μm×14μm×7μmである。The size of the semiconductor chip 1 is, for example, that the support material 3 is 20 μm × 20 μm × 10 μm,
The dimensions of the five parts are 14 μm × 14 μm × 7 μm.
【0020】図3は、上記半導体チップの磁束分布を示
す。磁束は、ソフト材強磁性体4によってチップ上面側
と側面側が閉じ、下面側のみが開いているため、上面お
よび側面方向には他の磁性体とは相互作用を及ぼさな
い。一方、チップ下面側では磁束が開いているため、こ
の下面側でのみ他の磁性体と静磁的相互作用を及ぼす。FIG. 3 shows the magnetic flux distribution of the semiconductor chip. The magnetic flux does not interact with the other magnetic material in the direction of the upper surface and the side surface because the upper surface and the side surface of the chip are closed by the soft ferromagnetic material 4 and only the lower surface is open. On the other hand, since the magnetic flux is open on the lower surface side of the chip, magnetostatic interaction with other magnetic materials is exerted only on the lower surface side.
【0021】図4は、上記半導体チップが実装される基
板の平面図である。例えばガラスからなる基板8上に、
TiとFeから構成されるストライプ状電極9が、幅1
00μm、周期1nmでパターニングされて形成され
る。FIG. 4 is a plan view of a substrate on which the semiconductor chip is mounted. For example, on a substrate 8 made of glass,
The stripe electrode 9 composed of Ti and Fe has a width of 1
It is formed by patterning with a pattern of 00 μm and a cycle of 1 nm.
【0022】図5は、上記半導体チップの製造プロセス
を示す説明図である。まず、(A)に示すように、n型
GaAsの支持材3の表面に、複数のLED素子2が分
離して形成され、表面に透明電極が形成された状態で、
ポジ型フォトレジスト10を両面に塗布する。裏面側の
フォトレジスト10は、磁性体埋設用の溝を形成するた
めにフォトマスクを用いて露光、現像してパターニング
される。次に、硫酸、過酸化水素、水の混合溶液中で湿
式エッチングを行い、(B)に示すように、溝11を形
成する。FIG. 5 is an explanatory view showing a manufacturing process of the semiconductor chip. First, as shown in (A), a plurality of LED elements 2 are separately formed on the surface of an n-type GaAs support member 3 and a transparent electrode is formed on the surface.
A positive photoresist 10 is applied to both sides. The photoresist 10 on the back side is exposed and developed using a photomask to form a groove for embedding a magnetic material, and is patterned. Next, wet etching is performed in a mixed solution of sulfuric acid, hydrogen peroxide, and water to form a groove 11 as shown in FIG.
【0023】次に、この支持材3の裏面に、Pdを10
nm、AuGe合金を150nm、Tiを50nm、、
Feを1000nmの厚さに蒸着して、(C)に示すよ
うに、ソフト材強磁性体4を成膜する。この際、蒸着し
ながら支持材3を自公転させることにより、溝11内の
側面にもこれらの金属を成膜する。次に、還元ガス雰囲
気で、180℃で5分の熱処理を行い合金化する。Next, on the back surface of the support member 3, 10
nm, AuGe alloy 150 nm, Ti 50 nm,
Fe is deposited to a thickness of 1000 nm to form a soft ferromagnetic material 4 as shown in FIG. At this time, these metals are also formed on the side surfaces in the grooves 11 by revolving the support member 3 while rotating. Next, heat treatment is performed at 180 ° C. for 5 minutes in a reducing gas atmosphere to form an alloy.
【0024】続いて、光硬化樹脂中に前述の鉄粉を分散
して、n−hexaneで適度な粘度に調整し、支持材
裏面の溝11内に塗布した後、10kOeの磁場中で光
硬化させて、(D)に示すように、ハード材強磁性体5
を形成する。その後、壁開により各LED素子間を分割
する。Subsequently, the above-mentioned iron powder is dispersed in a photo-curing resin, adjusted to an appropriate viscosity by n-hexane, applied to the groove 11 on the back surface of the support material, and then photo-cured in a magnetic field of 10 kOe. Then, as shown in FIG.
To form Thereafter, each LED element is divided by opening the wall.
【0025】次に上記半導体チップの実装方法について
説明する。まず、複数の上記半導体チップを水などの極
性溶媒に分散させ、これをポンプなどで循環させる。こ
の循環経路中に基板を配置する。この場合、半導体チッ
プの親水性や疎水性を考慮して極性溶媒や極性のない溶
媒を適宜選定する。本実施形態の支持材を構成するGa
Asは親水性が大きいため、極性溶媒である水を用いて
チップ同士の凝集を防ぎ分散性をよくしている。Next, a method for mounting the semiconductor chip will be described. First, a plurality of the semiconductor chips are dispersed in a polar solvent such as water and circulated by a pump or the like. The substrate is placed in this circulation path. In this case, a polar solvent or a non-polar solvent is appropriately selected in consideration of the hydrophilicity and hydrophobicity of the semiconductor chip. Ga constituting the support of the present embodiment
Since As has high hydrophilicity, water is used as a polar solvent to prevent aggregation of chips and improve dispersibility.
【0026】この循環経路中に分散している半導体チッ
プの一部がある確率で必ずこの循環経路内に配置された
基板上のFe等の強磁性体からなる電極9(図4参照)
に接近して流れる。このように基板の磁性体電極に近づ
き裏面がこの基板電極の方向に向いた半導体チップは、
その支持材の裏面に埋設された強磁性体4,5による静
磁的相互作用により、チップの裏面が基板電極に磁気的
に吸着されて半導体チップが基板上に接合される。An electrode 9 made of a ferromagnetic material such as Fe on a substrate arranged in the circulation path with a certain probability of a part of the semiconductor chips dispersed in the circulation path (see FIG. 4).
Flows close to As described above, the semiconductor chip approaching the magnetic electrode of the substrate and having the back surface facing the direction of the substrate electrode,
By the magnetostatic interaction of the ferromagnetic materials 4 and 5 embedded on the back surface of the support member, the back surface of the chip is magnetically attracted to the substrate electrode, and the semiconductor chip is joined to the substrate.
【0027】図6は基板上に磁気的に接合された半導体
チップの磁束分布状態を示す。図示したように、電極9
は、ガラス基板8上に形成されたTi層9aとAu電極
層9bとFe電極層9cとにより構成されている。この
接合状態では、半導体チップ1に形成されたハード材強
磁性体5による磁束は、その周囲のソフト材強磁性体4
と実装基板8の鉄電極9cの中に囲まれて閉じられ外に
は漏出しない。FIG. 6 shows a magnetic flux distribution state of a semiconductor chip magnetically bonded on a substrate. As shown, the electrode 9
Is composed of a Ti layer 9a, an Au electrode layer 9b, and an Fe electrode layer 9c formed on a glass substrate 8. In this joined state, the magnetic flux generated by the hard ferromagnetic material 5 formed on the semiconductor chip 1 is reduced by the soft ferromagnetic material 4 surrounding the hard ferromagnetic material 4.
And is enclosed by the iron electrode 9c of the mounting substrate 8 and is closed and does not leak outside.
【0028】また、既に1つの半導体チップ1が接合し
た基板8の電極上に、図7に示すようにさらに重なるよ
うに他の半導体チップ1’が接近した場合には、後から
接近した半導体チップ1’には弱い磁気的な相互作用は
存在するが、この磁気的相互作用は、既に基板電極と直
接接合している半導体チップ1と基板電極間の相互作用
に比べ磁性体同士の距離が離れているため、非常に弱
い。このため、後から接近した半導体チップ1’は、流
体によって押し流され1つの電極上に複数の半導体チッ
プが重なることはない。When another semiconductor chip 1 'approaches the electrode of the substrate 8 to which one semiconductor chip 1 has already been joined so as to further overlap as shown in FIG. 1 'has a weak magnetic interaction, but the magnetic interaction is farther apart than the interaction between the semiconductor chip 1 and the substrate electrode already joined directly to the substrate electrode. Because it is very weak. For this reason, the semiconductor chip 1 'approached later is not washed away by the fluid and a plurality of semiconductor chips do not overlap on one electrode.
【0029】図8は、本発明の別の実施の形態を示す。
この実施形態は、前述の半導体チップと基板電極間の磁
気的作用に加えて、基板8に局所的に外部磁場を付加し
て接合すべき位置に向かう磁束の空間分布を形成したも
のである。このように外部磁場を付加することにより、
半導体チップ1を要求された位置の電極に対し確実に接
合することができる。なお、この場合、半導体チップ1
のソフト材強磁性体4までが着磁されるため、外部に幾
分磁束が漏れて電極周辺に半導体チップが重なり合って
結合するが、接合後に、付加した磁場を解除することに
より、前述の図6に示した磁束分布となって、電極と直
接接合している半導体チップのみが電極上に残る。FIG. 8 shows another embodiment of the present invention.
In this embodiment, in addition to the above-described magnetic action between the semiconductor chip and the substrate electrode, a spatial distribution of magnetic flux toward a position to be joined is formed by locally applying an external magnetic field to the substrate 8. By adding an external magnetic field in this way,
The semiconductor chip 1 can be securely joined to the electrode at the required position. In this case, the semiconductor chip 1
Since the soft material ferromagnetic material 4 is magnetized, some magnetic flux leaks to the outside, and the semiconductor chip overlaps and couples around the electrode. With the magnetic flux distribution shown in FIG. 6, only the semiconductor chip directly connected to the electrode remains on the electrode.
【0030】以上のような磁気的な方法で半導体チップ
を基板上に実装した場合、半導体チップのソフト材強磁
性体と実装基板の磁性体電極とが直接接触するので、こ
れらを電極として利用することができる。When the semiconductor chip is mounted on the substrate by the magnetic method as described above, the soft ferromagnetic material of the semiconductor chip and the magnetic electrode of the mounting substrate are in direct contact, and these are used as electrodes. be able to.
【0031】[0031]
【発明の効果】以上説明したように、本発明では、半導
体チップの一部に設けた強磁性体またはフェリ磁性体の
磁気的作用により半導体チップが基板の磁性体電極に吸
着されて接合されるため、基板面に半導体チップを近づ
けるだけで微小な半導体チップを容易に確実に基板上に
接合することができ、同時に多数の半導体チップを所望
の位置に歩留まりよく効率的に実装することができる。As described above, according to the present invention, the semiconductor chip is attracted to and joined to the magnetic electrodes of the substrate by the magnetic action of the ferromagnetic or ferrimagnetic material provided on a part of the semiconductor chip. Therefore, a minute semiconductor chip can be easily and reliably joined to the substrate simply by bringing the semiconductor chip close to the substrate surface, and a large number of semiconductor chips can be efficiently mounted at desired positions with high yield.
【0032】この場合、半導体チップの一定位置に磁性
体を露出させて設けておくことにより、基板上での半導
体チップの位置とともにその方位や姿勢を制御すること
ができる。また、実装する個所に同時に複数の半導体チ
ップが重なって接合されることはなく、接合の信頼性が
高い。また、接合のために用いた半導体チップの磁性体
をそのまま電極として利用することができる。In this case, by providing the magnetic material at a predetermined position on the semiconductor chip so as to be exposed, it is possible to control the position and orientation of the semiconductor chip on the substrate as well as the direction and orientation thereof. In addition, a plurality of semiconductor chips are not overlapped and joined at the same time at the mounting location, and the joining reliability is high. Further, the magnetic material of the semiconductor chip used for bonding can be used as an electrode as it is.
【図1】 本発明に係る半導体チップの断面図。FIG. 1 is a cross-sectional view of a semiconductor chip according to the present invention.
【図2】 図1の半導体チップのハード材強磁性体の構
成説明図。FIG. 2 is a configuration explanatory view of a hard material ferromagnetic material of the semiconductor chip of FIG. 1;
【図3】 図1の半導体チップ周辺の磁束分布の説明
図。FIG. 3 is an explanatory diagram of a magnetic flux distribution around the semiconductor chip of FIG. 1;
【図4】 本発明の半導体チップが実装される基板の平
面図。FIG. 4 is a plan view of a substrate on which the semiconductor chip of the present invention is mounted.
【図5】 本発明の半導体チップの製造プロセスの説明
図。FIG. 5 is an explanatory diagram of a semiconductor chip manufacturing process of the present invention.
【図6】 本発明の半導体チップの実装状態の磁束分布
説明図。FIG. 6 is an explanatory view of a magnetic flux distribution in a mounted state of the semiconductor chip of the present invention.
【図7】 本発明の半導体チップの接合作用の説明図。FIG. 7 is an explanatory diagram of a bonding operation of the semiconductor chip of the present invention.
【図8】 本発明の別の実施形態による磁束分布説明
図。FIG. 8 is an explanatory diagram of a magnetic flux distribution according to another embodiment of the present invention.
1,1’:半導体チップ、2:LED素子、3:支持
材、4:ソフト材強磁性体、5:ハード材強磁性体、
6:鉄粒子、7:光硬化樹脂、8:基板、9:電極、1
0:フォトレジスト、11:溝。1, 1 ': semiconductor chip, 2: LED element, 3: support material, 4: soft material ferromagnetic material, 5: hard material ferromagnetic material,
6: iron particles, 7: photocurable resin, 8: substrate, 9: electrode, 1
0: photoresist, 11: groove.
Claims (4)
フェリ磁性体で構成されたことを特徴とする半導体チッ
プ。1. A semiconductor chip wherein a part including a bonding surface to a substrate is made of a ferromagnetic material or a ferrimagnetic material.
て基板に接合される支持材を有し、この支持材の基板へ
の接合面に露出して前記強磁性体またはフェリ磁性体を
設けたことを特徴とする請求項1に記載の半導体チッ
プ。2. The semiconductor chip according to claim 1, further comprising: a support member mounted with a semiconductor element and bonded to a substrate, and provided with said ferromagnetic material or ferrimagnetic material exposed at a bonding surface of said support material to said substrate. The semiconductor chip according to claim 1, wherein:
プを接合する半導体チップの実装方法において、 前記半導体チップの所定の一部を強磁性体またはフェリ
磁性体で構成し、この強磁性体またはフェリ磁性体と前
記基板の電極との間の磁気的吸引力により前記半導体チ
ップを基板上に吸着して接合することを特徴とする半導
体チップの実装方法。3. A method of mounting a semiconductor chip in which a semiconductor chip is joined to an electrode formed on a surface of a substrate, wherein a predetermined part of the semiconductor chip is made of a ferromagnetic material or a ferrimagnetic material. Alternatively, a method of mounting a semiconductor chip, wherein the semiconductor chip is attracted to and bonded to a substrate by magnetic attraction between a ferrimagnetic material and an electrode of the substrate.
中に分散させ、この循環経路中に前記基板を配置するこ
とにより、循環している半導体チップを基板電極に吸着
させることを特徴とする請求項3に記載の半導体チップ
の実装方法。4. A circulating semiconductor chip is adsorbed on a substrate electrode by dispersing a plurality of semiconductor chips in a circulation path of a fluid and disposing the substrate in the circulation path. A method for mounting the semiconductor chip according to claim 3.
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JP2000045689A JP2001237266A (en) | 2000-02-23 | 2000-02-23 | Semiconductor chip and its mounting method |
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