JP2001230363A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a contact property between a connecting terminal of a member for supporting a semiconductor device and a lead of the semiconductor device. SOLUTION: There are provided a tab 1e for supporting a semiconductor chip 2 having a semiconductor integrated circuit formed on its main surface, a plurality of leads 1a that are disposed in the periphery of the tab 1e and provided with a terminal connecting surface 1b exposed in the outer periphery of the rear surface 3a of a sealed portion 3, the sealed portion formed by sealing the semiconductor chip and bonding wires for connecting pads of the semiconductor chip 2 and leads 1a corresponding to them. Since the plurality of leads 1a disposed in the outer periphery of the rear surface 3a of the sealed portion 3 are provided while inclined in a direction perpendicular to their array direction, a CSP 7 can be reliably brought into contact with a mount board or a connecting terminal of a socket when the CSP 7 is mounted on the mount board or the socket. As a result, the contact property of the CSP 7 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor device, and more particularly to a technology which is effective when applied to the improvement of contact between leads and connection terminals when a small semiconductor device is mounted on a mounting board or a socket. .

[0002]

2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

[0003] As a miniaturized semiconductor device, CSP is used.
A small package called a (Chip Scale Package or Chip Size Package) having a size slightly larger than a chip size or a semiconductor chip has been developed.

In the CSP, various structures have been devised. As a structure in which external terminals are provided on the back surface (the surface on the semiconductor device mounting side) of a sealing portion formed by sealing, It is mainly classified into an area array type in which external terminals such as solder balls are arranged in a grid pattern, and a peripheral type in which external terminals such as leads are arranged on the outer periphery of the back surface.

[0005] The peripheral CSP is a QFN.
(Quad Flat Non-leaded Package) or the like. When inspecting the electrical characteristics of the QFN, the QFN is fitted to a socket (semiconductor device supporting member) and inspected.

[0006] The structures of various CSPs and their mounting techniques are described in, for example, Nikkan Kogyo Shimbun, September 1, 1999, “Electronic Technology 1999 / September / Vol.
1, No. 10, forefront of CSP / flip chip mounting technology ", pp. 1-13.

[0007]

However, the QFN of the above-mentioned technique has a very small standoff (a distance between a connection terminal on the mounting substrate side in surface mounting and a sealing portion of the semiconductor device) of about 10 μm. Because it is a package, Q
If the burrs are formed at the edges of the connection terminals such as the contact pins of the socket when the FN is set in the socket, even if there is only a slight misalignment in the QFN, the contact pins of the socket and the leads of the QFN do not come into contact. In this case, the burrs of the contact pins come into contact with the back surface of the QFN sealing portion.

As a result, there is a problem that the contact pin and the lead of the QFN do not come into contact with each other and cause a contact failure.

It is an object of the present invention to provide a method of manufacturing a semiconductor device for improving the contact between a connection terminal of a semiconductor device support member and a lead.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the method of manufacturing a semiconductor device according to the present invention, a step of preparing a lead frame having a chip supporting portion capable of supporting a semiconductor chip and a plurality of leads arranged around the chip supporting portion is provided. Bonding the chip support portion and the semiconductor chip, connecting the surface electrode of the semiconductor chip and the corresponding lead, and sealing the semiconductor chip to form a terminal connection surface of the lead. Forming a sealing portion by exposing the semiconductor device on the semiconductor device mounting side surface, separating a plurality of leads from a frame portion of the lead frame, and forming a plurality of semiconductor device supporting members capable of supporting the semiconductor device. One of the connection terminal and the plurality of leads of the semiconductor device is disposed so as to be inclined with respect to a direction perpendicular to the arrangement direction. And a step of mounting the semiconductor device on the semiconductor device supporting member in contact with said lead.

According to the present invention, the connection terminals of the semiconductor device supporting member and the leads of the semiconductor device can be reliably brought into contact with each other when the semiconductor device is mounted, so that the contact properties of the semiconductor device can be improved. .

As a result, it is possible to reduce incidental work such as re-inspection due to contact failure.

Further, since re-inspection can be reduced, an inspection tester can be effectively used, and as a result, inspection throughput can be improved.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIGS. 1A and 1B show an example of a structure of a semiconductor device assembled by a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view, FIG.
FIG. 2C is a bottom view, FIG. 2 is a cross-sectional view showing the structure of the semiconductor device shown in FIG. 1, FIG. 3 is a manufacturing process flow chart showing an example of an embodiment of a method of manufacturing the semiconductor device shown in FIG. FIG. 5 is a partial plan view showing an example of the structure of a lead frame used in the method of manufacturing the semiconductor device shown in FIG. 1, and FIG. 5 is a partial plan view showing an example of a mounting state of the semiconductor device shown in FIG. 6 is a partial cross-sectional view showing an example of a mounting state of the semiconductor device shown in FIG. 1 to the socket, and FIG. 7 is a diagram showing the connection between the package-side lead and the board-side connection terminal when mounting the semiconductor device shown in FIG. It is a diagram showing an example of a contact state,
(A) is a plan view, (b) is a partial sectional view.

The semiconductor device shown in FIG. 1 assembled by the method of manufacturing a semiconductor device according to the present embodiment is a CSP 7 (also referred to as QFN) having a small chip size or a size slightly larger than the semiconductor chip 2 and a surface mount type. The semiconductor package has a relatively small number of pins and is incorporated in, for example, a portable electronic device or a small electronic device.

A peripheral type (QFN) in which a plurality of leads 1a as external terminals are arranged side by side on an outer peripheral portion of a semiconductor device mounting side surface (hereinafter referred to as a back surface 3a) of a sealing portion 3 formed by molding. (Also referred to as bottom lead type).

The configuration of the CSP 7 will be described with reference to FIGS. 1 and 2. A tab 1e (chip supporting portion) for supporting a semiconductor chip 2 having a semiconductor integrated circuit formed on a main surface 2b, and a tub 1e surrounding the tab 1e. A plurality of leads 1a which are arranged and are also external terminals having a terminal connection surface 1b exposed at an outer peripheral portion of a back surface 3a of the sealing portion 3, and a sealing portion 3 formed by resin sealing the semiconductor chip 2. And a plurality of leads 1a arranged on the outer peripheral portion of the back surface 3a of the sealing portion 3 as shown in FIG. 1 (c). The bonding wires 4 connect the pads 2a of the semiconductor chip 2 and the corresponding leads 1a. As shown in FIG. 2), they are provided to be inclined with respect to the direction perpendicular to the arrangement direction.

That is, in the CSP 7 of this embodiment,
A plurality of leads 1a provided on the back surface 3a of the sealing portion 3 are slightly inclined in the same direction on each side with respect to a direction perpendicular to the arrangement direction. The CSP 7 is mounted on the mounting substrate 8 (semiconductor device supporting member) shown in FIG.
Is mounted, the leads 1a of the CSP 7 and their connection terminals 8a, 9h (see FIG. 7) on the substrate side can be reliably contacted.

The inclination angle of each of the leads 1a with respect to the direction perpendicular to the arrangement direction is very small.

Each lead 1a in the CSP 7 is:
1 has both functions of an inner lead and an outer lead, and a margin for cutting when separated from the frame 1f of the lead frame 1 shown in FIG. As shown in (a) and (c), the outer end of each lead 1a projects from the sealing portion 3 by about several tens to several hundreds of micrometers.

Further, in the CSP 7 of the present embodiment, FIG.
As shown in (1), the semiconductor chip 2 is fixed to the tab 1e by a die bond material 5 (for example, a paste material such as a resin).

Further, in the CSP 7 of the present embodiment, a solder plating layer 6 is formed on the terminal connection surface 1b of each lead 1a.

This solder plating layer 6 is used to increase the solder connection strength when the CSP 7 is solder-mounted on the mounting board 8 shown in FIG. 5 and the like. Is subjected to a solder plating process to form a solder plating layer 6.

The thickness of the solder plating layer 6 is, for example,
About 10 μm, and the thickness of the solder plating layer 6 is
This is a standoff in the CSP 7 (an interval between the connection terminal 8a of the mounting board 8 and the sealing portion 3 of the CSP 7 in surface mounting).

The bonding wire 4 for electrically connecting the pad 2a, which is the surface electrode of the semiconductor chip 2, to the bonding surface 1c of the corresponding lead 1a is
For example, a gold wire or an aluminum wire is used.

Further, the sealing portion 3 is formed by resin sealing by a molding method, and a sealing resin used at this time is, for example, a thermosetting epoxy resin.

The leads 1a and tabs 1e are, for example,
It is formed of Cu, Fe, Fe-Ni, or the like, and has a thickness of, for example, about 0.1 to 0.2 mm.

Next, the configuration of the lead frame 1 shown in FIG. 4 used for manufacturing the CSP 7 will be described. The lead frame 1 has a tab 1e capable of supporting the semiconductor chip 2.
(Chip supporting portion) and a terminal connection surface 1 disposed around the tab 1 e and exposed on the back surface 3 a of the sealing portion 3 of the CSP 7.
b, a plurality of leads 1a provided inclining in the same direction on each side with respect to a direction perpendicular to the arrangement direction, and a tab suspension lead 1d for supporting a tab 1e; It is a thin metal plate composed of a lead 1a and a frame portion 1f supporting the tab suspension lead 1d, and is a strip-shaped multiple unit capable of manufacturing a plurality of CSPs 7 from one lead frame 1. is there.

That is, one lead frame 1 has 1
A plurality of package regions corresponding to the CSPs 7 are formed, and a plurality of guide slots 1g and positioning holes for transporting the lead frame 1 at the time of die bonding or wire bonding are formed in the frame portion 1f. 1h
Are formed.

The material of the lead frame 1 is, for example, copper (Cu), iron (Fe), or an alloy of iron and nickel (Fe-Ni). The thickness is about 1 to 0.2 mm, but the material and the thickness are not limited to these.

Next, the semiconductor device of this embodiment (CSP
The manufacturing method 7) will be described with reference to the manufacturing process flow chart shown in FIG.

The method of manufacturing the CSP 7 is performed using the lead frame 1 shown in FIG.

First, in step S1, a tab 1e capable of supporting the semiconductor chip 2 and a plurality of tabs disposed around the tab 1e and provided in the same direction with respect to a direction perpendicular to the arrangement direction are provided. The lead frame 1 shown in FIG.

Note that the lead frame 1 is a strip-shaped multiple unit capable of manufacturing a plurality of CSPs 7 from one lead frame 1.
, A plurality of package regions corresponding to one CSP 7 are formed.

Subsequently, in step S2, the semiconductor chip 2 is supplied, and then, in step S3, the tab 1e of the lead frame 1 and the back surface 2c of the semiconductor chip 2 are joined.

That is, as shown in FIG. 2, a chip mount (die bonding or die bonding) for fixing the semiconductor chip 2 to the tab 1e of the lead frame 1 (see FIG. 4) with the main surface 2b facing upward via the die bonding material 5. Pellet bonding).

Thereafter, the pads 2a (surface electrodes) of the semiconductor chip 2 and the corresponding bonding surfaces 1c of the leads 1a are connected by wire bonding (step S4).

Further, as shown in step S5, resin sealing of the semiconductor chip 2 by molding is performed.

Here, the semiconductor chip 2 is sealed with a resin by molding, and at this time, each terminal connection surface 1b of each lead 1a is substantially the same as the back surface 3a of the sealing portion 3 (the surface on the semiconductor device mounting side). The sealing portion 3 is formed by resin sealing so as to be exposed as a surface.

Thus, as shown in FIG. 1 (c), each lead 1a is disposed on the back surface 3a of the sealing portion 3 so as to be substantially flush with the back surface 3a, and at the outer periphery of the back surface 3a. Each side is slightly inclined in the same direction with respect to a direction perpendicular to the arrangement direction.

After resin sealing, a solder plating layer 6 as shown in FIG. 2 is formed on the terminal connection surface 1b of each lead 1a exposed on the back surface 3a of the sealing portion 3 (step S6).

For the solder plating on each lead 1a, for example, a surface treatment for enabling connection to an external device (for example, a measuring instrument or the like) on the surface of the lead frame 1 at the stage of the lead frame 1 is performed in advance. For example, when a surface treatment such as Pd or Pd-Au is performed, the formation of the solder plating layer 6 after resin sealing, that is, the solder plating process is not required.

Thereafter, lead cutting (step S7) is performed in which the plurality of leads 1a and tab suspension leads 1d are cut off from the frame 1f of the lead frame 1 by cutting, thereby including the sealing portion 3 from the frame 1f of the lead frame 1. Each lead 1a is separated into a shape shown in FIGS. 1 (a), 1 (b) and 1 (c).

Thus, the CSP 7 shown in FIG. 1 is completed (step S8).

After that, the CSP 7 is mounted on the semiconductor device supporting member.

In this embodiment, the semiconductor device supporting member is the mounting substrate 8 shown in FIG. 5, and the CSP 7 is mounted on the mounting substrate 8, and the semiconductor device supporting member is the socket 9 shown in FIG. , And the case where the CSP 7 is mounted on the socket 9 will be described.

First, as shown in FIG. 5, when mounting the CSP 7 on the mounting board 8, the CSP 7 is mounted on the mounting board 8 by, for example, solder reflow.

At this time, the CSP 7 is configured such that each lead 1a is slightly inclined in the same direction on each side with respect to a direction perpendicular to the arrangement direction on the outer peripheral portion of the back surface 3a of the sealing portion 3. CSP 7 and mounting board 8
Even if there is some displacement between them, as shown in FIG. 5, each lead 1a and the connection terminal 8a of the mounting board 8 arranged substantially parallel to the direction perpendicular to the arrangement direction. Can be surely brought into contact.

On the other hand, the case where the CSP 7 is mounted on the socket 9 is shown in FIGS.

Here, the socket 9 is of a clamshell type used for inspecting the CSP 7 or the like by a sheet contact method in, for example, an electrical characteristic inspection of a semiconductor device.

Therefore, the socket 9 is provided with pin members 9f corresponding to the number of external terminals of the CSP 7, and the pin members 9f are attached to the test board 10 to electrically connect the socket 9 to the test board 10. Is performed.

The socket 9 includes a socket body 9a on which the CSP 7 is disposed and a lid member 9b for applying a load to the CSP 7. The lid member 9b has a lid member 9b when the lid member 9b is closed. Hook member 9e for locking the CSP 7 to the socket body 9a and a spring member 9 for applying a load to the CSP 7
c and a pressing element 9d are provided.

The socket body 9a is provided with a tape-shaped circuit board 9g for making a sheet contact with the CSP 7 at the time of inspection, and a base member 9i for supporting the circuit board 9g.

Further, as shown in FIG. 7A, the surface of the circuit board 9g (the surface on the side supporting the CSP 7) is CS
A connection terminal 9h, which is a plurality of contact pins arranged corresponding to each lead 1a of P7, is provided.

When the CSP 7 is set in the socket 9, the leads 1a of the CSP 7 are slightly inclined in the same direction with respect to the direction perpendicular to the arrangement direction. Even if there is a slight misalignment with the circuit board 9g of FIG.
As shown in (a) and (b), each lead 1a is securely brought into contact with the connection terminal 9h of the circuit board 9g of the socket 9 arranged substantially parallel to the direction perpendicular to the arrangement direction. be able to.

According to the method of manufacturing the semiconductor device (CSP 7) of the present embodiment, the following operational effects can be obtained.

That is, the plurality of leads 1a of the CSP 7 are arranged on the back surface 3a of the sealing portion 3 so as to be inclined with respect to the direction perpendicular to the arrangement direction, and the CSP 7 is mounted on the mounting substrate 8
When the semiconductor device is mounted on a semiconductor device supporting member such as the socket 9 or the like, the leads 1a of the CSP 7 and the connection terminals 8a of the mounting board 8 or the connection terminals 9h of the socket 9 are not parallel but obliquely contact with each other. , 9
The contact margin between h and the lead 1a can be increased.

Thus, the connection terminal 8a of the mounting board 8 or the connection terminal 9h of the socket 9 and the lead 1 of the CSP 7
a can be reliably brought into contact with each other. Therefore, even when burrs are formed at the edge of the connection terminal 9h such as a contact pin, the contact pin and the CS are not connected.
The lead 1a of P7 can be reliably contacted.

As a result, the contact property of the lead 1a in the CSP 7 can be improved.

In particular, it is possible to improve the contact property of the lead 1a with respect to the CSP 7 having a small standoff.

As a result, re-inspection due to contact failure (re-inspection of CSP 7 determined to be defective in the first inspection)
And other incidental operations can be reduced.

Furthermore, since re-inspection can be reduced, an inspection tester can be effectively used, and as a result, the CSP7
Inspection throughput can be improved.

Further, since the contact property of the CSP 7 can be improved, the yield of the CSP 7 can be improved.

Further, since the contact property of the CSP 7 can be improved, the CSP 7 when mounting the CSP 7 on a semiconductor device supporting member such as the socket 9 or the mounting substrate 8 and the connection terminals 8a and 9h of the semiconductor device supporting member are mounted. In the positioning with the CSP7, rough positioning that does not require high-precision positioning can be performed.
Slight misalignment can be absorbed,
The mountability of the CSP 7 can be improved.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the embodiments of the present invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

For example, in the above-described embodiment, the case where the tab 1e is not exposed on the back surface 3a of the sealing portion 3 in the CSP 7 has been described, but the CSP 7 may have a tab exposed structure.

In the above embodiment, the case where the socket 9 is of the clamshell type has been described, but the socket 9 may be of the open top type.

In the above-described embodiment, the case where the leads 1a of the semiconductor device (CSP 7) are arranged so as to be inclined in the same direction for each side with respect to a direction perpendicular to the arrangement direction has been described. As in the other embodiment shown in FIG. 9, the leads 1a of the semiconductor device (CSP7) may not be inclined but the connection terminals 8a of the mounting board 8 or the connection terminals 9h of the socket 9 may be inclined.

Therefore, in another embodiment shown in FIG. 8, the connection terminals 8a of the mounting board 8 are arranged so as to be inclined in the same direction for each side with respect to a direction perpendicular to the arrangement direction. As a result, the contact relationship between the connection terminal 8a and the lead 1a can be made oblique, as in the case where the lead 1a of the CSP 7 of the embodiment is inclined. As a result, the same effect as in the embodiment described above can be obtained. The operation and effect can be obtained.

Further, in another embodiment shown in FIG. 9, the connection terminals 9h of the socket 9 are arranged so as to be inclined in the same direction for each side with respect to a direction perpendicular to the arrangement direction. Thus, as in the other embodiment shown in FIG. 8, the contact relationship between the connection terminal 9h and the lead 1a can be made oblique, and as a result, the same operation and effect as those of the above embodiment can be obtained. Obtainable.

In the above-described embodiment and the other embodiments, the case where the semiconductor device is a small CSP 7 has been described. However, in the semiconductor device, a plurality of leads 1 a are provided on the back surface 3 a of the sealing portion 3. If it is placed,
It may be other than CSP7 (QFN).

[0075]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). At least one of the plurality of connection terminals of the semiconductor device support member and the plurality of leads of the semiconductor device is arranged to be inclined with respect to a direction perpendicular to the arrangement direction, and the semiconductor device is mounted on the semiconductor device support member. Thereby, the connection terminal of the semiconductor device support member and the lead of the semiconductor device can be reliably brought into contact, and as a result,
The contact property of the semiconductor device can be improved.

(2). According to the above (1), it is possible to reduce incidental work such as re-inspection due to contact failure. further,
Since re-inspection can be reduced, an inspection tester can be effectively used, and as a result, inspection throughput can be improved.

(3). Since the contact property of the semiconductor device can be improved, the yield of the semiconductor device can be improved.

(4). Since the contact property of the semiconductor device can be improved, when the semiconductor device is mounted on a semiconductor device support member such as a socket or a mounting board, the alignment between the semiconductor device and the connection terminal of the semiconductor device support member is roughened. And a slight displacement of the semiconductor device can be absorbed. As a result, the mountability of the semiconductor device can be improved.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are diagrams showing an example of a structure of a semiconductor device assembled by a method of manufacturing a semiconductor device according to an embodiment of the present invention; FIG. (B)
Is a side view, and (c) is a bottom view.

FIG. 2 is a cross-sectional view showing a structure of the semiconductor device shown in FIG.

FIG. 3 is a manufacturing process flow chart showing one example of an embodiment of a method of manufacturing the semiconductor device shown in FIG. 1;

FIG. 4 is a partial plan view showing an example of the structure of a lead frame used in the method of manufacturing the semiconductor device shown in FIG.

FIG. 5 is a partial plan view showing an example of a mounting state of the semiconductor device shown in FIG. 1 on a mounting board.

6 is a partial cross-sectional view showing an example of a state in which the semiconductor device shown in FIG. 1 is mounted on a socket.

FIGS. 7A and 7B are diagrams showing an example of a contact state between a package-side lead and a board-side connection terminal when the semiconductor device shown in FIG. 1 is mounted on a socket; Is a plan view, and (b) is a partial sectional view.

FIG. 8 is a partial plan view showing a state of being mounted on a mounting board by a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 9 is a plan view showing a state of being mounted on a socket by a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lead frame 1a Lead 1b Terminal connection surface 1c Bonding surface 1d Tab suspension lead 1e Tab (chip support part) 1f Frame part 1g Guide long hole 1h Positioning hole 2 Semiconductor chip 2a Pad (surface electrode) 2b Main surface 2c Back surface 3 Sealing Stop portion 3a Back surface (surface on the semiconductor device mounting side) 4 Bonding wire 5 Die bond material 6 Solder plating layer 7 CSP (semiconductor device) 8 Mounting substrate (semiconductor device support member) 8a Connection terminal 9 Socket (semiconductor device support member) 9a socket Main body 9b Lid member 9c Spring member 9d Presser 9e Hook member 9f Pin member 9g Circuit board 9h Connection terminal 9i Base member 10 Test board

Claims (1)

[Claims] 1. A method for manufacturing a surface-mounted semiconductor device, comprising: preparing a lead frame having a chip support portion capable of supporting a semiconductor chip and a plurality of leads arranged around the chip support portion; Joining the chip support portion of the lead frame and the semiconductor chip; connecting a surface electrode of the semiconductor chip and the corresponding lead; sealing the semiconductor chip and providing the lead Forming a sealing portion by exposing a terminal connection surface of the semiconductor device to the surface on the semiconductor device mounting side; separating a plurality of leads from a frame portion of the lead frame; and a semiconductor capable of supporting the semiconductor device. Any one of the plurality of connection terminals of the device support member and the plurality of leads of the semiconductor device is disposed so as to be inclined with respect to a direction perpendicular to the arrangement direction. Mounting the semiconductor device on the semiconductor device supporting member by bringing a connection terminal into contact with the lead.