JP2001230055A - Abnormality detection device for heater drive - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect steadily and promptly the abnormality related to heater drive by a combination of logic of heater drive signal and conduction detection signal. SOLUTION: A heater drive circuit b1 is connected with an alternating current power source AC and drives a heater b3 in compliance with a heater trigger signal s1 which instructs the conduction of the heater b3. An abnormality decision circuit b2, which is composed of a logic circuit, detects a combination of abnormal state or changes of the heater trigger signal s1 and the conduction detection signal s4, based on the conduction detection signal s4 showing the conduction state of the heater obtained from heater drive circuit b1 and the heater trigger signal, and outputs it as a decision signal s5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to driving of a load such as a fixing heater driven by an AC power supply, and more particularly to a device for detecting an abnormality thereof.

[0002]

2. Description of the Related Art Conventionally, there has been an image forming apparatus such as a copying machine, a printer, a facsimile, etc., which uses a heater driven by an AC power supply for fixing a toner image.

In a heater driving circuit for driving such a fixing heater, a heater conduction detection signal is smoothed by a capacitor, and the smoothed output is output to a CPU I / O via a comparator.
A method of detecting an abnormality of a triac or a heater by connecting to an O or the like is generally used. The advantage of this method is that the abnormality detecting means can be easily constituted by an analog circuit.

[0004]

However, the above conventional method has the following disadvantages. (1) Since the abnormality detection means is configured by an analog circuit, the threshold value of the abnormality determination comparator and the conduction detection signal (analog value) itself vary due to variations in the characteristics of the components used. (2) The output signal may be fixed to a high or low level due to an abnormality in the comparator output itself, so that a target abnormality may not be detected. (3) When the conduction detection signal line falls to a low level immediately after the power is turned off, the charge of the control power supply remains without being completely discharged until a time after this, and as a result, it is recognized as abnormal and error processing and storage are performed. There is a risk of going. In order to prevent this, it is necessary to provide a special process such that the main power supply is recognized by software and error processing is not performed for the time. In addition, this configuration involves software, which is not preferable as a safety system. (4) It is possible to cope to some extent when the heater is full-wave on or completely off, but it may not be able to cope with abnormality monitoring during phase control depending on its on / off (ON / OFF) duty. There was an uncertain point in terms of.

The present invention has been made in view of such a conventional background, and an object of the present invention is to compare a heater drive signal and a conduction detection signal without using a conventional comparator to compare an analog signal with a threshold level. An object of the present invention is to provide a heater drive abnormality detection device that can reliably and quickly detect an abnormality related to heater drive by combining logics, that is, by forming a digital circuit.

[0006]

A heater driving abnormality detecting device according to the present invention comprises a heater driven by an AC power supply;
Switching means for controlling conduction to the heater in response to a heater trigger signal for instructing conduction of the heater; a conduction detection circuit for detecting a conduction state of the heater and generating a conduction detection signal; An abnormality determination logic circuit for detecting a combination of a state and a change of the detection signal that cannot be in a normal state.

[0007] By using the digital signal and the hardware logic circuit as described above, it is possible to reliably and quickly detect an abnormality related to the heater drive, and to improve the reliability of the apparatus.

In the first embodiment, the abnormality determination logic circuit detects a case where the conduction detection signal has already indicated a conduction state when the heater trigger signal indicates conduction of the heater, and responds accordingly. A signal indicating the occurrence of an abnormal state is output.

In the second embodiment, the abnormality determination logic circuit detects a case where the conduction detection signal changes from a non-conduction state to a conduction state when the heater trigger signal does not indicate conduction of the heater, In response, a signal indicating the occurrence of an abnormal state is output.

In the third embodiment, the abnormality determination logic circuit detects a case where the conduction detection signal does not indicate the conduction state of the heater despite the heater trigger signal indicating the conduction of the heater. In response, a signal indicating the occurrence of an abnormal state is output.

More specifically, the first, second, and third embodiments have a first configuration in which one of the heater trigger signal and the conduction detection signal is received at a signal input terminal and is received.
, A second flip-flop which receives an output of the first flip-flop at an input terminal and takes in the same, and outputs a non-inverted output of one of the first and second flip-flops and an inverted output of the other. First and second
And an AND gate that receives the other of the heater trigger signal and the conduction detection signal at a third input terminal.

[0012] Preferably, when the signal indicating the occurrence of the abnormal state is generated plural times continuously within a predetermined time, it is determined that the signal is abnormal, and the signal is continuously generated plural times within the predetermined time. If it does not occur, it is determined not to be judged as abnormal. Thus, it is possible to prevent a case in which an abnormal state is temporarily returned to a normal state immediately after an abnormal state, such as a momentary interruption of the power supply voltage, from being determined as an abnormal state.

More specifically, the timer is activated by a signal indicating the occurrence of the abnormal state, and generates a time signal having a time width corresponding to the predetermined time. A counter that counts the number of occurrences of the signal indicating the occurrence of the abnormal state, and a comparator that outputs a final signal indicating the occurrence of the abnormal state when the count value of the counter reaches a predetermined value. By returning to the non-generating state of the timed signal, the counter can be reset even before the count value reaches a predetermined value.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a schematic configuration of the entire heater drive abnormality detecting device according to the present invention. This device includes a heater drive circuit b1 and a heater drive abnormality determination circuit (abnormality determination logic circuit) b2. The heater drive circuit b1 is connected to an AC power supply AC and drives the heater b3 according to a heater trigger signal s1 and a relay drive signal s2 from outside. The heater trigger signal s1 is a pulse signal generated according to the detected temperature of the heater b3 and instructing conduction of the heater b3. The relay drive signal s2 is a signal for instructing to shut off the power supply voltage of the heater b3 when an abnormality occurs, as described later. The heater drive abnormality determination circuit b2 receives the conduction detection signal s4 from the heater drive circuit b1, performs an abnormality determination based on an external heater trigger signal s1, and outputs an abnormality determination signal s5 according to the determination result. If the abnormality determination signal s5 indicates an abnormality, the control circuit (not shown) stops the subsequent generation of the heater trigger s1 and turns off the relay drive signal s2 to turn off the heater b3.
Power supply to the power supply is cut off.

FIG. 2 is a circuit diagram showing a specific circuit configuration inside the heater drive circuit b1 of FIG. 1 together with the heater b3.

The capacitor C1 connected to the AC power supply AC
01 are connected to the relay RL101 and the thyristor CR
It is connected to the heater b3 via 101 (switching means). The diode D101 connected in parallel with the relay RL101 is an element for improving the response speed of the relay RL101. In addition, a series connection SQ10 of a resistor and a capacitor connected in parallel to the thyristor CR101.
1 is a protection element of the thyristor CR101. Relay RL101 is normally turned on by a relay drive signal s2 via a drive circuit (transistor Q102 and resistor), and is turned off when an abnormality occurs. On the other hand, thyristor CR1
01 is conductively controlled by a heater trigger signal s1 via a drive circuit (such as the photocoupler PC101). Specifically, the relay turns on when the relay drive signal s2 is on and when the heater trigger signal s1 turns on, and turns off when the AC power supply voltage (the voltage across the capacitor C101) drops to around 0V. Therefore, the amount of power supplied to the heater b3 changes according to the phase of the ON timing of the heater trigger signal s1, and as a result, the heater b3
Is controlled. Note that the capacitor C102 connected in parallel with the resistor R101 is an element provided for removing noise of a trigger signal of the thyristor CR101.

The photocoupler PC102 (constituting a conduction detecting circuit) connected to both ends of the heater b3 via the resistor R104 turns on its output phototransistor when the potential difference between both ends of the heater b3 is equal to or larger than a predetermined value. Then, the conduction detection signal s4, which is an output signal, is set to a low level. During a period in which the potential difference between both ends of the heater b3 does not reach the predetermined value, the conduction detection signal s4 is at a high level. This conduction detection signal s4
Based on the heater trigger signal s1 and an abnormality determination circuit b2, which will be described in detail below, logically determines abnormality.

FIG. 3 shows an example of a circuit for making such a determination as a first abnormality determination circuit 30. The abnormality determination circuit 30 checks the conduction detection signal s4 when the heater trigger signal s1 rises (that is, when a heater conduction instruction is given), and indicates that the conduction detection signal s4 is already in a conduction state (that is, low). When the level is L), a high level (H) indicating "abnormal" is output to the determination signal s5. This is because the heater trigger signal s1 can only rise when the heater is in the non-conductive state. Therefore, when the heater trigger signal s1 rises while the heater is in the conductive state, this is detected as the first abnormal state. It is to judge.

In FIG. 3, D flip-flops (F
F) 32 fetches the heater trigger signal s1 in synchronization with the clock signal CLK and outputs it to its Q output terminal. It is assumed that the frequency of the clock signal CLK is higher than changes in other signals s1, s4, and the like. The D flip-flop 33 at the subsequent stage of the flip-flop 32 outputs the same clock signal CL.
The Q output of the flip-flop 32 is taken in synchronization with K. That is, the flip-flop 33 captures the state of the heater trigger signal s1 one clock before the flip-flop 32. The flip-flop 33 outputs an inverted signal of the fetched signal to the / Q output terminal ("/" represents an inverted bar here). Flip-flop 33
/ Q output is high level (this indicates that the heater trigger signal s1 taken into the flip-flop 32 one clock before was low level), and at the same time, the Q output of the flip-flop 32 is high level. There is (this indicates that the heater trigger signal s1 taken into the flip-flop 32 at the time of the current clock is at a high level)
At this time, this means that the heater trigger signal s1 has changed (rising) from a low level to a high level. To detect this state, the Q output of the flip-flop 32 and the / Q output of the flip-flop 33 are input to two input terminals of a three-input AND (logical product) gate 34.
Further, the continuity detection signal s4 is transmitted to A through the inverter 31.
The remaining one input terminal of the ND gate 34 is input. The input terminal goes to a high level when the conduction detection signal s4 is at a low level. Accordingly, the AND gate 34 generates a high-level output signal when the heater trigger signal s1 changes from a low level to a high level (rises) when the conduction detection signal s4 is at a low level. this is,
The above conditions are met.

The high-level output of the AND gate 34 is input to an enable (EN) input terminal of a subsequent D flip-flop 35. The D input terminal of the flip-flop 35 is fixed at a high level. Therefore, the Q output of the flip-flop 35 changes from the initial low level to the high level at the timing when the clock signal rises when the high level is input from the flip-flop 34 to the enable input terminal (EN) of the flip-flop 35. Change to level. Thus, the high-level determination signal s5 indicating the occurrence of the abnormal state is output to the Q output terminal of the flip-flop 35.
Is generated. The state where the flip-flop 35 detects the abnormal state is determined by a low-level reset signal (/ R
ESET) is held.

FIG. 4 shows a signal waveform (timing diagram) of a main part of the abnormality determination circuit 30 of FIG. However, the waveform of “zero cross” at the top of FIG. 4 is illustrated to show a position near zero of the AC power supply voltage (low-level portion of the waveform). When necessary, the heater trigger signal s1 is turned on somewhere in the middle of the adjacent zero-cross position (instructed phase angle position). In response to the rise of the heater trigger signal s1, the triac (CR101 in FIG. 1) starts conducting, and the conduction detection signal s4 becomes low. When the power supply voltage drops to near zero (that is, at the zero-cross position), the triac is turned off and the conduction detection signal s
4 returns to high level. Each of the time points t41 and t42 in FIG. 4 indicates a rising time point of the heater trigger signal s1. At time t41, the conduction detection signal s4 is at a high level (ie, non-conduction state), so this state is considered normal. On the other hand, at time t42, the conduction detection signal s4
Is already at a low level (ie, conducting state). As described above, such a state cannot occur in a normal state, and the output of the AND gate 34 in FIG. 3 is changed to a high level. As a result, the determination signal s5 from the flip-flop 35 is changed to a high level. (Abnormal).

There are other combinations of signal states and changes that cannot occur in a normal state in the heater drive circuit (b1 in FIG. 1). The second combination is a case where the heater is turned on even though the heater trigger signal s1 does not indicate that the heater is turned on (the conduction detection signal s4 has changed from a high level to a low level, that is, has fallen).

FIG. 5 shows a specific circuit configuration of the second abnormality judging circuit 50 for detecting the second abnormal state. The flip-flops 52 and 53 connected in series perform the same operation as the flip-flops 32 and 33 in FIG.
However, the input signal is not the heater trigger signal s1 but the conduction detection signal s4. The / Q output from the preceding flip-flop 52 in FIG. 5 is input to the AND gate 54, and the Q output from the subsequent flip-flop 53 is output.
The output is input to the AND gate 54. Therefore, when the Q output of flip-flop 53 is at a high level (ie, conduction detection signal s4 was at a high level one clock before), the / Q output of flip-flop 52 is at a high level (ie, conduction detection signal s4). When s4 goes low in the current clock), this means that the conduction detection signal s4 has changed (falled) from high to low. On the other hand, the inverter 31 of FIG.
Is provided with an inverter 51. However, the input to the inverter 51 is not the conduction detection signal s4 but the heater trigger signal s1. Therefore, the AND gate 54 generates a high-level output signal when the conduction detection signal s4 changes from a high level to a low level (falls) when the heater trigger signal s1 is at a low level. This is the flip-flop 3 in FIG.
5, the flip-flop 55 is enabled,
The Q output (judgment signal s5) is changed to a high level.

FIG. 6 shows a main signal waveform of the second abnormality judging circuit 50 shown in FIG. At time t61 when the conduction detection signal s4 falls, the heater trigger signal s1 is at a high level (that is, non-conduction state), so this state is considered normal. On the other hand, at time t62 when the conduction detection signal s4 falls, the heater trigger signal s1 is already at the low level (that is, the conduction state). As described above, such a state cannot occur in a normal state, and the output of the AND gate 54 in FIG. 5 is changed to a high level. As a result, the determination signal s5 from the flip-flop 55 is changed to a high level. (Abnormal).

In the third combination of signal states and changes that cannot occur in a normal state in the heater drive circuit (b1 in FIG. 1), the triac is not conductive (ie, conductive) despite the rise of the heater trigger signal s1. This is the case where the detection signal s4 remains unchanged at the high level.

FIG. 7 shows a third abnormality determination circuit 70 for detecting the third combination. The combination of the flip-flops 71 and 72 is the same as the flip-flops 52 and 53 of the second abnormality determination circuit 50 in FIG. However, it differs from the case of FIG. 5 in that the input signal is not the conduction detection signal s4 but the heater trigger signal s1. Therefore, flip-flops 71 and 72 and AND gate 73
Is a configuration for detecting the falling point of the heater trigger signal s1. The reason for detecting the falling point of the heater trigger signal s1 is that it is considered that the heater trigger signal s1 has risen a predetermined time before that.
Therefore, the falling point of the heater trigger signal s1 corresponds to the point in time when the conduction detection signal s4 should be at a low level indicating the conduction state, if it is normal. At this point, the fact that the conduction detection signal s4 remains at a high level means that some abnormality has occurred. Therefore, the conduction detection signal s4
Is input to the other input terminal of the AND gate 73 as it is. Thus, when the conduction detection signal s4 is at a high level at the time when the heater trigger signal s1 falls (that is, when the heater does not conduct even though the heater trigger signal s1 indicates that the heater is conducting), the AND gate 73 operates as follows.
Generates a high-level signal, which is
The determination signal s5, which is the Q output of No. 4, is changed to a high level.

FIG. 8 shows a signal waveform of a main part of the third abnormality judging circuit 70 of FIG. At time t81 when the heater trigger signal s1 falls, the conduction detection signal s4 is already at a low level (that is, non-conduction state), so this state is considered normal. On the other hand, at time t82 when the heater trigger signal s1 falls, the conduction detection signal s4 remains at a high level (that is, non-conduction state). As described above, such a state cannot occur in a normal state, and the AND gate 73 shown in FIG.
Is changed to a high level, and as a result, the determination signal s5 from the flip-flop 74 becomes a high level (abnormal).

In the first to third abnormality determination circuits described above, if the combination of the signal state and the change as described above occurs even once, it is determined that the state is abnormal. However, even if a state that is determined to be abnormal momentarily due to a cause such as a momentary interruption of the power supply voltage appears, the state may be restored to the normal state immediately thereafter. In such a case, it is not necessary to determine that there is an abnormality and stop driving the heater.

Then, by adding a circuit element to the above-mentioned abnormality determination circuit, the determination signal s5 is set to a high level after confirming that the above-mentioned abnormality determination state has occurred several times in succession. I do.

FIG. 9 shows a circuit configuration of a fourth abnormality judging circuit 90 using the first abnormality judging circuit 30 shown in FIG. 3 and adding an additional circuit portion 99 for temporal judgment. . However, in FIG. 3, the AND gate 3 of the abnormality determination circuit 30
Although the output of the flip-flop 35 is used as the enable input of the flip-flop 35, the output of the AND gate 34 is used as the D input of the flip-flop 35 in the abnormality determination circuit 90 of FIG. This is 1 in the abnormality determination circuit 30 of FIG.
This is because the abnormality determination circuit 90 shown in FIG. 9 does not determine that the abnormality is abnormal only by one abnormality determination result, while the determination signal s5 is fixed at a high level in the results of the abnormality determinations.
As a result, when the abnormal state continues for a certain period of time, not instantaneously, the output signal s6 of the flip-flop 35 repeats on / off as shown in FIG.
Since the circuit on the left half of FIG. 9 is not exactly the same as the abnormality determination circuit 30, it is indicated by reference numeral 30 '.

An additional circuit portion 99 for the abnormality determination circuit 30 'includes a timer 91, a counter 92, a comparator 93,
A D flip-flop 94 and an AND gate 95. The timer 91 has an abnormality determination circuit 3 at its TRG input terminal.
Triggered by the rise of the output signal s6 of 0 ', a pulse having a predetermined relatively long time width (for example, about 2 or 3 seconds) is generated as the timed signal s7. During this time, changes in the output signal s6 input to the TRG input terminal are ignored. While the time signal s7 was at the low level, the counter 92 was maintained in the reset state via the AND gate 95. However, when the time signal s7 became the high level (when the other input of the AND gate 95 Since a certain reset signal / RESET is normally at a high level), the reset state of the counter 92 is released.

The output signal s6 of the abnormality determination circuit 30 'is input to the enable terminal EN of the counter 92, and the clock signal (CLK) is input to the clock input terminal of the counter 92. As can be seen from FIG. 10, the counter 92 counts the clock each time the output signal s6 becomes high for one clock period while the timed signal s7 of the timer 91 is high. The count value s8 is compared with a predetermined count value (for example, an integer value n larger than 1) in the comparator 93 (FIG. 9). When the count value s8 reaches the predetermined value n, the comparison output s9 of the comparator 93 goes high, and in response, the D flip-flop 94 outputs a high-level determination signal s5 indicating the occurrence of an abnormality. However, in the case of an instantaneous interruption or the like, before the count value s8 reaches the predetermined value n, the state may return to the normal state and the output signal s6 may remain unchanged at a low level. In such a case, while the time signal s7 of the timer 91 is maintained at a high level, the counter 92
Of the timed signal s8 without reaching the predetermined value n
7 returns to low level. As a result, the counter 92 is reset via the AND gate 95. Therefore, the output of the comparator 93 does not go high, and the determination signal s5 from the last-stage flip-flop 94 does not go high. In this way, abnormalities in a very short time, such as instantaneous interruption, can be ignored.

FIG. 11 is a circuit diagram of FIG. 9 using an abnormality determination circuit 50 'obtained by slightly modifying the second abnormality determination circuit 50 shown in FIG.
15 shows a configuration example of a fifth abnormality determination circuit 110 to which a circuit element for temporal determination similar to the above is added. Additional circuit part 99
Are the same as those shown in FIG.
The operation of the abnormality determination circuit 50 'is based on the abnormality determination circuit 50 shown in FIG. 5, and the output of the abnormality determination circuit 50' is not fixed by a single occurrence of an abnormality, as can be easily inferred from the case of the abnormality determination circuit 30 '. It was made. Therefore, FIG.
The signal waveform of the abnormality determination circuit 110 is not particularly shown.

FIG. 12 is a circuit diagram of FIG. 9 using an abnormality determination circuit 70 'obtained by slightly modifying the third abnormality determination circuit 70 shown in FIG.
13 shows a configuration example of a sixth abnormality determination circuit 120 to which a circuit element for temporal determination similar to the above is added. Additional circuit part 99
Are the same as those shown in FIG.
Also, the operation of the abnormality determination circuit 70 'is based on the abnormality determination circuit 70 of FIG. 7, and its output is not fixed by one abnormality occurrence as easily analogized from the case of the abnormality determination circuit 30'. It was made. Therefore, FIG.
The signal waveform of the abnormality determination circuit 120 of No. 2 is not particularly shown.

Finally, the fourth, fifth, and sixth abnormality determination circuits 90, 110, and 120 in FIGS. 9, 11, and 12, respectively.
FIG. 13 shows a circuit configuration example of the abnormality determination circuit 130 in which all the functions described above are combined. In this abnormality determination circuit 130,
Only one common additional circuit portion 99 is prepared, and the three output signals of the preceding abnormality determination circuits 30 ′, 50 ′, and 70 ′ are ORed by an OR (logical OR) gate 131.
The operation result signal s10 is used instead of the output signal s6 for the additional circuit section 99. With this circuit configuration, it is possible to cope with all the abnormal combinations of the first, second, and third signal states and changes described above, and to cope with a temporary abnormal state such as an instantaneous interruption. Become.

Although the preferred embodiment of the present invention has been described above, various modifications and changes are possible. For example,
The elements used as circuit elements and their specific combinations are not limited to those described above, and a substantially equivalent circuit configuration is sufficient. Further, the meaning of the high level and the low level of the signal (whether positive logic or negative logic) or the like may be reversed from the above description.

[0038]

According to the present invention, the conventional abnormality determination circuit is replaced with a digital logic circuit, and the heater and the switching element are used not only during the phase control of the heater, but also in the half-wave control and when the heater is turned off. It is possible to reliably detect a heater drive-related abnormality up to the (triac) abnormality or the disconnection of the detection line. Further, in the embodiment in which the time factor is taken into consideration, a malfunction due to noise can be reliably prevented, and an instantaneous interruption of the AC power supply can be dealt with without generating error processing due to false detection. Further, since no software intervention is required, the reliability of abnormality determination is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an entire heater drive abnormality detection device according to the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration inside a heater drive circuit b1 of FIG. 1 together with a heater b3.

FIG. 3 is a circuit diagram of a first abnormality determination circuit 30 which is a first configuration example of the abnormality determination circuit b2 of FIG. 1;

FIG. 4 is a timing chart showing signal waveforms of main parts of the abnormality determination circuit 30 of FIG.

FIG. 5 is a circuit diagram of a second abnormality determination circuit 50 which is a second configuration example of the abnormality determination circuit b2 of FIG.

FIG. 6 is a timing chart showing signal waveforms of main parts of the abnormality determination circuit 50 of FIG.

FIG. 7 is a circuit diagram of a third abnormality determination circuit 70 which is a third configuration example of the abnormality determination circuit b2 of FIG.

8 is a timing chart showing signal waveforms of main parts of the abnormality determination circuit 70 of FIG.

9 is a circuit diagram showing a circuit configuration of a fourth abnormality determination circuit 90 which is a fourth configuration example of the abnormality determination circuit b2 of FIG.

FIG. 10 is a timing chart showing signal waveforms of main parts of the abnormality determination circuit 90 of FIG. 9;

11 is a circuit diagram illustrating a circuit configuration of a fifth abnormality determination circuit 110 which is a fifth configuration example of the abnormality determination circuit b2 of FIG.

12 is a circuit diagram showing a circuit configuration of a sixth abnormality determination circuit 120 which is a sixth configuration example of the abnormality determination circuit b2 of FIG.

FIG. 13 is a circuit diagram showing a circuit configuration of a seventh abnormality determination circuit 130 which is a seventh configuration example of the abnormality determination circuit b2 of FIG.

[Explanation of symbols]

 b1 heater drive circuit b2 heater drive abnormality determination circuit b3 heater s1 heater trigger signal s2 relay drive signal s4 conduction detection signal s5 abnormality determination signal s6 output signal s7 timed signal s9 comparison output 32, 33, 35, 55, 74 D flip-flop 34, 54, 73, 95 AND gate 91 Timer 92 Counter 93 Comparator 131 OR gate

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H027 DA38 DA48 DA50 ED25 EK00 2H033 AA35 CA01 CA34 3K058 AA11 BA18 CB02 CD01 5H323 AA36 BB17 CA08 CB02 DA01 DB04 DB06 JJ03 KK05 LL13 MM02 MM12 NN02 Q01 NN06 NN06 SS08 SS10 TT02 TT05

Claims (8)

[Claims] 1. A heater driven by an AC power supply, switching means for controlling conduction to the heater in response to a heater trigger signal instructing conduction of the heater, and a conduction detection signal for detecting a conduction state of the heater. And a malfunction detection logic circuit for detecting a combination of a state and a change of the heater trigger signal and the conduction detection signal that cannot be in a normal state. 2. The heater drive abnormality detection device according to claim 1, further comprising means for urgently stopping heater drive based on an output signal indicating an abnormality from the abnormality determination logic circuit. 3. The abnormality determining logic circuit detects a case where the conduction detection signal already indicates a conduction state when the heater trigger signal indicates conduction of the heater, and generates an abnormal state accordingly. The heater drive abnormality detecting device according to claim 1, wherein the device outputs a signal indicating the following. 4. The abnormality determining logic circuit detects a case where the conduction detection signal changes from a non-conduction state to a conduction state when the heater trigger signal does not indicate conduction of the heater, and responds accordingly. 4. The heater drive abnormality detecting device according to claim 1, wherein the device outputs a signal indicating occurrence of an abnormal state. 5. The abnormality determination logic circuit detects a case where the conduction detection signal does not indicate the conduction state of the heater, even though the heater trigger signal indicates the conduction of the heater. 5. The heater drive abnormality detection device according to claim 1, wherein a signal indicating the occurrence of the occurrence is output. 6. A first flip-flop which receives one of the heater trigger signal and the conduction detection signal at a signal input terminal and captures the signal, and a second flip-flop which receives an output of the first flip-flop at an input terminal and captures the signal. And a non-inverted output of one of the first and second flip-flops and an inverted output of the other are received at first and second input terminals, and the other of the heater trigger signal and the conduction detection signal The heater drive abnormality detecting device according to claim 3, further comprising: a logical product gate receiving the third input terminal at a third input terminal. 7. When the signal indicating the occurrence of the abnormal condition occurs continuously plural times within a predetermined time, it is determined that the signal is abnormal, and the signal is generated plural times continuously within the predetermined time. The heater drive abnormality detecting device according to claim 1, wherein the abnormality is not determined when there is no abnormality. 8. A timer which is activated by a signal indicating occurrence of the abnormal state and generates a time signal having a time width corresponding to the predetermined time, and indicates the occurrence of the abnormal state during the time period of generation of the time signal. A counter that counts the number of signal occurrences, and a comparator that outputs a final signal indicating the occurrence of an abnormal state when the count value of the counter reaches a predetermined value, wherein the timed signal is not generated 8. The heater drive abnormality detecting device according to claim 7, wherein returning to the state resets the counter even before the count value reaches a predetermined value.