CN111834983A - Circuit, method and device for preventing false triggering through IO control of SOC (System on chip) - Google Patents

Circuit, method and device for preventing false triggering through IO control of SOC (System on chip) Download PDF

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Publication number
CN111834983A
CN111834983A CN202010766297.8A CN202010766297A CN111834983A CN 111834983 A CN111834983 A CN 111834983A CN 202010766297 A CN202010766297 A CN 202010766297A CN 111834983 A CN111834983 A CN 111834983A
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unit
voltage
timing
input
output
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CN111834983B (en
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王晓明
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Xinhe Semiconductor Technology Wuxi Co Ltd
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Xinhe Semiconductor Technology Wuxi Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/24—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to undervoltage or no-voltage
    • H02H3/247—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to undervoltage or no-voltage having timing means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16557—Logic probes, i.e. circuits indicating logic state (high, low, O)

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

The invention discloses a method and a device for preventing error triggering of SOC chip IO control, which comprises an SOC chip, wherein a comparison circuit unit, a timing and arbitration unit and an IO BUFFER unit are integrated in the SOC chip, the IO voltage and the core voltage of the SOC chip are monitored through the comparison circuit unit, a hardware timing circuit is started for timing as long as any voltage of the IO voltage or the core voltage falls and the voltage falls to a set threshold, when the voltage falling time exceeds a set time limit, the voltage falling is judged to be power supply abnormality conforming to expectation, the IO BUFFER outputting a Trigger _ Ctrl signal is closed, and therefore a controlled module unit cannot abnormally send an effective signal. The uncertainty of the time for using software to close the IO is avoided, and the complexity of the software is reduced; the problem that the power-on and power-off sequence of the IO power supply and the kernel power supply needs to be considered in a board-level circuit is avoided, the selection range of the power supply chip can be expanded, and the cost is reduced.

Description

Circuit, method and device for preventing false triggering through IO control of SOC (System on chip)
Technical Field
The invention belongs to the technical field of electronic control, and particularly relates to a circuit, a method and a device for preventing error triggering of SOC chip IO control.
Background
In a distributed communication system, a near-end system is arranged near a user side, a main chip is an SOC chip, the SOC chip is in butt joint with a controlled module chip in the whole distributed communication system, data are sent to a far-end system or received from a far-end through a controlled module, the data are all electric signals or optical signals, the controlled module generates signals transmitted on a wired network or an optical fiber, the signals are generated according to a time sequence rule designated by the SOC chip, if the controlled module generates a chaotic error due to control signal abnormity, the control signal is called as false triggering, the signals are sent out when the signals are not sent out, and fig. 1 is a simple transmission system consisting of the near-end system and the far-end system.
In order to prevent false triggering, the current prior art mainly adopts the following two technical solutions:
the first technical scheme is as follows: controlling the power-down sequence of the power supply of the near-end system single board;
the technical scheme is as follows: the power supply of the SOC chip IO on the system single board at the near end is controlled to be 3.3V prior to the power supply of the SOC chip kernel to be 1.1V, so that the signal sent by the SOC chip and used for controlling the controlled module cannot generate abnormal level, namely the controlled module is triggered by mistake due to the fact that the effective control level does not occur when the effective control level does not occur.
As shown in fig. 2, when the power supply of the external power supply 220V of the near-end system board is powered down, the voltage (IO voltage) supplied to the IO of the SOC chip is usually 3.3V or 1.8V, which is much higher than the voltage 1.1V or 0.9V supplied to the power supply of the core of the chip, when the power supply of the external power supply 220V is powered down, the power supply of the 3.3V starts to be powered down as long as the power supply of the 220V is dropped to a certain extent, as long as the power supply of the 3.3V is powered down first, the IO voltage of the SOC chip is powered down first, so that the IOBUFFER of the SOC chip shuts down the power supply first, at this time, the power supply of the internal logic in the core of the chip is powered down again, the logic signal driving level of the control controlled module does not matter, because the IOBUFFER is already shut down, the external level of the SOC chip is determined by the pull-up or pull-down resistor, when the external pull-up, when the external is a pull-down resistor, the Trigger _ Ctrl signal is active at high level. The case where the external pull-up resistor is used is described here.
The technical scheme has the disadvantages that the power failure of the IO power supply of 3.3V or 1.8V on the near-end system single board is strictly controlled to be earlier than the power supply of the kernel, and if the power failure sequence cannot be controlled, the problem of false triggering can occur.
The second technical scheme is as follows: and at the communication interaction time interval of the near-end system and the far-end system, the opposite far-end system is informed, the near-end system SOC chip system possibly cannot work normally, and the SOC chip carries out power supply off control on the controlled module through software implementation.
The technical scheme is as follows: the Trigger _ Ctrl signal is turned off through software, when the SOC chip detects that 220V power supply fails, the SOC chip sends a power supply abnormal interrupt state signal to inform a far-end system, the near-end system single board fails to power down, the near-end system upper application software also knows that 220V power down occurs, the Trigger _ Ctrl signal which controls the controlled module to send an effective signal can be turned off at appointed time, the problem of misoperation of the controlled module can be avoided, and therefore the problem of false triggering of the controlled module is avoided.
In general, due to the fact that the power supply abnormal communication interaction time window is 3-10ms and is very large, the Trigger _ Ctrl signal should be turned off at which time point, and the determination is not good in practice. In addition, the possibility exists that after the 220V power supply is abnormally interrupted, the power supply of the 220V power supply is recovered immediately, at this time, the voltage of the SOC chip power supply 3.3V and the core logic power supply 1.1V may start to drop slightly, and at this time, the Trigger _ Ctrl signal is not suitable to be turned off, and if the Trigger _ Ctrl signal is turned off, the problem of cooperation between the near-end system and the far-end system is caused, so that the problem is enlarged, and the influence is more serious.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a circuit, a method and a device for preventing false triggering of SOC chip IO control, wherein the turn-off of the Trigger _ Ctrl signal of the SOC chip is determined by hardware, and the power-on sequence and the power-off sequence of the IO power supply and the kernel power supply of the SOC chip do not influence the Trigger _ Ctrl signal.
In order to solve the problems, the technical scheme adopted by the invention is as follows:
a method for preventing error trigger of SOC chip IO control includes the following steps
S1) monitoring whether the IO voltage and the kernel voltage of the SOC chip drop or not through a voltage monitoring circuit, and starting a hardware timer to time when any one of the IO voltage and the kernel voltage drops;
s2), when the hardware timer exceeds the set time limit, that is, the voltage drop time exceeds the set time limit, the Trigger _ Ctrl signal causing the controlled module unit to abnormally send out the valid signal is turned off.
In the step S1, the voltage monitoring circuit is a voltage comparison circuit, the IO voltage and the core voltage are respectively compared with a reference voltage, and when any one of the IO voltage and the core voltage drops below the reference voltage compared with the IO voltage or the core voltage, a hardware timer is started to time.
A circuit for preventing error trigger of IO control of an SOC chip comprises the SOC chip, wherein a comparison circuit unit, a timing and arbitration unit and an IOBUFFER unit are integrated in the SOC chip, the comparison circuit unit is used for monitoring whether the drop of IO voltage and core voltage is lower than a reference value or not, the timing and arbitration unit is used for timing when the IO voltage or the core voltage is lower than the reference value and outputting an enable signal to the IOBUFFER unit when the timing time exceeds a set time limit, input signals of the comparison circuit unit are the IO voltage and the core voltage, the output of the comparison circuit unit is connected with the input of the timing and arbitration unit, the output of the timing and arbitration unit is connected with the input of the IOBUFFER unit, the output of the IOBUFFER unit is connected with the input of a controlled module unit, the IO voltage and the core voltage are respectively compared with the reference voltage, and when any one of the voltage drops to be lower than the corresponding reference voltage, the comparison circuit unit outputs a signal to the timing and arbitration unit, the timing and arbitration unit starts timing, and when the timing time exceeds a set time limit, the timing and arbitration unit outputs an enable signal to the IOBUFFER unit to close the output of the IOBUFFER unit.
Preferably, the comparison circuit unit includes a voltage comparator and a dual reference voltage unit, wherein the dual reference voltage unit is used for generating two reference voltages, the voltage comparator is a dual-path voltage comparator, one path of input signal is IO voltage and reference voltage, and is used for comparing whether IO voltage sag is lower than the reference voltage, and the other path of input signal is core voltage and reference voltage, and is used for comparing whether the core voltage sag is lower than the reference voltage.
Preferably, the timing and arbitration unit comprises a timing unit, an arbitration unit and a configuration unit, wherein the input of the timing unit is connected with the output of the comparison circuit unit, the output of the timing unit is connected with the input of the arbitration unit, the output of the arbitration unit is connected with the input of the IOBUFFER unit, and the output of the configuration unit is respectively connected with the input of the timing unit and the input of the arbitration unit; the timing unit is a hardware timing unit for timing, the arbitration unit is a hardware arbitration unit for judging whether the timing time exceeds a set time limit so as to output an enable signal, and the configuration unit is used for configuring specific parameters of the timing unit and the arbitration unit.
A device for preventing error triggering of SOC chip IO control comprises a board-level power supply unit, an SOC chip and a controlled module unit, wherein the output of the board-level power supply unit is connected with the power input ends of the SOC chip and the controlled module unit to supply power to the SOC chip and the controlled module unit, and the output Trigger _ Ctrl of the SOC chip is connected with the controlled module unit; the SOC chip is internally integrated with a comparison circuit unit, a timing and arbitration unit and an IOBUFFER unit, wherein input signals of the comparison circuit unit are IO voltage and core voltage, the output of the comparison circuit unit is connected with the input of the timing and arbitration unit, the output of the timing and arbitration unit is connected with the input of the IOBUFFER unit, the output of the IOBUFFER unit is connected with the input of a controlled module unit, the IO voltage and the core voltage are respectively compared with reference voltage, when any voltage falls below the corresponding reference voltage, the comparison circuit unit outputs a signal to the timing and arbitration unit, the timing and arbitration unit starts timing, and when the timing time exceeds a set time limit, the timing and arbitration unit outputs an enable signal to the IOBUFFER unit to close the output of the IOBUFFER unit.
Preferably, the comparison circuit unit includes a voltage comparator and a dual reference voltage unit, wherein the dual reference voltage unit is used for generating two reference voltages, the voltage comparator is a dual-path voltage comparator, one path of input signal is IO voltage and reference voltage, and is used for comparing whether IO voltage sag is lower than the reference voltage, and the other path of input signal is core voltage and reference voltage, and is used for comparing whether the core voltage sag is lower than the reference voltage.
The timing and arbitration unit preferably comprises a timing unit, an arbitration unit and a configuration unit, wherein the input of the timing unit is connected with the output of the comparison circuit unit, the output of the timing unit is connected with the input of the arbitration unit, the output of the timing unit is connected with the input of the IOBUFFER unit, and the output of the configuration unit is respectively connected with the input of the timing unit and the input of the arbitration unit; the timing unit is a hardware timing unit for timing, the arbitration unit is a hardware arbitration unit for judging whether the timing time exceeds a set time limit so as to output an enable signal, and the configuration unit is used for configuring specific parameters of the timing unit and the arbitration unit.
Adopt the produced beneficial effect of above-mentioned technical scheme to lie in:
the method adopts the hardware circuit to monitor the IO voltage and the kernel voltage of the SOC chip, judge whether the power supply is abnormal or not, and then close the Trigger _ Ctrl, so that the time uncertainty of using software to close the IO is avoided, and the complexity of the software is reduced; the design requirement that the power-on and power-off sequence of the IO power supply and the kernel power supply needs to be considered in a board-level circuit is avoided, the selection range of a power supply chip can be expanded, and therefore the cost of raw materials of the single board is reduced.
Drawings
Fig. 1 is a simple transmission system consisting of a near-end system + a far-end system, which is a typical system to which the present invention is applied;
fig. 2 is a circuit structure diagram for controlling the power supply sequence of the single board IO of the near-end system;
FIG. 3 is a schematic diagram of the circuit configuration of the present invention;
FIG. 4 shows a flow chart and a method for implementing the present invention in practical application.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings:
the invention relates to a circuit, a method and a device for preventing error triggering by SOC chip IO control.
A method for preventing error trigger of SOC chip IO control includes the following steps
S1) monitoring whether the IO voltage and the kernel voltage of the SOC chip drop or not through a voltage monitoring circuit, and starting a hardware timer to time when any one of the IO voltage and the kernel voltage drops;
s2), when the hardware timer exceeds the set time limit, that is, the voltage drop time exceeds the set time limit, the Trigger _ Ctrl signal causing the controlled module unit to abnormally send out the valid signal is turned off.
In the step S1, the voltage monitoring circuit is a voltage comparison circuit, the IO voltage and the core voltage are respectively compared with a reference voltage, and when any one of the IO voltage and the core voltage drops below the reference voltage compared with the IO voltage or the core voltage, a hardware timer is started to time.
The implementation flow of the method in practical application is shown in fig. 4, when the single board power supply drops, the IO power supply and the kernel power supply are affected, the voltage comparison circuit monitors the dropping condition of the IO voltage and the kernel voltage, and the voltage comparison circuit outputs a signal to start the hardware timing circuit to time when the IO power supply drops below a reference value due to the hardware voltage comparison circuit. Meanwhile, when the power supply drop of the kernel is lower than the reference value, the voltage comparison circuit can also output a signal to start the hardware timing circuit to time, namely, the timer can be started as long as any voltage drop of the IO power supply voltage or the power supply voltage of the kernel is lower than the reference value. When the time counted by the timer exceeds the set time, the power failure can be judged to be the power supply abnormality meeting the expectation, and then a signal is output to the arbitration unit, and the arbitration unit closes the output of the IOBUFFER.
As shown in fig. 3, the circuit for preventing mis-triggering for IO control of an SOC chip of the present invention includes an SOC chip, wherein a comparison circuit unit, a timing and arbitration unit, and an IOBUFFER unit are integrated in the SOC chip, the comparison circuit unit is configured to monitor whether drops of an IO voltage and a core voltage are lower than a reference value, the timing and arbitration unit is configured to perform timing when the IO voltage or the core voltage drops below the reference value and output an enable signal to the IO BUFFER unit when a timing time exceeds a set time limit, input signals of the comparison circuit unit are an IO voltage and a core voltage, an output of the comparison circuit unit is connected to an input of the timing and arbitration unit, an output of the timing and arbitration unit is connected to an input of the IOBUFFER unit, an output of the IOBUFFER unit is connected to an input of a controlled module unit, the IO voltage and the core voltage are respectively compared with the reference voltages, and when any one of the voltages drops below the corresponding reference voltage, the comparison circuit unit outputs a signal to the timing and arbitration unit, the timing and arbitration unit starts timing, and when the timing time exceeds a set time limit, the timing and arbitration unit outputs an enable signal to the IO BUFFER unit to close the output of the IO BUFFER unit.
The comparison circuit unit comprises a voltage comparator and a double-reference voltage unit, wherein the double-reference voltage unit is used for generating two reference voltages (Vref1 and Vref2), the voltage comparator is a double-path voltage comparator, one path of input signals are IO voltage and reference voltage and are used for comparing whether IO voltage drop is lower than the reference voltage, and the other path of input signals are kernel voltage and reference voltage and are used for comparing whether the kernel voltage drop is lower than the reference voltage.
The timing and arbitration unit comprises a timing unit, an arbitration unit and a configuration unit, wherein the input of the timing unit is connected with the output of the comparison circuit unit, the output of the timing unit is connected with the input of the arbitration unit, the output of the arbitration unit is connected with the input of the IOBUFFER unit, and the output of the configuration unit is respectively connected with the input of the timing unit and the input of the arbitration unit; the timing unit is a hardware timing unit for timing, the arbitration unit is a hardware arbitration unit for judging whether the timing time exceeds a set time limit so as to output an enable signal, and the configuration unit is used for configuring specific parameters of the timing unit and the arbitration unit.
Description of the working principle:
the IO voltage of an SOC chip (generally an SOC-Systemofchip chip with a built-in processor) is monitored and compared with the core voltage through a voltage comparator, as long as any one of the voltages is found to have a dropping condition, and when the voltage drops to a reference voltage, the voltage comparator outputs a comp _ out indicating level to be provided for a timing and arbitration unit, a timing unit circuit starts timing, when the voltage dropping time exceeds a set time limit, the voltage dropping is considered to be in accordance with expected power supply abnormity, an iobuf _ enable signal for turning off an IOBUFFER is output, the IOBUFFER is turned off, and the condition that the IOBUFFER outputs an abnormal level on a Trigger _ Ctrl signal to cause an abnormal sending of an effective signal of a controlled module unit is prevented.
The whole system is closed from the drop of the power supply voltage to the IOBUFFER without any software intervention and is realized by a hardware circuit. In addition, as the monitoring comparison circuit respectively monitors the IO voltage and the core voltage (the IO voltage and the core voltage are respectively compared with the reference voltage), as long as any one of the IO voltage and the core voltage drops, the logic circuit for closing the IOBUFFER is triggered to act, so that the problem that the board level circuit has clear power-on and power-off sequence requirements on the IO voltage and the core voltage of the chip is solved.
As shown in fig. 3, the present invention further provides a device, which includes a board-level power supply unit, an SOC chip, and a controlled module unit, wherein an output of the board-level power supply unit is connected to power input terminals of the SOC chip and the controlled module unit to supply power to the SOC chip and the controlled module unit, and an output Trigger _ Ctrl of the SOC chip is connected to the controlled module unit. The SOC chip adopts the IO control false triggering prevention control circuit.

Claims (8)

1. A method for preventing error triggering of SOC chip IO control is characterized in that: comprises the following steps
S1) monitoring whether the IO voltage and the kernel voltage of the SOC chip drop or not through a voltage monitoring circuit, and starting a hardware timer to time when any one of the IO voltage and the kernel voltage drops;
s2), when the hardware timer exceeds the set time limit, that is, the voltage drop time exceeds the set time limit, the Trigger _ Ctrl signal causing the controlled module unit to abnormally send out the valid signal is turned off.
2. The method for preventing the false triggering of the IO control of the SOC chip according to claim 1, wherein: the voltage monitoring circuit in step S1 is a voltage comparison circuit, the IO voltage and the core voltage are respectively compared with the reference voltage, and when any one of the IO voltage and the core voltage drops below the reference voltage compared with the IO voltage or the core voltage, the hardware timer is started to time.
3. The utility model provides a circuit that SOC chip IO control prevented false triggering which characterized in that: the SOC comprises an SOC chip, wherein a comparison circuit unit, a timing and arbitration unit and an IO BUFFER unit are integrated in the SOC chip, the comparison circuit unit is used for monitoring whether the drop of IO voltage and core voltage is lower than a reference value or not, the timing and arbitration unit is used for timing when the IO voltage or the core voltage is lower than the reference value and outputting an enable signal to the IO BUFFER unit when the timing time exceeds a set time limit, the input signals of the comparison circuit unit are the IO voltage and the core voltage, the output of the comparison circuit unit is connected with the input of the timing and arbitration unit, the output of the timing and arbitration unit is connected with the input of the IO BUFFER unit, the output of the IO BUFFER unit is connected with the input of a controlled module unit, the IO voltage and the core voltage are respectively compared with the reference voltage, and when any one of the voltages drops to be lower than the corresponding reference voltage, the comparison circuit unit outputs the signal to the timing and arbitration unit, the timing and arbitration unit starts timing, and when the timing time exceeds the set time limit, the timing and arbitration unit outputs an enable signal to the IO BUFFER unit to close the output of the IO BUFFER unit.
4. The SOC chip IO control false triggering prevention circuit of claim 3, wherein: the comparison circuit unit comprises a voltage comparator and a double-reference voltage unit, wherein the double-reference voltage unit is used for generating two reference voltages, the voltage comparator is a double-circuit voltage comparator, one input signal is IO voltage and reference voltage and used for comparing whether IO voltage drop is lower than the reference voltage, and the other input signal is core voltage and reference voltage and used for comparing whether the core voltage drop is lower than the reference voltage.
5. The SOC chip IO control false triggering prevention circuit of claim 3, wherein: the timing and arbitration unit comprises a timing unit, an arbitration unit and a configuration unit, wherein the input of the timing unit is connected with the output of the comparison circuit unit, the output of the timing unit is connected with the input of the arbitration unit, the output of the timing unit is connected with the input of the IO BUFFER unit, and the output of the configuration unit is respectively connected with the input of the timing unit and the input of the arbitration unit; the timing unit is a hardware timing unit for timing, the arbitration unit is a hardware arbitration unit for judging whether the timing time exceeds a set time limit so as to output an enable signal, and the configuration unit is used for configuring specific parameters of the timing unit and the arbitration unit.
6. The utility model provides a device that SOC chip IO control prevented false triggering which characterized in that: the system comprises a board-level power supply unit, an SOC chip and a controlled module unit, wherein the output of the board-level power supply unit is connected with the power input ends of the SOC chip and the controlled module unit to supply power to the SOC chip and the controlled module unit, and the output Trigger _ Ctrl of the SOC chip is connected with the controlled module unit; the SOC chip is internally integrated with a comparison circuit unit, a timing and arbitration unit and an IO BUFFER unit, wherein input signals of the comparison circuit unit are IO voltage and core voltage, the output of the comparison circuit unit is connected with the input of the timing and arbitration unit, the output of the timing and arbitration unit is connected with the input of the IO BUFFER unit, the output of the IO BUFFER unit is connected with the input of a controlled module unit, the IO voltage and the core voltage are respectively compared with reference voltages, when any voltage falls to be lower than the corresponding reference voltage, the comparison circuit unit outputs a signal to the timing and arbitration unit, the timing and arbitration unit starts timing, and when the timing time exceeds a set time limit, the timing and arbitration unit outputs an enable signal to the IO BUFFER unit to close the output of the IO BUFFER unit.
7. The device for preventing the IO control of the SOC chip according to claim 6, wherein: the comparison circuit unit comprises a voltage comparator and a double-reference voltage unit, wherein the double-reference voltage unit is used for generating two reference voltages, the voltage comparator is a double-circuit voltage comparator, one input signal is IO voltage and reference voltage and used for comparing whether IO voltage drop is lower than the reference voltage, and the other input signal is core voltage and reference voltage and used for comparing whether the core voltage drop is lower than the reference voltage.
8. The device for preventing the IO control of the SOC chip according to claim 6, wherein: the timing and arbitration unit comprises a timing unit, an arbitration unit and a configuration unit, wherein the input of the timing unit is connected with the output of the comparison circuit unit, the output of the timing unit is connected with the input of the arbitration unit, the output of the timing unit is connected with the input of the IO BUFFER unit, and the output of the configuration unit is respectively connected with the input of the timing unit and the input of the arbitration unit; the timing unit is a hardware timing unit for timing, the arbitration unit is a hardware arbitration unit for judging whether the timing time exceeds a set time limit so as to output an enable signal, and the configuration unit is used for configuring specific parameters of the timing unit and the arbitration unit.
CN202010766297.8A 2020-08-03 2020-08-03 Circuit, method and device for preventing false triggering through IO control of SOC (System on chip) Active CN111834983B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103138716A (en) * 2013-01-31 2013-06-05 深圳威迈斯电源有限公司 Power down triggered monostable protection circuit
CN110032263A (en) * 2019-04-15 2019-07-19 苏州浪潮智能科技有限公司 A kind of server and its power-down protection circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103138716A (en) * 2013-01-31 2013-06-05 深圳威迈斯电源有限公司 Power down triggered monostable protection circuit
CN110032263A (en) * 2019-04-15 2019-07-19 苏州浪潮智能科技有限公司 A kind of server and its power-down protection circuit

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