CN211127759U - Automatic reset circuit and electronic equipment - Google Patents
Automatic reset circuit and electronic equipment Download PDFInfo
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- CN211127759U CN211127759U CN201922092616.7U CN201922092616U CN211127759U CN 211127759 U CN211127759 U CN 211127759U CN 201922092616 U CN201922092616 U CN 201922092616U CN 211127759 U CN211127759 U CN 211127759U
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Abstract
The utility model relates to an automatic reset circuit and electronic equipment, wherein the automatic reset circuit is used for sending reset signals to the reset end of a main control chip, and the main control chip outputs first signals which indicate normal work to the automatic reset circuit at regular time; the automatic reset circuit includes: the input end of the charging and discharging circuit is connected with the output end of the main control chip, which is used for outputting the first signal; and the level conversion circuit comprises a switch control element and a current-limiting resistor which are connected in series, the control end of the switch control element is connected with the output end of the charge-discharge circuit, and the output end of the level conversion circuit is connected with the reset end of the main control chip. The utility model is used for realize system automatic re-setting when electronic equipment's system software crashes or the procedure runs to fly.
Description
Technical Field
The utility model belongs to the technical field of communication, concretely relates to automatic reset circuit and have its electronic equipment.
Background
At present, there are many reset methods for electronic devices (e.g. bluetooth headsets, etc.), such as full hardware key reset and full software watchdog automatic reset. Although the resetting of the full hardware key is reliable, manual intervention is required, and the user experience is poor; the reset of the full software watchdog sometimes causes the condition that the reset cannot be carried out due to the error of relevant code software of the watchdog, and the reset is unreliable, so that actually, in many existing products, a hard reset circuit is also added, and when a system crashes or a program runs off, the system is reset by manual participation through input triggering of keys and the like.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an automatic re-setting circuit and electronic equipment realizes resetting system automatic re-setting when electronic equipment's system software crashes or the procedure runs to fly, and it is reliable to reset, promotes user experience.
In order to solve the technical problem, the utility model provides a following technical scheme solves:
an automatic reset circuit is used for sending a reset signal to a reset end of a main control chip, and the main control chip outputs a first signal which represents normal work to the automatic reset circuit at regular time; the automatic reset circuit includes: the input end of the charging and discharging circuit is connected with the output end of the main control chip for outputting the first signal; and the level conversion circuit comprises a switch control element and a current-limiting resistor which are connected in series, the control end of the switch control element is connected with the output end of the charge and discharge circuit, and the output end of the level conversion circuit is connected with the reset end of the main control chip.
In the automatic reset circuit, the charge and discharge circuit is an RC circuit connected in parallel.
The automatic reset circuit comprises a charging and discharging circuit, a main control chip and an RC circuit, wherein the charging and discharging circuit comprises a capacitor, a diode and a resistor, the capacitor is connected with the main control chip, the diode is connected with the main control chip, and the resistor is connected with the RC circuit.
In the automatic reset circuit, the switching control element is a switching element that is turned on at a low level or a switching element that is turned on at a high level.
In the automatic reset circuit, when the switching control element is a switching element that is turned on at a low level, the switching control element is a PMOS transistor.
In the automatic reset circuit, the gate of the PMOS transistor is connected to the output terminal of the charge and discharge circuit, the source is connected to the dc power supply of the level shift circuit, and the drain is grounded through the current-limiting resistor; and the reset end of the main control chip is connected between the drain electrode of the PMOS tube and the current-limiting resistor.
In the automatic reset circuit, when the switch control circuit is a high-level conducting switch element, the switch control element is an NMOS transistor;
in the automatic reset circuit, the gate of the NMOS transistor is connected to the output terminal of the charge and discharge circuit, the source is grounded, and the drain is connected to the dc power supply of the level shift circuit through the current-limiting resistor; and the reset end of the main control chip is connected between the drain electrode of the NMOS tube and the current-limiting resistor.
The automatic reset circuit as described above, the interval time of the main control chip outputting the first signal is less than the discharge time of the charge and discharge circuit, wherein during the discharge time, the output voltage of the charge and discharge circuit is on average greater than the threshold level of the switch control element.
The embodiment also relates to an electronic device, which comprises a main control chip with a reset terminal and the automatic reset circuit; the main control chip outputs a first signal indicating normal work to the automatic reset circuit at regular time; the automatic reset circuit outputs a reset signal to a reset end of the main control chip.
Compared with the prior art, the utility model discloses an automatic reset circuit's advantage and beneficial effect are: by designing the charge and discharge circuit and the level conversion circuit, when the system works normally, the output end of the level conversion circuit is maintained to output a low level through the interval charge of the charge and discharge circuit, at the moment, the level received by the reset end of the main control chip is the low level, the system keeps working normally, and when the system is abnormal, the output end of the level conversion circuit outputs a high level through the discharge of the charge and discharge circuit, at the moment, the level received by the reset end of the main control chip is the high level, the system resets, the whole process does not need manual participation, automatic reset is realized, and the charge and discharge circuit and the level conversion circuit work stably in the embodiment, and the reset reliability is improved; and the reliable automatic reset method improves the use reliability and the use experience of the electronic equipment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments of the present invention or the description of the prior art will be briefly described below, and it is obvious that the drawings described below are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a block diagram of an embodiment of an automatic reset circuit according to the present invention connected to a main control chip;
FIG. 2 is a first circuit diagram of the embodiment of the automatic reset circuit shown in FIG. 1 connected to a main control chip;
fig. 3 is a second circuit diagram of the automatic reset circuit of fig. 1 connected to a main control chip.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Example one
In order to realize that a system can be reliably and automatically Reset when abnormal work such as system halt or program runaway and the like occurs in an electronic device (for example, a bluetooth headset), as shown in fig. 1, the present embodiment relates to an automatic Reset circuit, which is used for resetting a main control chip 1, where the main control chip 1 has an input/output port I/O port and a Reset terminal Reset, and the main control chip 1 outputs a first signal indicating normal work to the automatic Reset circuit at regular time, such as the I/O port in fig. 1 outputs the first signal; the automatic reset circuit includes: the input end of the charge-discharge circuit 2 is connected with the I/O port of the main control chip 1; and the level conversion circuit 3 comprises a switch control element and a current-limiting resistor which are connected in series, the control end of the switch control element is connected with the output end of the charge and discharge circuit 2, and the output end of the level conversion circuit 3 is connected with the Reset end Reset of the main control chip 1. It is understood that the current limiting resistor in this embodiment is not necessarily a resistor, and may be a resistor formed by connecting a plurality of resistors in parallel or in series, or by using a mixture of series and parallel.
When the system works normally, the main control chip 1 outputs a first signal at the I/O port at regular time, the first signal in this embodiment is at a high level, and is used for charging the charging and discharging circuit 2 when the system works normally, and when the system works normally, because the main control chip 1 outputs the first signal to the I/O port at regular time, when the system works normally, the charging and discharging circuit 2 will receive the first signal to perform a discharging process after charging, in order to ensure that the level output by the level conversion circuit 3 when the system works normally is at a low level, the level output by the charging and discharging circuit 2 needs to control the state (on or off) of the switching control element at least so as to satisfy that the output level of the level conversion circuit 3 is at a low level, so that when the system works normally, even if there is a discharging process of the charging and discharging circuit 2, the output level of the charging and discharging circuit 2 will not control the state of the switching control element so as to satisfy that the level conversion circuit is Way 3 outputs high.
As shown in fig. 2 and fig. 3, the charging and discharging circuit 2 of this embodiment adopts an RC circuit formed by connecting a resistor R2 and a charging capacitor C1 in parallel, and charges through the charging capacitor C1 when the I/O port of the main control chip 1 outputs a high level. In addition, in order to avoid backward current flowing to the I/O port of the main control chip 1 when the charging capacitor C1 discharges, a diode D1 is connected between the I/O port of the main control chip 1 and the input end of the charging and discharging circuit 2, and the anode of the diode D1 is connected with the I/O port of the main control chip 1 and the cathode of the diode D is connected with the anode of the charging capacitor C1.
Fig. 2 shows the first circuit diagram of the embodiment of the automatic reset circuit of the present invention connected to the main control chip 1, and fig. 3 shows the second circuit diagram of the embodiment of the automatic reset circuit of the present invention connected to the main control chip 1, and the difference point of these two circuit diagrams is the level shift circuit 3.
The level shift module 3 in the first circuit diagram includes a switching element and a pull-down current-limiting resistor R1 which are connected in series and are switched on at a low level, an output end of the level shift module 3 is connected between a signal end of the switching element and the pull-down current-limiting resistor R1, when the system is normal, the charge and discharge circuit 2 is continuously charged, the switching element which is switched on at the low level is not switched on, at this time, the level shift circuit 3 outputs the low level to a Reset end Reset, and when the system is abnormal, the charge and discharge circuit 2 discharges to an output level to switch on the switching element which is switched on at the low level, at this time, the level shift circuit 3 outputs the high level to the Reset end Reset, so that.
Specifically, as shown in fig. 2, the low-level conducting switch element in this embodiment is a PMOS transistor Q1, the gate G is connected to the output terminal of the charge and discharge circuit 2, the source S is connected to the dc power source VCC, the drain D is grounded through a pull-down current-limiting resistor R1, and the Reset terminal Reset of the main control chip 1 is connected between the drain D of the PMOS transistor Q1 and the pull-down current-limiting resistor R1. When the system normally works, the I/O port of the main control chip 1 outputs a high level at intervals, the charging capacitor C1 is continuously charged through the diode D1, the charging capacitor C1 slowly discharges through the resistor R2 during the period that the I/O port does not output a high level, the I/O port outputs a high level again before the level of the charging capacitor C1 discharges to the threshold level of the PMOS transistor Q1, and the charging capacitor C1 continues to be charged at this time, so that the PMOS transistor Q1 can be kept off during the normal work of the system, the level conversion circuit 3 outputs a low level, the signal received by the Reset terminal Reset is also a low level, and the main control chip 1 cannot be Reset; when the I/O port of the main control chip 1 outputs a high level to the charge and discharge module 2 when the system works abnormally, the charge capacitor C1 discharges slowly through the resistor R2, after the level of the charge capacitor C1 discharges to the threshold level of the PMOS transistor Q1, the PMOS transistor Q1 is turned on, the level conversion circuit 3 outputs a high level, a signal received by the Reset terminal Reset is also a high level, so that the main control chip 1 can be Reset, and the system works normally again.
The level shift module 3 in the second circuit diagram includes a switch element and a pull-up current limiting resistor R1 which are connected in series and are switched on at a high level, an output end of the level shift module 3 is connected between a signal end of the switch element and the pull-up current limiting resistor R1, when the system is normal, the charge and discharge circuit 2 is continuously charged, the switch element which is switched on at the high level is switched on, at this time, the level shift circuit 3 outputs a low level to a Reset end Reset, and when the system is abnormal, the charge and discharge circuit 2 discharges to an output level to cut off the switch element which is switched on at the high level, at this time, the level shift circuit 3 outputs a high level to the Reset end Reset, so as to realize system Reset.
Specifically, as shown in fig. 3, the switching element turned on at a high level in this embodiment is an NMOS transistor Q2, the gate G is connected to the output terminal of the charge and discharge circuit 2, the source S is grounded, the drain D is connected to the dc power supply VCC through a pull-up current limiting resistor R1, and the Reset terminal Reset of the main control chip 1 is connected between the drain D of the NMOS transistor Q2 and the pull-up current limiting resistor R1. When the system works normally, the I/O port of the main control chip 1 outputs a high level at intervals, the charging capacitor C1 is continuously charged through the diode D1, the charging capacitor C1 discharges slowly through the resistor R2 during the period that the I/O port does not output a high level, the I/O port outputs a high level again before the level of the charging capacitor C1 discharges to the threshold level of the NMOS transistor Q2, and the charging capacitor C1 charges continuously at the time, so that the NMOS transistor Q2 can be kept on during the normal working period of the system, the level conversion circuit 3 outputs a level, a signal received by the Reset terminal Reset is also a low level, and the main control chip 1 cannot be Reset; when the I/O port of the main control chip 1 outputs a high level to the charge/discharge module 2 when the system works abnormally, the charge capacitor C1 discharges slowly through the resistor R2, after the level of the charge capacitor C1 discharges to the threshold level of the NMOS transistor Q2, the NMOS transistor Q2 is cut off, the level conversion circuit 3 outputs a high level, a signal received by the Reset terminal Reset is also a high level, so that the main control chip 1 can be Reset, and the system works normally again.
Example two
The embodiment also relates to an electronic device (for example, a bluetooth headset) which comprises a main control chip 1 and an automatic reset circuit; the main control chip 1 has an I/O port and a Reset terminal Reset at an input end and an output end, and the structure and the working principle of the automatic Reset circuit of this embodiment refer to fig. 1 to fig. 3 and the description of the first embodiment thereof, which are not described herein again.
The main control chip 1 outputs a first signal indicating normal operation to the automatic Reset circuit at the I/O port at regular time, that is, the input end of the automatic Reset circuit is connected to the I/O port of the main control chip 1, and the output end of the automatic Reset circuit is connected to the Reset end Reset of the main control chip 1, and is configured to send a Reset signal to the Reset end Reset, so that when the system normally operates, the level received by the Reset end Reset is low level to maintain normal operation of the system, and when the system abnormally operates, the level received by the Reset end Reset is high level to Reset the system, and thereafter, the system normally operates again.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (9)
1. An automatic reset circuit, it is used for sending reset signal to the reset end of main control chip, its characterized in that, main control chip regularly to automatic reset circuit output shows the first signal of normal work, automatic reset circuit includes:
the input end of the charging and discharging circuit is connected with the output end of the main control chip for outputting the first signal;
and the level conversion circuit comprises a switch control element and a current-limiting resistor which are connected in series, the control end of the switch control element is connected with the output end of the charge and discharge circuit, and the output end of the level conversion circuit is connected with the reset end of the main control chip.
2. The automatic reset circuit of claim 1, wherein the charge and discharge circuit is a parallel RC circuit.
3. The automatic reset circuit of claim 2, wherein the charge and discharge circuit further comprises a diode, an anode of the diode is connected to the output terminal of the main control chip, and a cathode of the diode is connected to the input terminal of the RC circuit.
4. The automatic reset circuit of claim 1, wherein the switch control element is a low-level conducting switch element or a high-level conducting switch element.
5. The automatic reset circuit of claim 4, wherein when the switch control element is a low-level conducting switch element, the switch control element is a PMOS transistor.
6. The automatic reset circuit of claim 5, wherein the gate of the PMOS transistor is connected to the output terminal of the charge and discharge circuit, the source is connected to the DC power supply of the level shift circuit, and the drain is grounded via the current limiting resistor; and the reset end of the main control chip is connected between the drain electrode of the PMOS tube and the current-limiting resistor.
7. The automatic reset circuit of claim 4, wherein when the switch control element is a high-level conducting switch element, the switch control element is an NMOS transistor.
8. The automatic reset circuit of claim 7, wherein the gate of the NMOS transistor is connected to the output terminal of the charge and discharge circuit, the source is grounded, and the drain is connected to the dc power supply of the level shift circuit through the current limiting resistor; and the reset end of the main control chip is connected between the drain electrode of the NMOS tube and the current-limiting resistor.
9. An electronic device comprising a main control chip having a reset terminal, wherein the electronic device further comprises the automatic reset circuit of any one of claims 1 to 8; the main control chip outputs a first signal indicating normal work to the automatic reset circuit at regular time; the automatic reset circuit outputs a reset signal to a reset end of the main control chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922092616.7U CN211127759U (en) | 2019-11-28 | 2019-11-28 | Automatic reset circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922092616.7U CN211127759U (en) | 2019-11-28 | 2019-11-28 | Automatic reset circuit and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211127759U true CN211127759U (en) | 2020-07-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922092616.7U Active CN211127759U (en) | 2019-11-28 | 2019-11-28 | Automatic reset circuit and electronic equipment |
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| Country | Link |
|---|---|
| CN (1) | CN211127759U (en) |
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2019
- 2019-11-28 CN CN201922092616.7U patent/CN211127759U/en active Active
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