JP2001223549A - Gain control circuit and radio communication equipment using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that current consumption becomes large since the current value of a constant current source is to be set large when the characteristics of low NF and high IIP 3 are simultaneously to be satisfied in a gain variable amplifier. SOLUTION: An up side variable amplification part 32 where gain variable amplifiers 21U and 22U are cascade-connected and a down side variable amplification part 32 where gain variable amplifiers 21D and 22D are cascade-connected are connected in parallel between an input terminal 37 and an output terminal 38. The peculiar point of the up side variable amplification part 31 and that of the down side variable amplification part 32 are overlapped and a bias change-over switch part 36 control a system so that paths (the path of the up side variable 32) where a signal passes are switched at the point.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gain control circuit and a radio communication apparatus using the same, and more particularly, to a gain control circuit suitable for power control in a communication field such as a mobile communication system, and a method using the same. The present invention relates to a wireless communication device.

[0002]

2. Description of the Related Art In the field of communication and the like, signals from a weak level to a large amplitude level are handled. Therefore, a variable gain amplifier having a wide variable gain range is required. At that time, the following two characteristics become important as the variable gain amplifier. That is, as one of them, when the input signal is small, the noise is small. In other words, low NF (noise figure) at high gain
That. Second, when the input signal is large, the output should not be distorted by the input. In other words, high IIP3 (input intercept point) at low gain.

FIG. 13 shows a circuit example of a general variable gain amplifier. In FIG. 1, a variable gain amplifier 100 according to the present embodiment includes a differential amplifier circuit 101, two current dividing circuits 102 and 103, two resistor networks 104 and 105, a control voltage (Vc) generating source 106, and a bias voltage ( Vb) It has a configuration having a source 107.

The differential amplifier circuit 101 includes an npn-type differential pair transistor Q101, Q102, emitter resistors R101, R102 connected in series between the emitters of the differential pair transistors Q101, Q102, and these emitter resistors. It comprises a constant current source Io connected between the common connection point of R101 and R102 and the ground.

[0005] One current dividing circuit 102 is composed of npn-type differential pair transistors Q103 and Q104 each having an emitter commonly connected to the collector of the transistor Q101. The other current dividing circuit 103 includes an npn-type differential pair of transistors Q105 and Q1 each having an emitter commonly connected to the collector of the transistor Q102.
06.

In these current dividing circuits 102 and 103, the bases of transistors Q103 and Q105 are commonly connected to the positive side of control voltage generating source 106,
The bases of the transistors Q104 and Q106 are commonly connected to the negative side of the control voltage source 106. The bias voltage source 107 is connected between the negative side of the control voltage source 106 and the ground.

One resistor network 104 is connected between the resistors R103 and R104 connected between the collectors of the differential pair transistors Q103 and Q104 and the power supply VCC and between the collectors of the differential pair transistors Q103 and Q104. And a resistor R105.

The other resistor network 105 is connected between the resistors R106 and R107 connected between the collectors of the differential pair transistors Q105 and Q106 and the power supply VCC, and between the collectors of the differential pair transistors Q105 and Q106. And a resistor R108.

In the variable gain amplifier 100 having the above configuration, the bases of the differential pair transistors Q101 and Q102 are connected to the input terminals INX and IN, respectively.
A signal input Vi is applied between NX and IN. The collectors of the transistors Q103 and Q105 are connected to the output terminal O.
UT, OUTX, and these output terminals OUT, O
A signal output Vo is derived from between UTX. The gain is controlled by changing the current flowing through the resistors R103 and R106 of the resistor networks 104 and 105 according to the control voltage Vc. In FIG.
4 shows gain characteristics of the variable gain amplifier 100.

[0010]

In the variable gain amplifier 100 having the above configuration, the NF is equal to the emitter resistance R10.
1 and R102 can be lowered by reducing the respective resistance values. If the resistances of the emitter resistors R101 and R102 are increased or the current value of the constant current source Io is increased, the dynamic range of the input is increased, and the IIP3 is increased.

As is apparent from this, for each resistance value of the emitter resistors R101 and R102, NF and II
Each characteristic of P3 is a conflicting setting condition. Therefore,
In order to satisfy both the characteristics of the low NF and the high IIP3 at the same time, the current value of the constant current source Io must be set large, and as a result, the current consumption of the variable gain amplifier 100 becomes large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a gain capable of achieving both low NF characteristics at high gain and high IIP3 characteristics at low gain with low current consumption. It is to provide a control circuit and a wireless communication device using the same.

[0013]

According to the present invention, there is provided a gain control circuit comprising: a first circuit portion exhibiting a low NF characteristic at a high gain;
A gain varying means in which a second circuit section exhibiting a high IIP3 characteristic at low gain is connected in parallel between an input terminal and an output terminal; and a circuit for superimposing characteristics of each circuit section in the gain varying means. The configuration includes offset voltage means for generating an offset voltage, and switching means for switching a signal path of the gain variable means according to the gain. This gain control circuit is used as a transmission or reception system amplifying means in a wireless communication device such as a mobile phone device.

In the gain control circuit having the above-described configuration and a wireless communication apparatus using the same, a first circuit section exhibiting a low NF characteristic at a high gain, and a second circuit section exhibiting a high IIP3 characteristic at a low gain.
When the offset voltage is applied from the offset voltage generating means, the circuit portions of the circuit portions are superimposed on each other. The switching means switches a signal path of the gain varying means, that is, a path through which the signal passes through the first circuit unit and a path through which the signal passes through the second circuit unit, according to the gain.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the gain control circuit according to the first embodiment of the present invention. In FIG. 1, the gain control circuit according to the first embodiment includes two variable gain amplifiers 11 and 12, a control voltage generator 13,
The configuration includes two offset voltage generation units 14 and 15 and a bias switch unit 16.

As the two variable gain amplifiers 11 and 12, for example, those having a circuit configuration shown in FIG. 13 are used. The variable gain ranges of these amplifiers 11 and 12 are limited to a certain range by the maximum gain MaxGain and the minimum gain MinGain, and have a finite width.

The input terminals of the variable gain amplifiers 11 and 12 are connected to input terminals 1 through capacitors C11 and C12.
7 and each output terminal is connected to an output terminal 18 via capacitors C13 and C14. That is, the variable gain amplifiers 11 and 12 are connected to the input terminal 11 and the output terminal 1.
8 are connected in parallel.

The variable gain amplifier 11 has a gain characteristic as shown in FIG. 2A and is a low NF amplifier. This variable gain amplifier 11 is referred to as an “up-side amplifier” because it has a positive gain. On the other hand, the variable gain amplifier 12
Has a gain characteristic as shown in FIG.
This is a P3 amplifier. This variable gain amplifier 12 is referred to as a Down side amplifier because it has a negative gain.

The control voltage generator 13 generates a control voltage Vc1 according to the external gain control input voltage Vcont. The control voltage Vc1 output from the control voltage generator 13 is supplied to the Up-side amplifier 11 and the Down-side amplifier 12.
The reference voltage of the control voltage Vc1 is Down
It is supplied to the side amplifier 12 and the offset voltage generator 14.

The offset voltage generating section 14 is provided in the state shown in FIG.
Generates an offset voltage Voff1 indicated by the gain characteristic of FIG. The offset voltage Voff1 is supplied to the offset voltage generator 15 and the bias switch unit 16. The offset voltage generator 15 generates an offset voltage Voff2 shown in the gain characteristic of FIG. This offset voltage Voff2 is determined by the Up-side amplifier 1
1 is supplied.

When the control voltage Vc1 is smaller than (reference voltage + Voff1), the bias voltage switching unit 16 supplies a bias to the Down-side amplifier 12 and stops supplying a bias to the Up-side amplifier 11. When the control voltage Vc1 is equal to or higher than (reference voltage + Voff1), Dow
The bias supply to the n-side amplifier 12 is stopped and Up
The bias is switched so as to supply the bias to the side amplifier 11.

Next, the circuit operation of the gain control circuit according to the first embodiment having the above configuration will be described. First, when the control voltage Vc1 is smaller than the voltage of (reference voltage + Voff1), the bias switch 16
Since the bias is supplied only to the down-side amplifier 12, only the down-side amplifier 12 operates.

When the control voltage Vc1 is (reference voltage + V
When the voltage reaches the voltage of off1), the bias switch unit 16 stops supplying the bias to the Down-side amplifier 12 and supplies the bias to the Up-side amplifier 11. As a result, the operation of the Down-side amplifier 12 stops, and the Up-side amplifier 11 starts operating.

When the control voltage Vc1 is higher than the voltage of (reference voltage + Voff1), only the Up-side amplifier 11 operates. As a result, the gain control circuit as a whole has gain characteristics as shown in FIG.

As described above, the path through which the signal passes (the path of the Up-side amplifier 11 / the path of the Down-side amplifier 12) is switched between when the gain is a plus gain and when the gain is a minus gain. Side amplifier 11 and Do
When the gain variable amplifier having the circuit configuration shown in FIG. 13 is used as the wn-side amplifier 12, the NF can be reduced at a high gain and the input at a low gain without setting a large current value of the constant current source Io. NF characteristic at high gain and high IIP3 at low gain without increasing current consumption.
The characteristic and the characteristic can be compatible.

When a variable gain amplifier having the circuit configuration shown in FIG. 13 is used as the Up-side amplifier 11 and the Down-side amplifier 12, a current proportional to the absolute temperature is supplied to the constant current source Io to obtain a differential. Transistor Q1
It is possible to suppress the gain variation of the amplifier due to the temperature characteristics of the transfer conductance of the amplifiers 01 and Q102.

However, the transistors Q103 to Q10
Since the slope of the gain characteristic with respect to the control voltage Vc changes due to the temperature characteristic of No. 6, the gain characteristic of one stage of the amplifier has a variation in gain due to temperature as shown in FIGS. 3 (a) and 3 (b). Become. For this reason, there is a concern that the temperature characteristic of the entire gain characteristic may have a characteristic that the gain does not have continuity as shown in FIG.

By the way, the gain curves shown in FIGS. 3A and 3B are the real gains (MaxGa) of one amplifier.
The characteristic is substantially point-symmetric with respect to a point (center gain) showing a gain of (in + MinGain) / 2. Using this characteristic, multiple stages of variable gain amplifiers are cascaded and the operating range of each stage is overlapped to compensate for excess or deficiency in gain between each stage, and the overall linearity of the gain curve Has been proposed by the present applicant (Japanese Patent Application Laid-Open No. H8-4646).
No. 3).

A specific configuration of the gain control circuit according to the prior application will be briefly described with reference to FIG. In FIG. 4, the gain control circuit according to the second embodiment has a configuration including two variable gain amplifiers 21 and 22, a control voltage generator 23, and an offset voltage generator 24. As the two variable gain amplifiers 21 and 22, for example, those having a circuit configuration shown in FIG. 13 are used.

The amplifiers 21 and 22 are connected to a capacitor C2.
2, the input terminal of the first-stage amplifier 21 is connected to the input terminal 25 via the capacitor C21, and the output terminal of the second-stage amplifier 22 is connected to the output terminal 26 via the capacitor C23. I have. The first-stage and second-stage amplifiers 21 and 22 each have gain characteristics shown in FIG.

The control voltage generator 23 generates a control voltage Vc2 according to the external gain control input voltage Vcont. The control voltage Vc2 output from the control voltage generator 23 is supplied to each of the variable gain amplifiers 21 and 22. The reference voltage of the control voltage Vc2 is supplied to the first-stage amplifier 21 and the offset voltage generator 24.

The offset voltage generator 24 generates the offset voltage Voff3 shown in the gain characteristic of FIG. 5A in order to overlap the operation ranges of the first-stage amplifier 21 and the second-stage amplifier 22. As the offset voltage Voff3, a voltage of Vt · ln (G) is given. Here, Vt is the threshold voltage of the bipolar transistor, and G is G = (antilogarithm of MaxGain) / (antilogarithm of MinGain). This offset voltage Voff3 is supplied to the second-stage amplifier 24.

As described above, the variable gain amplifiers are connected in cascade, for example, in two stages, and a predetermined offset voltage Voff3 is applied to the second stage amplifier 24 to overlap the operation range of each stage, so that each stage can be connected. Since the excess or deficiency of the gain can be compensated for, the linearity of the gain characteristic can be improved as a whole.

However, the linearity of the gain characteristic is improved, but the slope of the characteristic differs with temperature. For this reason, when converting the external gain control input voltage Vcont to the internal control voltage Vc2 in the control voltage generation unit 23, a term having a temperature characteristic is added. As a result, it is possible to obtain a characteristic as shown in FIG.

At this time, the following relationship is provided between the control voltage Vc2 and the external gain control input voltage Vcont. Vc2 = Vcont + α (T−To) Here, T is a temperature, To is a reference temperature, and α is a temperature-voltage conversion coefficient.

FIG. 5B shows a characteristic in which two stages of variable gain amplifiers are connected in cascade and the temperature characteristic of the gain is corrected. A1 and A2 can be provided.
As described above, the technique of improving the linearity of the gain characteristic by cascade-connecting a plurality of variable gain amplifiers can be applied to the Down-side amplifier and the Up-side amplifier described in the first embodiment.

First, based on the configuration of FIG. 4, FIG. 6 shows a configuration in which the two-stage cascaded Down-side amplifiers emphasizing the IIP3 characteristics described in the first embodiment are cascaded. In FIG. 6, the same parts as those in FIG. 4 are denoted by the same reference numerals. The Down side amplifiers 21D and 22D have gain characteristics shown in FIG.

Here, the offset voltage generator 24 'sets an offset voltage for temperature characteristic adjustment in accordance with a gain variable width due to the cascade connection of the Down-side amplifiers 21D and 22D, and sets the offset voltage as the offset voltage Voff4 in the second stage. The signal is supplied to the Down-side amplifier 22D. As a result, the gain characteristic for Down becomes as shown in the gain characteristic of FIG. 7B, and singular points Down1 and Down2 whose gain does not change with temperature can be provided.

Next, based on the configuration of FIG. 4, FIG. 8 shows a configuration in which the two-stage Up-side amplifier emphasizing the NF characteristic described in the first embodiment is cascaded. In FIG. 8, the same parts as those in FIG. 4 are denoted by the same reference numerals. The Up-side amplifiers 21U and 22U have gain characteristics shown in FIG.

The two offset voltage generators 24-
1 and 24-2, the offset voltage Voff4 generated by the offset voltage generator 24-1 is supplied to the first-stage Up-side amplifier 21U, and the temperature characteristic adjustment offset voltage Voff3 generated by the offset voltage generator 24-2. To the second stage U
The signal is supplied to the p-side amplifier 22U. This allows U
The gain characteristic for p becomes as shown in the gain characteristic of FIG. 9B, and the singular point Up at which the gain does not vary with temperature.
1, Up2 can be provided.

A combination of the configuration of FIG. 6 and the configuration of FIG. 8 is a gain control circuit according to the second embodiment of the present invention. FIG. 10 is a block diagram showing the configuration of the gain control circuit according to the second embodiment of the present invention.
The same parts are denoted by the same reference numerals.

In FIG. 10, the gain control circuit according to the second embodiment includes an Up-side variable amplifier 31, a Down-side variable amplifier 32, a control voltage generator 33, two offset voltage generators 34 and 35, and a bias switch. A switch unit 36 is provided, and the Up-side variable amplifying unit 31 and the Down-side variable amplifying unit 32 are connected in parallel between an input terminal 37 and an output terminal 38.

In the above configuration, the Up-side variable amplifier 3
As shown in FIG. 8, for example, two variable gain amplifiers 21U and 22U connected in cascade are used as shown in FIG.
As shown in FIG. 6, for example, the variable gain amplifier 21 connected in two stages in cascade is used as the own variable amplifier 32.
D, 22D are used. The Up-side variable amplifying unit 31 has a gain characteristic shown in FIG. This gain characteristic corresponds to the gain characteristic in FIG. The down-side variable amplifier 32 has a gain characteristic shown in FIG. This gain characteristic corresponds to the gain characteristic in FIG.

The control voltage generator 33 generates a control voltage Vc2 according to the external gain control input voltage Vcont. This control voltage Vc2
Are the first-stage and second-stage amplifiers 21 of the Up-side variable amplifier 31.
U, 22U, and are supplied to the first-stage and second-stage amplifiers 21D and 22D of the Down-side variable amplification unit 32 and the bias switch unit 36, respectively.

The reference voltage of the control voltage Vc 2 is supplied to the first-stage amplifier 21 D and the offset voltage generator 34 of the Down side variable amplifier 32. The offset voltage generator 34 is the offset voltage generator 24 shown in FIG.
8 corresponds to the offset voltage generator 24-1 in FIG.
Further, the offset generator 35 corresponds to the offset voltage generator 24-2 in FIG.

That is, the offset voltage generating section 34
An offset voltage Voff4 shown in each gain characteristic of FIGS. 11A and 11B is generated. This offset voltage Vof
f4 is the first-stage amplifier 21U of the Up-side variable amplifying unit 31,
The voltage is supplied to the second-stage amplifier 22D of the Down-side variable amplifying unit 32 and the bias switch unit 36, respectively. The offset voltage generator 35 generates an offset voltage Voff3 shown in the gain characteristic of FIG. This offset voltage Voff3 is supplied to the Up-side variable amplifier 31.
Is supplied to the second stage amplifier 22U.

When the control voltage Vc2 is smaller than the voltage of (reference voltage + Voff4), the bias voltage switching unit 36 supplies a bias to the Down variable amplifier 32 and a bias to the Up variable amplifier 31. The supply is stopped, and when the control voltage Vc2 is equal to or higher than (reference voltage + Voff4), the bias supply to the Down-side variable amplifier 32 is stopped and the bias is supplied to the Up-side variable amplifier 31. The bias is switched so that

That is, the bias switch unit 3
6 is an offset voltage Vo as a reference voltage of the input.
From the position shifted by ff4, the singular point Up2 and the gain characteristic of the Down-side variable amplifier 32 in the gain characteristic of the Up-side variable amplifier 31 (see FIG. 9B) (FIG. 7).
(See (b))) and control is performed such that the path is switched at this point.

Next, the circuit operation of the gain control circuit according to the second embodiment having the above configuration will be described. First, when the control voltage Vc2 is smaller than the voltage of (reference voltage + Voff4), the bias switch 36
Since the bias is supplied only to the down side variable amplifying section 32, only the down side variable amplifying section 32 operates.

That is, when the control voltage Vc2 is Do
Until the singular point Down1 of the wn-side variable amplification unit 32 and the singular point Up2 of the Up-side variable amplification unit 31 are reached, Dow
Only the n-side variable amplifier 32 operates. As described above, the Down-side variable amplifying unit 32 performs an operation that emphasizes the IIP3 characteristics.

When the control voltage Vc2 is (reference voltage + V
When the voltage reaches the voltage of off4), the bias switch unit 36 stops supplying the bias to the Down-side variable amplifier 32 and supplies the bias to the Up-side variable amplifier 31. As a result, the operation of the down-side variable amplifier 32 stops, and the up-side variable amplifier 31 starts to move.

When the control voltage Vc2 is higher than the voltage of (reference voltage + Voff4), only the Up-side variable amplifier 31 operates. That is, the control voltage Vc2 is changed to the singular point Do of the down-side variable amplifier 32.
When wn1 and the singular point Up2 of the Up-side variable amplifying section 31 are exceeded, only the Up-side variable amplifying section 31 operates. This U
As described above, the p-side variable amplifying unit 31 performs an operation with emphasis on the NF characteristic.

As described above, the Up-side variable amplifying section 31 in which the variable gain amplifiers are cascaded in multiple stages and the Down-side variable amplifying section 32 in which the gain variable amplifiers are similarly connected in multiple stages are provided in parallel. , The singular point Up2 of the Up-side variable amplifying unit 31 and the singular point Down1 of the Down-side variable amplifying unit 32 are overlapped, and the path through which the signal passes (the path of the Up-side variable amplifying unit 31 / the By switching the path, a gain characteristic excellent in the linearity of the gain curve can be obtained as shown in FIG.

Moreover, since the setting of the Up side variable amplifying section 31 has a low NF characteristic and the setting of the Down side variable amplifying section 32 has a high IIP3 characteristic, the gain control circuit as a whole has a gain characteristic. Excellent linearity, low current consumption, low NF characteristics at high gain, and high IIP3 at low gain
A gain control circuit that satisfies both characteristics can be realized.

In each of the above embodiments, the bias switching switches 16 and 36 are switched between when the stability of the external gain control input voltage Vcont is poor and when the switching gain of the switching switches 16 and 36 is low. Is not performed instantaneously, and no signal is output. Therefore, it is possible to use a configuration having hysteresis for the purpose of increasing the switching gain.

In each of the above embodiments, the signal passes through two paths. In the second embodiment, the number of cascade-connected variable gain amplifiers is two. However, the present invention is not limited to these. , The number of paths through which signals pass and the number of cascade connection stages can be further increased.

The gain control circuits according to the first and second embodiments described above are used, for example, in the RF of a CDMA mobile phone.
It is used to configure the amplifier of each part in the front end part. FIG. 12 is a block diagram showing an example of the configuration of the RF front-end unit in the CDMA mobile phone.

In FIG. 12, a reception wave received by an antenna 41 passes through a band distribution filter 42 shared for transmission / reception, and passes through a low noise amplifier 43 to a mixer 4.
4 is supplied. In the mixer 44, the signal is mixed with the local oscillation frequency from the local oscillator 45 and converted into an intermediate frequency (IF). Then, after the signal level is made constant by the AGC amplifier 46, the signal is supplied to the baseband IC 47 at the subsequent stage.

On the other hand, on the transmitting side, the baseband I
The IF signal supplied from C47 is amplified by the AGC amplifier 48 and then supplied to the mixer 49 where the local oscillator 5
It is mixed with the local oscillation frequency from 0 and converted to an RF signal. The RF signal is transmitted from the antenna 41 via the power amplifier 51 and the band distribution filter 42.

The R of the CDMA type portable telephone device having the above configuration
In the F front end section, a low noise amplifier 43 for amplifying an RF signal of a receiving system, and an AGC
Amplifier 46 or AG for amplifying the IF signal of the transmission system
C amplifier 48 and power amplifier 51 for amplifying RF signal
The gain control circuits according to the first and second embodiments described above are used.

As described above, in the receiving system or the transmitting system of the CDMA type portable telephone device, the low noise amplifier 4 is used.
3, AGC amplifiers 46 and 48 or power amplifier 5
As the first, by using the gain control circuits according to the first and second embodiments of the present invention, the gain control circuit has a low NF characteristic at a high gain with a low current consumption and a high IIP at a low gain.
Since the three characteristics can be compatible, it is possible to contribute to a reduction in current consumption of the mobile phone device itself.

In the above application example, the case where the present invention is applied to a CDMA type portable telephone device has been described as an example. However, the present invention is not limited to this application example, and can be applied to all wireless communication devices. It is.

[0064]

As described above, according to the present invention,
A circuit part exhibiting a low NF characteristic at a high gain and a circuit part exhibiting a high IIP3 characteristic at a low gain are connected in parallel between an input terminal and an output terminal, and the characteristics of the respective circuit parts are superimposed on each other. NF can be reduced at a high gain without inputting a large current value of a constant current source of a variable gain amplifier constituting each circuit section, and an input at a low gain can be achieved. Since the dynamic range can be increased, the low NF characteristic at the time of high gain and the high IIP3 characteristic at the time of low gain can both be achieved without increasing current consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a gain control circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating gain characteristics of the gain control circuit according to the first embodiment.

FIG. 3 is a diagram illustrating a temperature characteristic of a gain characteristic of the gain control circuit according to the first embodiment.

FIG. 4 is a block diagram showing a configuration of a gain control circuit according to the prior application.

FIG. 5 is a diagram showing gain characteristics of a gain control circuit according to the prior application.

FIG. 6 is a block diagram illustrating a configuration of a gain control circuit applied to a Down-side amplifier.

FIG. 7 is a diagram illustrating gain characteristics of a gain control circuit applied to a Down-side amplifier.

FIG. 8 is a block diagram illustrating a configuration of a gain control circuit applied to the Up-side amplifier.

FIG. 9 is a diagram illustrating gain characteristics of a gain control circuit applied to an Up-side amplifier.

FIG. 10 is a block diagram illustrating a configuration of a gain control circuit according to a second embodiment of the present invention.

FIG. 11 is a diagram illustrating gain characteristics of a gain control circuit according to a second embodiment.

FIG. 12 is a block diagram illustrating an example of a configuration of an RF front end unit in the CDMA mobile phone device.

FIG. 13 is a circuit diagram showing a circuit example of a general gain variable amplifier.

FIG. 14 is a diagram illustrating gain characteristics of a general variable gain amplifier.

[Explanation of symbols]

11, 21U, 22U ... Up-side amplifier (variable gain amplifier), 12, 21D, 22D ... Down-side amplifier (variable gain amplifier), 13, 23, 33 ... control voltage generators, 14, 15, 24, 24 ', 24-1, 24-2,
34, 35... Offset voltage generators, 16, 23, 36
... Bias switch unit, 31 ... Up-side variable amplifier, 32 ... Down-side variable amplifier

Continued on the front page F term (reference) 5J091 AA01 AA41 CA13 CA35 CA41 FA18 HA02 HA25 HA29 HA38 KA02 KA05 KA41 SA13 TA01 TA02 5J100 AA01 AA15 BA01 BC01 CA00 CA11 DA06 EA02 FA01 FA02

Claims (8)

[Claims] 1. A first device exhibiting a low noise figure characteristic at a high gain.
And a second circuit section exhibiting a high input intercept point characteristic at a low gain, and a gain varying means connected in parallel between an input terminal and an output terminal; and the first circuit section and the Gain control, comprising: an offset voltage generating means for generating an offset voltage for superimposing respective characteristics of the second circuit portion; and a switching means for switching a signal path of the gain variable means according to a gain. circuit. 2. The gain control device according to claim 1, wherein each of the circuit sections in the gain variable means has a variable gain range limited to a fixed range, and includes a plurality of stages of variable gain amplifiers connected in cascade. circuit. 3. The gain control circuit according to claim 2, wherein said switching means switches a signal path of said gain varying means at a singular point of a temperature characteristic of each circuit section in said gain varying means. . 4. The gain control circuit according to claim 3, wherein said offset voltage generation means generates an offset voltage corresponding to a singular point of a temperature characteristic of each circuit section in said gain variable means. 5. An amplifying means for amplifying an IF signal or an RF signal in a transmitting system or a receiving system, the amplifying means comprising: a first circuit unit exhibiting a low noise figure characteristic at a high gain; A gain varying means in which a second circuit part exhibiting an input intercept point characteristic is connected in parallel between an input terminal and an output terminal; and a characteristic of each of the first circuit part and the second circuit part. A wireless communication apparatus comprising: a gain control circuit having offset voltage generating means for generating an offset voltage for superimposition and switching means for switching a signal path of the gain varying means according to a gain. 6. The wireless communication system according to claim 5, wherein each of the circuit sections in the gain variable means has a variable gain range limited to a fixed range, and comprises a plurality of stages of variable gain amplifiers connected in cascade with each other. apparatus. 7. The wireless communication apparatus according to claim 6, wherein the switching unit switches a signal path of the gain varying unit at a singular point of a temperature characteristic of each circuit unit in the gain varying unit. . 8. The wireless communication apparatus according to claim 7, wherein said offset voltage generating means generates an offset voltage corresponding to a singular point of a temperature characteristic of each circuit section in said gain varying means.