KR100470718B1 - Dc offset canceller - Google Patents

Abstract

The present invention relates to a DC offset removing device for efficiently removing a DC offset generated on a differential signal path. The low frequency signal detector of the DC offset remover is a low pass filter and detects the low frequency signals present at the first and second output terminals of the signal processor for processing signals input to the first and second input terminals. The current controller detects a feedback current corresponding to the low frequency signal detected by the low frequency signal detector, and returns the detected feedback current to the first and second output terminals. Therefore, the DC offset is removed as the first and second DC bias currents of the first and second output terminals of the signal processor are adjusted by the feedback current.

Description

DC offset elimination device {DC OFFSET CANCELLER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for removing a DC offset, and more particularly, to a DC offset removing apparatus for efficiently removing a DC offset generated on a differential signal path.

The most commonly used superheterodyne receiver currently mixes the received RF signal f1 with the local oscillation signal f2 generated by the local oscillator and filters the mixed signal by means of a bandpass filter to Frequency conversion to frequency (IF) signal. As such, superheterodyne receivers require bandpass filters, which are expensive intermediate frequency circuits, and thus are not ideal for small and low cost mobile communication systems such as cellular telephones, pagers, cordless telephones, and the like.

The direct conversion receiver is a transceiver developed to solve the problems of the above superheterodyne receiver. The direct conversion receiver frequency converts the received RF signal into a direct baseband signal by mixing the received RF signal with a local oscillation signal of the same frequency as the signal and a mixer. That is, since the direct conversion receiver directly converts the received RF signal into an IF signal, without directly converting the received RF signal into a baseband signal, a filter, a mixer, an amplifier, and the like used to convert the intermediate frequency signal may be omitted. In addition, since the direct conversion receiver uses only a low pass filter, it is easy to integrate on one chip.

In the direct conversion receiver having the above characteristics, a DC offset occurs because the frequency of the received RF signal and the local oscillation signal are the same. For example, when the local oscillation signal leaks to the input terminal of the received RF signal, multiplication of the local oscillation signals occurs and a DC offset voltage is generated.

In a high-speed wireless communication system, a signal received from an antenna is demodulated through an RF (radio frequency) terminal and an IF (infrared frequency) terminal, and then a signal is restored. Each stage processing the signal received from the antenna performs a frequency down function and a signal amplitude amplification function to obtain a desired signal. RF and IF stages use many analog devices, including mixers and amplifiers. These devices are used to meet a certain standard, but the standard is limited. Degradation of the input signal occurs due to the incompleteness of the insulation and orthogonality between these elements. One of the biggest deterioration factors is the DC power offset. The DC offset is caused by self-mixing of a drift signal in an analog circuit of a high speed wireless communication system in a quadrature converter, and is a leakage signal generated through each device.

As described above, in order to eliminate the DC offset generated in the direct conversion receiver and the electronic circuit system operated in the differential mode, the transmission of the DC signal is conventionally performed by inserting an analog element capacitor in series on the signal transmission path. Blocked.

However, the conventional method of removing a DC offset using a capacitor has a problem of filtering not only a DC component but also a desired signal near the DC due to the device characteristics of the capacitor.

In addition, the capacitor located in series on the signal transmission path is operated by a high pass filter (HPF) that cuts a low frequency signal, that is, a DC component signal, so that the cutoff frequency of the HPF when it is present in the low frequency of the signal to be transmitted Must be low enough, so a very large capacitor is needed.

Therefore, a DC offset device using a capacitor is also difficult to implement on one chip.

Accordingly, an object of the present invention is to provide a direct current offset removing device for performing a direct current offset.

One feature for achieving the above object is a DC offset removing device for removing the DC offset generated in the first and second output terminal of the signal processing unit for processing and outputting the signal input through the first and second input terminal A low frequency signal detection unit for detecting low frequency signals present in the first output terminal and the second output terminal; And a current adjuster detecting a feedback current corresponding to the low frequency signal detected by the low frequency signal detector and returning the detected feedback current to the first output terminal and the second output terminal.

The low frequency signal detector may include: a first resistor and a second resistor connected to the first output terminal and the second output terminal, respectively; And a first capacitor and a second capacitor connected in series with the first resistor and the second resistor, respectively. In this case, the first resistor and the second resistor may be composed of a first variable resistor and a second variable resistor whose resistance is adjusted according to a predetermined control signal.

The current adjusting unit may further include: a first transistor and a second transistor configured to receive a first low frequency signal of a first output terminal and a second low frequency signal of a second output terminal from a low frequency signal detector; A first load and a second load connected to collectors of the first transistor and the second transistor, respectively; A constant current source commonly connected to the emitters of the first transistor and the second transistor; And a current feedback unit for feedbacking the first and second currents of the first load and the second load to the first output terminal and the second output terminal, respectively. In this case, the current controller is an OTA of the feedback current according to the voltage difference between the low frequency signal of the first output terminal and the low frequency signal detected by the second output terminal.

The DC offset removing device according to the present invention further includes first and second current buffers having an input terminal connected to an output terminal of the current control unit and an output terminal connected to the first and second output terminals of the signal processing unit, respectively.

Hereinafter, a DC offset removing apparatus and method according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a DC offset removing apparatus according to a first embodiment of the present invention.

Referring to FIG. 1, a DC offset removing apparatus according to a first embodiment of the present invention detects a DC offset voltage of a main amplifier 100 and a main amplifier 100 to amplify a predetermined signal on a signal path. The low frequency signal detecting unit 110 and the low frequency signal detecting unit 100 includes a current adjusting unit 120 that detects a feedback current according to the DC offset voltage detected by the main amplifier 100 and feeds it back.

Here, the main amplifier 100 is a differential amplifier used for a direct conversion transceiver and the like, and includes a first transistor T1 and a base having a base connected to the first input terminal _Vi1 and the second input terminal _Vi2 , respectively. The first load 102 and the second load 104 and the first and second transistors T1 and T2 connected to the collectors of the second transistor T2, the first and second transistors T1 and T2, respectively. And a first constant current source 106 commonly connected to an emitter. In this case, it is obvious that the first and second transistors T1 and T2 may be formed of MOSFETs.

In addition, the low frequency signal detector 110 is a low pass filter including a resistor and a capacitor, and includes first and second resistors connected to the first output terminal V _o1 and the second output terminal V _o2 of the main amplifier 100. 112, a first capacitor C1 connected in series to the first resistor 112, and a second capacitor C2 connected in parallel to the second resistor 114. In this case, the first resistor 112 and the second resistor 114 may be configured not only by the passive resistance element but also by an active resistance element such as a MOSFET.

The current controller 120 is an operation transconductance amplifier (OTA) that outputs a current according to a difference in an input voltage input to a base, and is applied to the first resistor 112 and the second resistor 114 of the low frequency signal detector 110. The third and fourth loads 124 and 124 connected to the collectors of the third and fourth transistors T3 and T4, and the third and fourth transistors T3 and T4, respectively, to which the bases are connected, respectively. Include. Here, the first and second outputs I _o1 and I _o2 of the current controller 120 are connected to the first and second output terminals V _{o1 and} V _o2 of the main amplifier 110. At this time, it is apparent that the third and fourth transistors T3 and T4 of the current controller 120 may be configured by MOSFETs.

The operation of the DC offset removing device according to the first embodiment of the present invention configured as described above is as follows.

The main amplifier 100 has a first and a second input common mode and a different voltage to the first and second input terminals (V _i1, V _i2), which is operated as a common voltage is applied to the (V _i1, V _i2) applied Has a differential mode that operates as

When the main amplifier 100 is operated in the common mode or the differential mode as described above, the small signal of the differential mode and the DC signal of the common mode are present in the first and second output terminals V _{o1 and} V _o2 . In this case, when the DC voltage v1 of the first output terminal V _o1 and the DC voltage v2 of the second output terminal V _o2 are different from each other, a DC offset is generated in the main amplifier 100.

The low frequency signal detector 110 detects a low frequency signal component, that is, a DC offset voltage at the first output terminal V _o1 and the second output terminal V _o2 of the main amplifier 100, and converts the detected DC offset voltage into a current controller. Output to 120.

The current controller 120 detects a feedback current Io according to the DC offset voltage input from the low frequency signal detector 110, and returns the detected feedback current Io to the main amplifier 100.

At this time, the main amplifier 100 receives the first and second DC bias currents I ₁ and I ₂ of the first and second loads 102 and 104 by the feedback current Io fed back from the current adjusting unit 120. The regulated DC offset voltage is removed.

The above DC offset voltage detection operation will be described in more detail.

A case in which a DC offset occurs because the first DC voltage v1 of the first output terminal V _o1 of the main amplifier 100 is greater than the second DC voltage v2 of the second output terminal V _o2 will be described.

First, the DC offset voltage removing principle of the present invention is that when the first DC voltage v1 is greater than the second DC voltage v2, the first DC bias current I ₁ flowing through the first load 102 becomes the second. Since it is smaller than the second DC bias current I ₂ flowing in the load 104, the DC offset voltage is adjusted by adjusting the first DC bias current I ₁ to be large and adjusting the second DC bias current I ₂ to be low. This is the principle that is removed.

Since the low frequency signal detection unit 110 is a low pass filter including the first and second resistors 112 and 114 and the first and second capacitors C1 and C2, the first output terminal V _{o1 of} the main amplifier 100 may be used. The DC voltage v1 is detected, and the second DC voltage v2 is detected at the second output terminal V _o2 and output to the current controller 120. Here, the difference between the first DC voltage v1 and the second DC voltage v2 is a DC offset voltage.

The current controller 120 receives the first DC voltage v1 and the second DC voltage v2 detected by the low frequency signal detector 110 as gate voltages of the third and fourth transistors T3 and T4. .

Here, when the first and second DC voltages v1 and v2 are input to the gates of the third transistor T3 and the fourth transistor T4, the current adjuster 120 receives the third and fourth transistors T3,. T4) is operated to detect the feedback current according to the DC offset voltage which is the difference (v1-v2) of the first and second DC voltages v1 and v2.

That is, the feedback current Io detected at the first output terminal I _o1 and the second output terminal I _O2 of the current adjuster 120 is the difference between the first and second DC voltages v1 and v2 (v1-1). v2) is calculated by multiplying transconductance (gm). At this time, the transconductance is a fixed value set arbitrarily. Also, the transconductance is an adjustable value to adjust the accuracy of the offset rejection.

In addition, the feedback current Io detected at the first output terminal I _o1 and the second output terminal I _o2 of the current adjusting unit 120 has a different current direction, but is different from the second output terminal I _o2 . The feedback current flows toward the main amplifier 100, and the feedback current at the first output terminal I _o1 flows toward the current adjuster 120.

Therefore, the value of the first DC bias current I ₁ of the main amplifier 100 is increased by adding a feedback current, and the value of the second DC bias current I ₂ is smaller by the feedback current.

As such, the first DC voltage decreases as the first DC bias current increases due to the feedback current, and the second DC voltage increases as the second DC bias current decreases, so that the first DC voltage and the second DC voltage are the same. As a result, the DC offset voltage is eliminated.

As described above, when the low frequency signal detected by the low frequency signal detector 110, that is, the DC voltage is detected, the current controller 120 calculates a current according to the detected DC voltage and feeds it back to the main amplifier 100. The low frequency signal detector 110 and the current controller 120 serve as a high pass filter that blocks low frequency signals and passes high frequency signals.

As described above, the operation principle of the DC voltage removing device according to the first embodiment of the present invention including the low frequency signal detection unit 110 and the current control unit 120 serving as a high pass filter will be described.

2 is a conceptual diagram of a DC offset removing apparatus according to a first embodiment of the present invention.

As shown in FIG. 2, the first amplifier 200 on the signal path is the main amplifier 100 of FIG. 1, and the second amplifier 210 on the feedback loop includes a low frequency signal detector 110 and a current controller. A second amplifier 210 having an operating characteristic of 120, i.e., feedback occurs only in a low frequency signal. At this time, the conceptual diagram of the DC offset eliminator according to the first embodiment has a single-ended structure having one input and one output, but is applicable to a differential structure having two inputs and two outputs. Can be.

In Figure 2, the voltage gain is equal to Equation 1.

In addition, to simplify the model of the DC offset removing device according to the first embodiment of the present invention, and for the conceptual description, the frequency characteristics of the first and second amplifiers 200 and 210 are represented by a single pole as shown in Equations 2 and 3 Defined by the transfer function model.

here, Is the operating bandwidth of the first amplifier 200, Is the operating bandwidth of the second amplifier 210.

That is, the DC offset removing apparatus according to the first embodiment has the frequency characteristics as shown in FIG.

As shown in FIG. 3, the cutoff frequency of the second amplifier 210, that is, the pole ( ) Constitutes a zero point in the signal path and should be set to a sufficiently low value since there is no change in the value of the open-loop or close-loop.

In addition, the cutoff frequency of the second amplifier 210 ( Since the signal attenuation occurs as much as (A ₂ +1) in components below), the gain A ₂ of the second amplifier 210 must be set to a large value in order to sufficiently remove the input DC component.

At this time, the gain A ₂ of the second amplifier 210 set to a large value is (A ₂ +1) in the frequency characteristic on the closed loop. Poles are generated, and normal processing is performed only on signal components above the poles. Therefore, when the gain A ₂ of the second amplifier 210 is set to a value that is too large, a wide transition region is generated, and the effective attenuation bandwidth increases, so that the attenuation ratio A ₂ is increased. +1) and attenuation bandwidth ( ) Should be chosen accordingly.

4 is a block diagram illustrating a DC offset removing apparatus according to a second embodiment of the present invention.

Referring to FIG. 4, the DC offset removing apparatus according to the second exemplary embodiment of the present invention may include a first variable resistor connected to the first output terminal V _o1 and the second output terminal V _o2 of the main amplifier 100, respectively. A low frequency detector including a first capacitor C1 and a second capacitor C2 connected in series to the 402 and the second variable resistor 404, the first variable resistor 402, and the second variable resistor 404, respectively. And a control signal generator 410 for outputting a control signal for adjusting the resistance values of the first and second variable resistors 402 and 404 of the low frequency detector 400, and the rest of the configuration of the present invention. Since it is the same as the first embodiment, a description of the configuration thereof is omitted.

Here, the first and second variable resistors 402 and 404 may be configured as MOS field transistors whose gate voltage is adjusted according to the control signal of the control signal generator 410.

The operation of the DC offset removing apparatus according to the second embodiment of the present invention configured as described above will be described below.

First, the same components as in the first embodiment will be described with the same reference numerals.

A case in which a DC offset occurs because the first DC voltage v1 of the first output terminal V _o1 of the main amplifier 100 is greater than the second DC voltage v2 of the second output terminal V _o2 will be described.

Since the low frequency signal detector 400 is a low pass filter including the first and second variable resistors 402 and 404 and the first and second capacitors C1 and C2, the first output terminal V _o1 of the main amplifier 100 is used. And a low frequency signal, that is, a DC offset voltage at the second output terminal V _o2 , and outputs the detected DC offset voltage to the current controller 120.

Here, the low frequency signal detector 400 adjusts the resistance of the first variable resistor 402 and the second variable resistor 404 according to a control signal input from the control signal generator 410. In this case, as the resistance values of the first variable resistor 402 and the second variable resistor 404 are adjusted, the low frequency signal detector 400 has a frequency characteristic having a plurality of poles, that is, a plurality of cutoff frequencies.

When the first DC voltage v1 and the second DC voltage v2 detected by the low frequency signal detector 400 are input, the current adjuster 120 detects a feedback current according to the input signal, and detects the detected padback current. Feedback to the main amplifier 100.

Here, the adjustment of the first and second DC bias currents I ₁ and I ₂ of the main amplifier 100 according to the feedback current detected by the current adjusting unit 120 and the DC offset voltage removing operation according thereto are _{shown in} FIG. Since it is the same as the first embodiment of the present invention, a detailed description thereof will be omitted.

As described above, the resistance values of the first and second variable resistors 402 and 404 are adjusted by the control signal generated by the control signal generator 410 so that the low frequency signal detector 400 has a frequency characteristic having a plurality of cutoff frequencies. Since the DC offset removing apparatus according to the second embodiment of the present invention serves as a band pass filter.

Here, the DC offset removing apparatus according to the second embodiment of the present invention has a lower cutoff frequency and a higher cutoff frequency, and as the lower cutoff frequency is lowered, the DC offset removing efficiency increases. In this case, when the resistance values of the first and second variable resistors 402 and 404 of the low frequency signal detector 400 are increased, the lower cutoff frequency is lowered.

However, in the second embodiment of the present invention, if the lower cutoff frequency is made too low to increase the DC offset removal efficiency, the transition period becomes too wide, so that the resistance values of the first and second variable resistors 402 and 404 are appropriately adjusted. Therefore, the attenuation efficiency and the transition interval must be properly traded.

5 is a diagram illustrating a DC offset removing device according to a third embodiment of the present invention.

Referring to FIG. 5, the DC offset removing apparatus according to the third exemplary embodiment of the present invention includes a current adjuster 120 and a main amplifier detecting a feedback current for removing the DC offset voltage generated by the main amplifier 100. A buffer unit 500 for isolating 100 is included, and other configurations are the same as those of the second embodiment of the present invention, and thus detailed configuration description thereof will be omitted.

Here, the buffer unit 500 has an input terminal connected to the first output terminal I _o1 and the second output terminal I _o2 of the current controller 120, respectively, and the first output terminal V _o1 of the main amplifier 100. And a first current buffer 502 and a second current buffer 504 each having an output terminal connected to the second output terminal V _o2 . In this case, the first current buffer 502 and the second current buffer 504 of the buffer unit 500 have a unidirectional characteristic in which signal transmission is performed only on one side.

The operation of the DC offset removing device according to the third embodiment of the present invention configured as described above is as follows.

First, operations of the low frequency signal detector 400, the current controller 120, and the control signal generator 410 for removing the DC offset voltage generated by the main amplifier 100 are the same as in the second embodiment of the present invention. Therefore, detailed description thereof will be omitted.

Then, in the ideal case, the current regulator 120 has a very large output impedance (infinity: The main amplifier 100 has little influence on the third load 122 and the fourth load 124 of the current controller 120.

However, in practice, the gain of the main amplifier 100 is lowered by the third and fourth loads 122 and 124 of the current controller 120.

For example, a DC loading in which current flows from the main amplifier 100 toward the current control unit 120 is generated by the third load 122 and the fourth load 124, and the main amplifier 100 is generated. AC loading of the form in which the first and second loads 102 and 104 and the third and fourth loads 122 and 124 of the current controller 120 are connected in parallel is performed.

The first current buffer 502 and the second current buffer 504 of the buffer unit 500 have a unidirectional characteristic in which a signal transmission direction is one, thereby insulating the main amplifier 100 and the current control unit 120. This prevents the above DC loading phenomenon and the AC loading phenomenon.

As described above, the offset cancellation apparatus according to the present invention is configured as a low-pass filter of the low frequency signal detection unit of the first order, it is obvious that it can be configured as a low-pass filter of the second order or more to increase the DC offset removal efficiency. .

As described above, the DC offset removing apparatus according to the present invention detects a DC offset voltage by a low pass filter that passes only a signal of a DC component, which is a low frequency signal, and detects a feedback current with respect to the detected DC offset voltage to maintain the main amplifier. Feedback to remove the DC offset voltage generated by adjusting the DC bias current of the main amplifier.

Therefore, the present invention has the effect that the detection of the DC offset voltage and the current feedback are made at the same node, so that the configuration is independent of the main device on the differential mode signal path and can be used at any position without changing the main device.

In addition, since the present invention detects a low frequency, that is, a DC offset voltage by the low pass filter, and removes the detected DC offset voltage, the present invention can also remove the DC offset even in a frequency division duplex (FDD) transceiver. have.

In addition, the present invention implements the operation of the high pass filter by the current control unit of the low pass filter and OTA, it can be implemented by a small capacitor, there is an effect that can be implemented by the IC.

Although the present invention has been described with reference to the embodiments, those skilled in the art may variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. You will understand.

1 is a circuit diagram of a DC offset removing device according to a first embodiment of the present invention.

2 is a conceptual diagram illustrating the operation principle of the present invention.

3 is a diagram illustrating the frequency characteristics of FIG. 2.

4 is a circuit diagram of a DC offset removing apparatus according to a second embodiment of the present invention.

5 is a circuit diagram of a DC offset removing apparatus according to a third embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100: main amplifier 110: low frequency signal detection unit

120: current regulator

Claims (11)

In the DC offset removing device for removing the DC offset generated in the first and second output terminal of the signal processing unit for processing and output the signal input through the first and second input terminal, First and second resistors connected in series to the first and second output terminals, respectively, for detecting low frequency signals present in the first and second output terminals, respectively, in series with the first and second resistors. A low frequency signal detector comprising a first capacitor and a second capacitor; And And a current adjuster configured of an OAT for feeding back a feedback current according to the voltage difference between the low frequency signals of the first and second output terminals detected by the low frequency signal detector to the first and second output terminals. DC offset eliminator. delete The apparatus of claim 1, wherein the first resistor and the second resistor of the low frequency signal detector are passive resistors or active resistors. 4. The DC offset removing device of claim 3, wherein the active resistance element is a MOS field effect transistor (MOSFET). delete The display device of claim 1, wherein the current controller comprises: a first transistor and a second transistor configured to receive a first low frequency signal of the first output terminal and a second low frequency signal of a second output terminal from the low frequency signal detector; A first load and a second load connected to the collectors of the first transistor and the second transistor, respectively; A constant current source commonly connected to the emitters of the first and second transistors; And And a current feedback unit for returning first and second currents of the first and second loads to the first output terminal and the second output terminal, respectively. The apparatus of claim 6, wherein the first transistor and the second transistor are Morse field effect transistors. The apparatus of claim 1, further comprising a buffer unit for blocking a signal flow from the signal processor to the current controller. The method of claim 8, wherein the buffer unit comprises an input terminal is connected to the output terminal of the current control unit, the output terminal is connected to the first and second output terminal of the signal processor, characterized in that it comprises a first and second current buffer, respectively DC offset eliminator. The method of claim 1, And the first and second resistors of the low frequency signal detector are configured of a variable resistor whose resistance is adjusted according to a predetermined control signal. The method of claim 10, And the first resistor and the second resistor are MOS field effect transistors whose gate voltage is adjusted according to the control signal.