JP2001215483A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JP2001215483A JP2001215483A JP2000023984A JP2000023984A JP2001215483A JP 2001215483 A JP2001215483 A JP 2001215483A JP 2000023984 A JP2000023984 A JP 2000023984A JP 2000023984 A JP2000023984 A JP 2000023984A JP 2001215483 A JP2001215483 A JP 2001215483A
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- glass substrate
- display device
- crystal display
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は液晶表示装置に関す
るものである。[0001] The present invention relates to a liquid crystal display device.
【０００２】[0002]
【従来の技術】液晶表示装置は一般に、板面を対向させ
間に液晶層を介在させて配置された第１および第２のガ
ラス基板を含み、第１のガラス基板の液晶層側の表面に
は、それぞれ透明電極を含む画素が多数密に配列され、
画素の配列領域の外側に画素の駆動回路が形成されてい
る。そして、画素および駆動回路の上に層間絶縁膜が形
成され、層間絶縁膜の上にはパネル上面を平坦化するた
めの有機平坦化膜が形成されている。また、第２のガラ
ス基板の液晶層側の表面には対向電極が形成されてい
る。2. Description of the Related Art In general, a liquid crystal display device includes first and second glass substrates arranged with a liquid crystal layer interposed therebetween with their plate surfaces facing each other, and a liquid crystal layer side surface of the first glass substrate is provided on the liquid crystal layer side. Is densely arranged with a large number of pixels each including a transparent electrode,
A pixel driving circuit is formed outside the pixel arrangement region. Then, an interlayer insulating film is formed on the pixels and the drive circuit, and an organic planarizing film for flattening the upper surface of the panel is formed on the interlayer insulating film. A counter electrode is formed on the surface of the second glass substrate on the liquid crystal layer side.
【０００３】図８はこのような従来の液晶表示装置を構
成する一方のガラス基板の一例を示す部分拡大断面側面
図、図９は平面図である。なお、図８は図９におけるＡ
Ａ’線に沿った断面を示している。図９に示したよう
に、平面視矩形の第１のガラス基板１２上の中央部に、
それぞれ透明電極を含む多数の画素１４がマトリクス状
に配列されている。画素の配列領域１６の外側には、図
８に示したように、薄膜トランジスタ１８を含む、画素
の駆動回路７が形成されている。そして、画素の配列領
域１６、およびその外側の領域の上には全体に図８に示
したように層間絶縁膜２０が形成され、さらにその上全
体に有機平坦化膜２２が形成されている。FIG. 8 is a partially enlarged side view showing an example of one glass substrate constituting such a conventional liquid crystal display device, and FIG. 9 is a plan view. FIG. 8 shows A in FIG.
The cross section along the line A 'is shown. As shown in FIG. 9, at the center of the first glass substrate 12 having a rectangular shape in plan view,
Many pixels 14 each including a transparent electrode are arranged in a matrix. As shown in FIG. 8, a pixel drive circuit 7 including a thin film transistor 18 is formed outside the pixel array region 16. Then, an interlayer insulating film 20 is formed entirely on the pixel arrangement region 16 and the region outside thereof, as shown in FIG. 8, and an organic flattening film 22 is further formed entirely thereon.
【０００４】[0004]
【発明が解決しようとする課題】しかし、このような従
来の液晶表示装置では、第１のガラス基板１２上には上
述のように全体に層間絶縁膜２０が形成され、その熱膨
張率が第１のガラス基板１２と異なるなどの理由で、常
温では図８に示したような上に凸の反りが生じるという
問題がある。このような反りが生じると第１のガラス基
板１２と上記第２のガラス基板とを張り合わせる際にガ
ラス基板間の隙間が均一とならず、液晶表示装置として
必要な性能が得られなくなることから製造歩留まりが低
下する。However, in such a conventional liquid crystal display device, the interlayer insulating film 20 is entirely formed on the first glass substrate 12 as described above, and the coefficient of thermal expansion of the interlayer insulating film 20 is reduced to the second. At room temperature, there is a problem that upwardly convex warpage as shown in FIG. 8 occurs due to a difference from the glass substrate 12 of FIG. When such a warp occurs, the gap between the glass substrates is not uniform when the first glass substrate 12 and the second glass substrate are bonded to each other, and the performance required for the liquid crystal display device cannot be obtained. Manufacturing yield decreases.
【０００５】ところで、有機平坦化膜２２は、層間絶縁
膜２０とは反対の方向に第１のガラス基板１２を反らせ
るように作用する。したがって、有機平坦化膜２２を従
来より厚く形成すれば、その作用が高まり、層間絶縁膜
２０による反りを打ち消すことができる。しかし、その
場合には、有機平坦化膜２２における光の減衰が大きく
なるため、液晶表示装置の輝度が全体に低下し、性能が
劣化する。また、有機平坦化膜２２を厚くすると加工性
が悪くなり、コスト増につながる。本発明はこのような
問題を解決するためになされたもので、その目的は、輝
度の低下や加工性の悪化を招くことなくガラス基板の反
りを緩和して製造歩留まりの向上を実現する液晶表示装
置を提供することにある。Incidentally, the organic planarizing film 22 acts so as to warp the first glass substrate 12 in a direction opposite to the direction of the interlayer insulating film 20. Therefore, if the organic flattening film 22 is formed thicker than before, the effect is enhanced, and the warpage due to the interlayer insulating film 20 can be canceled. However, in this case, since the attenuation of light in the organic flattening film 22 is large, the brightness of the liquid crystal display device is reduced as a whole, and the performance is deteriorated. Further, when the organic flattening film 22 is made thick, the workability is deteriorated, which leads to an increase in cost. The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a liquid crystal display capable of reducing a warpage of a glass substrate and improving a manufacturing yield without causing a decrease in luminance and a deterioration in workability. It is to provide a device.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するため、板面を対向させ間に液晶層を介在させて配
置された第１および第２のガラス基板を含み、前記第１
のガラス基板の前記液晶層側の表面には、それぞれ透明
電極を含む画素が多数密に配列され、前記画素の配列領
域の外側に前記画素の駆動回路が形成され、前記画素の
配列領域および前記駆動回路の上に層間絶縁膜が形成さ
れ、前記層間絶縁膜の上に有機平坦化膜が形成され、前
記第２のガラス基板の前記液晶層側の表面には対向電極
が形成されている液晶表示装置であって、前記第１のガ
ラス基板上の前記層間絶縁膜には、前記画素および前記
駆動回路のいずれか一方または両方の周辺において凹
部、または周辺部より低い段部が形成され、前記凹部お
よび前記段部の箇所には前記凹部および前記段部の周辺
部より厚い前記有機平坦化膜が形成されていることを特
徴とする。In order to achieve the above object, the present invention includes first and second glass substrates which are arranged with a liquid crystal layer interposed therebetween with their plate surfaces facing each other.
On the surface of the glass substrate on the side of the liquid crystal layer, a large number of pixels each including a transparent electrode are densely arranged, and a driving circuit for the pixels is formed outside the arrangement region of the pixels. A liquid crystal in which an interlayer insulating film is formed on the driving circuit, an organic planarizing film is formed on the interlayer insulating film, and a counter electrode is formed on a surface of the second glass substrate on the side of the liquid crystal layer. In the display device, the interlayer insulating film on the first glass substrate is formed with a concave portion or a step portion lower than a peripheral portion around one or both of the pixel and the drive circuit, The organic planarizing film, which is thicker than the periphery of the concave portion and the step portion, is formed at the concave portion and the step portion.
【０００７】本発明の液晶表示装置では、第１のガラス
基板の層間絶縁膜には、画素および駆動回路のいずれか
一方または両方の周辺において凹部、または周辺部より
低い段部が形成されている。そして、凹部および段部の
箇所には凹部および段部の周辺部より厚い有機平坦化膜
が形成されている。したがって、凹部および段部の箇所
では、層間絶縁膜の膜厚が薄いか、または層間絶縁膜が
形成されていないため層間絶縁膜による第１のガラス基
板の反りは少ないか、または発生しない。一方、凹部お
よび段部の箇所では有機平坦化膜の膜厚が厚いため、層
間絶縁膜による第１のガラス基板の反りを打ち消す、有
機平坦化膜による第１のガラス基板の反りが大きくな
る。その結果、有機平坦化膜上面の第１のガラス基板か
らの高さが従来と同じであっても、全体として層間絶縁
膜による第１のガラス基板の反りは、有機平坦化膜によ
る第１のガラス基板の反りにより従来より大きく打ち消
され、第１のガラス基板の反りが緩和される。In the liquid crystal display device of the present invention, a concave portion or a step portion lower than the peripheral portion is formed around one or both of the pixel and the drive circuit in the interlayer insulating film of the first glass substrate. . An organic planarizing film thicker than the periphery of the concave portion and the step is formed at the position of the concave portion and the step. Therefore, in the concave portion and the step portion, the thickness of the interlayer insulating film is thin or the first glass substrate is not warped due to the interlayer insulating film because the interlayer insulating film is not formed. On the other hand, since the thickness of the organic flattening film is large in the concave portion and the stepped portion, the first glass substrate is warped by the organic flattening film to cancel the warpage of the first glass substrate due to the interlayer insulating film. As a result, even if the height of the upper surface of the organic planarization film from the first glass substrate is the same as that of the related art, the warpage of the first glass substrate due to the interlayer insulating film as a whole is caused by the first planarization film due to the organic planarization film. The warpage of the glass substrate cancels out more than the conventional case, and the warpage of the first glass substrate is reduced.
【０００８】[0008]
【発明の実施の形態】次に本発明の実施の形態例につい
て図面を参照して説明する。図１は本発明による液晶表
示装置の一例を示す部分断面側面図、図２は同平面図で
ある。図中、図８、図９と同一の要素には同一の符号が
付されている。なお、図１は図２におけるＡＡ’線に沿
った断面を示している。本実施の形態例の液晶表示装置
は、板面を対向させ間に液晶層を介在させて配置された
第１のガラス基板１２と、液晶層側の表面に不図示の対
向電極が形成された不図示の第２のガラス基板とを含ん
で構成されている。第１のガラス基板１２の液晶層側の
表面には、それぞれ不図示の透明電極を含む画素１４が
多数密に配列され、画素の配列領域１６の外側に画素１
４の駆動回路７が形成されている。また、画素の配列領
域１６および駆動回路７の上には層間絶縁膜２０が形成
され、層間絶縁膜２０の上に有機平坦化膜２２が形成さ
れている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a partial sectional side view showing an example of the liquid crystal display device according to the present invention, and FIG. 2 is a plan view thereof. In the figure, the same elements as those in FIGS. 8 and 9 are denoted by the same reference numerals. FIG. 1 shows a cross section along the line AA ′ in FIG. In the liquid crystal display device of the present embodiment, a first glass substrate 12 disposed with a liquid crystal layer interposed therebetween with the plate surfaces facing each other, and a counter electrode (not shown) formed on the surface on the liquid crystal layer side. And a second glass substrate (not shown). On the surface of the first glass substrate 12 on the liquid crystal layer side, a large number of pixels 14 each including a transparent electrode (not shown) are densely arranged.
4 drive circuits 7 are formed. Further, an interlayer insulating film 20 is formed on the pixel arrangement region 16 and the drive circuit 7, and an organic planarizing film 22 is formed on the interlayer insulating film 20.
【０００９】駆動回路７は薄膜トランジスタ１８を含ん
で構成され、また、画素の配列領域１６には各画素１４
ごとに透明電極に接続された不図示の薄膜トランジスタ
が配設されている。そして、第１のガラス基板１２の層
間絶縁膜２０には、画素の配列領域１６および駆動回路
７を内側にして平面視矩形の枠状の溝４が形成されてい
る。本実施の形態例では溝４の深さは周辺の層間絶縁膜
２０の厚さに等しく、底部は第１のガラス基板１２の表
面となっている。この溝４内には有機平坦化膜２２の材
料が充填され、したがって溝４の箇所では有機平坦化膜
２２は周辺部より厚く形成されている。The driving circuit 7 includes a thin film transistor 18, and a pixel array region 16 includes
A thin-film transistor (not shown) connected to the transparent electrode is provided for each of them. The rectangular frame-shaped groove 4 is formed in the interlayer insulating film 20 of the first glass substrate 12 with the pixel array region 16 and the drive circuit 7 inside. In the present embodiment, the depth of the groove 4 is equal to the thickness of the peripheral interlayer insulating film 20, and the bottom is the surface of the first glass substrate 12. The groove 4 is filled with the material of the organic flattening film 22, and thus the organic flattening film 22 is formed thicker at the groove 4 than at the peripheral portion.
【００１０】このように構成された第１のガラス基板１
２では、溝４の箇所では層間絶縁膜２０が形成されてい
ないため層間絶縁膜２０による第１のガラス基板１２の
反りは発生しない。一方、溝４の箇所では有機平坦化膜
２２の膜厚が厚いため、層間絶縁膜２０による第１のガ
ラス基板１２の反りを打ち消す、有機平坦化膜２２によ
る第１のガラス基板１２の反りが大きくなる。[0010] The first glass substrate 1 thus configured
In 2, the first glass substrate 12 is not warped by the interlayer insulating film 20 because the interlayer insulating film 20 is not formed at the location of the groove 4. On the other hand, since the thickness of the organic flattening film 22 is large at the location of the groove 4, the warpage of the first glass substrate 12 due to the interlayer insulating film 20 is canceled out. growing.
【００１１】図３は有機平坦化膜２２の厚さとガラス基
板の反り量との関係を実測した結果を示すグラフであ
る。図中、横軸が有機平坦化膜２２の厚を示し、縦軸は
ガラス基板の反り量を示している。なお、このグラフ
は、縦横３ｃｍのガラス基板の全体に、層間絶縁膜２０
は形成せず、一定厚の有機平坦化膜２２のみを形成した
場合の全体の反り量を表している。グラフ中の黒丸が実
測結果を示している。FIG. 3 is a graph showing the relationship between the thickness of the organic planarizing film 22 and the amount of warpage of the glass substrate. In the figure, the horizontal axis indicates the thickness of the organic planarizing film 22, and the vertical axis indicates the amount of warpage of the glass substrate. Note that this graph shows that an interlayer insulating film 20
Indicates the entire amount of warpage when only the organic planarizing film 22 having a constant thickness is formed without being formed. The black circles in the graph indicate actual measurement results.
【００１２】このグラフから分かるように有機平坦化膜
２２を厚くするほど反り量は大きくなっており、本実施
の形態例では、溝４の箇所において有機平坦化膜２２が
厚いため、層間絶縁膜２０による反りが強く打ち消され
る。その結果、有機平坦化膜２２上面の第１のガラス基
板１２からの高さが従来と同じであっても、全体として
層間絶縁膜２０による第１のガラス基板１２の反りは、
有機平坦化膜２２による第１のガラス基板１２の反りに
より従来より大きく打ち消され、第１のガラス基板１２
の反りが緩和される。そのため、本実施の形態例では、
輝度の低下や加工性の悪化を招くことなくガラス基板の
反りを緩和することができ、第２のガラス基板を第１の
ガラス基板１２に重ねた際に両ガラス基板間の隙間が均
一となって、液晶表示装置製造時の歩留まりを向上させ
ることができる。As can be seen from this graph, the warpage increases as the thickness of the organic flattening film 22 increases. In the present embodiment, since the organic flattening film 22 is thicker at the groove 4, the interlayer insulating film is formed. 20 warpage is strongly negated. As a result, even though the height of the upper surface of the organic planarization film 22 from the first glass substrate 12 is the same as that of the related art, the warpage of the first glass substrate 12 due to the interlayer insulating film 20 as a whole is
The warpage of the first glass substrate 12 caused by the organic flattening film 22 is largely canceled by the conventional method, and the first glass substrate 12
Warpage is reduced. Therefore, in the present embodiment,
The warpage of the glass substrates can be reduced without causing a decrease in luminance or a deterioration in workability, and the gap between the two glass substrates becomes uniform when the second glass substrate is stacked on the first glass substrate 12. Thus, the yield at the time of manufacturing the liquid crystal display device can be improved.
【００１３】次に第２の実施の形態例について説明す
る。図４は本発明の第２の実施の形態例を示す部分断面
側面図、図５は同平面図である。図中、図１、図２と同
一の要素には同一の符号が付されている。なお、図４は
図５におけるＡＡ’線に沿った断面を示している。第２
の実施の形態例が上記実施の形態例と異なるのは、画素
の配列領域１６および駆動回路７の外側に、溝４に変え
て段部６が形成されている点である。すなわち、第２の
実施の形態例では、第１のガラス基板１２の層間絶縁膜
２０には、画素の配列領域１６および駆動回路７を内側
にして平面視矩形の枠状の段部６が形成されている。本
実施の形態例では段部６の深さは内側周辺部の層間絶縁
膜２０の厚さに等しく、底部は第１のガラス基板１２の
表面となっている。この段部６内には有機平坦化膜２２
の材料が充填され、したがって段部６の箇所では有機平
坦化膜２２は内側周辺部より厚く形成されている。第２
の実施の形態例では、有機平坦化膜２２が厚い領域を、
第１の実施の形態例の場合より広くできるので、層間絶
縁膜２０による第１のガラス基板１２の反りをいっそう
効果的に打ち消すことができる。Next, a second embodiment will be described. FIG. 4 is a partial cross-sectional side view showing a second embodiment of the present invention, and FIG. 5 is a plan view of the same. In the drawings, the same elements as those in FIGS. 1 and 2 are denoted by the same reference numerals. FIG. 4 shows a cross section along the line AA ′ in FIG. Second
This embodiment is different from the above-described embodiment in that a step portion 6 is formed instead of the groove 4 outside the pixel array region 16 and the drive circuit 7. That is, in the second embodiment, a rectangular frame-shaped stepped portion 6 is formed in the interlayer insulating film 20 of the first glass substrate 12 with the pixel array region 16 and the drive circuit 7 inside. Have been. In the present embodiment, the depth of the step 6 is equal to the thickness of the interlayer insulating film 20 in the inner peripheral portion, and the bottom is the surface of the first glass substrate 12. An organic planarizing film 22 is provided in the step 6.
Therefore, the organic flattening film 22 is formed thicker at the step portion 6 than at the inner peripheral portion. Second
In the embodiment, the region where the organic planarizing film 22 is thick is
Since the first glass substrate 12 can be wider than in the case of the first embodiment, the warpage of the first glass substrate 12 due to the interlayer insulating film 20 can be canceled more effectively.
【００１４】次に第３の実施の形態例について説明す
る。図６は本発明の第３の実施の形態例を示す部分断面
側面図、図７は同平面図である。図中、図１、図２と同
一の要素には同一の符号が付されている。なお、図６は
図７におけるＡＡ’線に沿った断面を示している。第３
の実施の形態例が上記実施の形態例と異なるのは、個々
の画素１４の周辺に凹部８が形成されている点である。
すなわち、第３の実施の形態例では、図６に示したよう
に、画素１４の周辺に、画素１４ごとに配置された薄膜
トランジスタ２の箇所を除いて、凹部８が形成されてい
る。本実施の形態例では凹部８の深さは周辺部の層間絶
縁膜２０の厚さに等しく、底部は第１のガラス基板１２
の表面となっている。この凹部８内には有機平坦化膜２
２の材料が充填され、したがって凹部８の箇所では有機
平坦化膜２２は周辺部より厚く形成されている。Next, a third embodiment will be described. FIG. 6 is a partial cross-sectional side view showing a third embodiment of the present invention, and FIG. 7 is a plan view of the same. In the drawings, the same elements as those in FIGS. 1 and 2 are denoted by the same reference numerals. FIG. 6 shows a cross section along the line AA ′ in FIG. Third
This embodiment is different from the above embodiment in that a concave portion 8 is formed around each pixel 14.
That is, in the third embodiment, as shown in FIG. 6, the recess 8 is formed around the pixel 14 except for the portion of the thin film transistor 2 arranged for each pixel 14. In the present embodiment, the depth of the recess 8 is equal to the thickness of the interlayer insulating film 20 in the peripheral portion, and the bottom is the first glass substrate 12.
Surface. The organic flattening film 2 is formed in the recess 8.
Therefore, the organic flattening film 22 is formed thicker at the recess 8 than at the periphery.
【００１５】そのため、この実施の形態例においても、
凹部８の箇所では層間絶縁膜２０が形成されていないた
め層間絶縁膜２０による第１のガラス基板１２の反りは
発生しない。一方、凹部８の箇所では有機平坦化膜２２
の膜厚が厚いため、層間絶縁膜２０による第１のガラス
基板１２の反りを打ち消す、有機平坦化膜２２による第
１のガラス基板１２の反りが大きくなる。その結果、有
機平坦化膜２２上面の第１のガラス基板１２からの高さ
が従来と同じであっても、全体として層間絶縁膜２０に
よる第１のガラス基板１２の反りは、有機平坦化膜２２
による第１のガラス基板１２の反りにより従来より大き
く打ち消され、第１のガラス基板１２の反りが緩和され
る。Therefore, in this embodiment,
Since the interlayer insulating film 20 is not formed at the recess 8, the first glass substrate 12 does not warp due to the interlayer insulating film 20. On the other hand, the organic flattening film 22
Is thick, the warpage of the first glass substrate 12 due to the interlayer insulating film 20 is canceled out, and the warp of the first glass substrate 12 due to the organic planarizing film 22 is increased. As a result, even if the height of the upper surface of the organic flattening film 22 from the first glass substrate 12 is the same as that of the related art, the warpage of the first glass substrate 12 due to the interlayer insulating film 20 as a whole is caused by the organic flattening film. 22
As a result, the warpage of the first glass substrate 12 is largely cancelled, and the warpage of the first glass substrate 12 is reduced.
【００１６】[0016]
【発明の効果】以上説明したように本発明は、板面を対
向させ間に液晶層を介在させて配置された第１および第
２のガラス基板を含み、前記第１のガラス基板の前記液
晶層側の表面には、それぞれ透明電極を含む画素が多数
密に配列され、前記画素の配列領域の外側に前記画素の
駆動回路が形成され、前記画素の配列領域および前記駆
動回路の上に層間絶縁膜が形成され、前記層間絶縁膜の
上に有機平坦化膜が形成され、前記第２のガラス基板の
前記液晶層側の表面には対向電極が形成されている液晶
表示装置であって、前記第１のガラス基板上の前記層間
絶縁膜には、前記画素および前記駆動回路のいずれか一
方または両方の周辺において凹部、または周辺部より低
い段部が形成され、前記凹部および前記段部の箇所には
前記凹部および前記段部の周辺部より厚い前記有機平坦
化膜が形成されていることを特徴とする。As described above, the present invention includes the first and second glass substrates arranged with the liquid crystal layer interposed therebetween with the plate surfaces facing each other, and the liquid crystal of the first glass substrate is provided. On the layer-side surface, a large number of pixels each including a transparent electrode are densely arranged, and a drive circuit for the pixel is formed outside the pixel arrangement area. An interlayer is formed on the pixel arrangement area and the drive circuit. A liquid crystal display device, wherein an insulating film is formed, an organic planarizing film is formed on the interlayer insulating film, and a counter electrode is formed on a surface of the second glass substrate on the liquid crystal layer side, In the interlayer insulating film on the first glass substrate, a recess is formed around one or both of the pixel and the drive circuit, or a step lower than the periphery is formed, and the recess and the step of the step are formed. Where the recess and front Characterized in that thick the organic planarization layer from the peripheral portion of the step portion is formed.
【００１７】本発明の液晶表示装置では、第１のガラス
基板の層間絶縁膜には、画素および駆動回路のいずれか
一方または両方の周辺において凹部、または周辺部より
低い段部が形成されている。そして、凹部および段部の
箇所には凹部および段部の周辺部より厚い有機平坦化膜
が形成されている。したがって、凹部および段部の箇所
では、層間絶縁膜の膜厚が薄いか、または層間絶縁膜が
形成されていないため層間絶縁膜による第１のガラス基
板の反りは少ないか、または発生しない。一方、凹部お
よび段部の箇所では有機平坦化膜の膜厚が厚いため、層
間絶縁膜による第１のガラス基板の反りを打ち消す、有
機平坦化膜による第１のガラス基板の反りが大きくな
る。その結果、有機平坦化膜上面の第１のガラス基板か
らの高さが従来と同じであっても、全体として層間絶縁
膜による第１のガラス基板の反りは、有機平坦化膜によ
る第１のガラス基板の反りにより従来より大きく打ち消
され、第１のガラス基板の反りが緩和される。そのた
め、本発明により、輝度の低下や加工性の悪化を招くこ
となくガラス基板の反りを緩和して液晶表示装置製造時
の歩留まりを向上させることができる。In the liquid crystal display device of the present invention, the interlayer insulating film of the first glass substrate has a concave portion or a step portion lower than the peripheral portion in one or both of the pixel and the drive circuit. . An organic planarizing film thicker than the periphery of the concave portion and the step is formed at the position of the concave portion and the step. Therefore, in the concave portion and the step portion, the thickness of the interlayer insulating film is thin or the first glass substrate is not warped due to the interlayer insulating film because the interlayer insulating film is not formed. On the other hand, since the thickness of the organic flattening film is large in the concave portion and the stepped portion, the first glass substrate is warped by the organic flattening film to cancel the warpage of the first glass substrate due to the interlayer insulating film. As a result, even if the height of the upper surface of the organic planarization film from the first glass substrate is the same as that of the related art, the warpage of the first glass substrate due to the interlayer insulating film as a whole is caused by the first planarization film due to the organic planarization film. The warpage of the glass substrate cancels out more than the conventional case, and the warpage of the first glass substrate is reduced. Therefore, according to the present invention, it is possible to alleviate the warpage of the glass substrate and improve the yield at the time of manufacturing the liquid crystal display device without causing a decrease in luminance or a deterioration in workability.
【図１】本発明による液晶表示装置の一例を示す部分断
面側面図である。FIG. 1 is a partial sectional side view showing an example of a liquid crystal display device according to the present invention.
【図２】本発明による液晶表示装置の一例を示す平面図
である。FIG. 2 is a plan view illustrating an example of a liquid crystal display device according to the present invention.
【図３】有機平坦化膜の厚さとガラス基板の反り量との
関係を実測した結果を示すグラフである。FIG. 3 is a graph showing the results of actually measuring the relationship between the thickness of an organic planarizing film and the amount of warpage of a glass substrate.
【図４】本発明の第２の実施の形態例を示す部分断面側
面図である。FIG. 4 is a partial sectional side view showing a second embodiment of the present invention.
【図５】本発明の第２の実施の形態例を示す平面図であ
る。FIG. 5 is a plan view showing a second embodiment of the present invention.
【図６】本発明の第３の実施の形態例を示す部分断面側
面図である。FIG. 6 is a partial sectional side view showing a third embodiment of the present invention.
【図７】本発明の第３の実施の形態例を示す平面図であ
る。FIG. 7 is a plan view showing a third embodiment of the present invention.
【図８】従来の液晶表示装置を構成する一方のガラス基
板の一例を示す部分拡大断面側面図である。FIG. 8 is a partially enlarged cross-sectional side view showing one example of one glass substrate constituting a conventional liquid crystal display device.
【図９】従来の液晶表示装置を構成する一方のガラス基
板の一例を示す平面図である。FIG. 9 is a plan view showing an example of one glass substrate constituting a conventional liquid crystal display device.
２……薄膜トランジスタ、４……溝、６……段部、７…
…駆動回路、８……凹部、１２……第１のガラス基板、
１４……画素、１６……画素の配列領域、１８……薄膜
トランジスタ、２０……層間絶縁膜、２２……有機平坦
化膜。2 ... thin film transistor, 4 ... groove, 6 ... step, 7 ...
... Drive circuit, 8 ... Recess, 12 ... First glass substrate,
14 pixels, 16 pixels array region, 18 thin film transistor, 20 interlayer insulating film, 22 organic flattening film.
Claims (6)
配置された第１および第２のガラス基板を含み、前記第
１のガラス基板の前記液晶層側の表面には、それぞれ透
明電極を含む画素が多数密に配列され、前記画素の配列
領域の外側に前記画素の駆動回路が形成され、前記画素
の配列領域および前記駆動回路の上に層間絶縁膜が形成
され、前記層間絶縁膜の上に有機平坦化膜が形成され、
前記第２のガラス基板の前記液晶層側の表面には対向電
極が形成されている液晶表示装置であって、 前記第１のガラス基板上の前記層間絶縁膜には、前記画
素および前記駆動回路のいずれか一方または両方の周辺
において凹部、または周辺部より低い段部が形成され、 前記凹部および前記段部の箇所には前記凹部および前記
段部の周辺部より厚い前記有機平坦化膜が形成されてい
ることを特徴とする液晶表示装置。1. A liquid crystal device comprising: first and second glass substrates arranged with a liquid crystal layer interposed therebetween with their plate surfaces facing each other, and a transparent surface on the liquid crystal layer side of the first glass substrate. A large number of pixels including electrodes are densely arranged, a driving circuit of the pixel is formed outside the arrangement region of the pixels, an interlayer insulating film is formed on the arrangement region of the pixels and the driving circuit, An organic planarization film is formed on the film,
A liquid crystal display device in which a counter electrode is formed on a surface of the second glass substrate on the side of the liquid crystal layer, wherein the pixel and the driving circuit are provided on the interlayer insulating film on the first glass substrate. A concave portion or a step portion lower than the peripheral portion is formed around one or both of the above, and the organic flattening film thicker than the concave portion and the peripheral portion of the step portion is formed at the concave portion and the step portion. A liquid crystal display device characterized in that:
前記駆動回路を内側にして枠状に形成されていることを
特徴とする請求項１記載の液晶表示装置。2. The liquid crystal display device according to claim 1, wherein the step portion is formed in a frame shape with the pixel arrangement region and the drive circuit inside.
前記駆動回路を内側にして枠状の溝として形成されてい
ることを特徴とする請求項１記載の液晶表示装置。3. The liquid crystal display device according to claim 1, wherein the recess is formed as a frame-shaped groove with the pixel arrangement region and the drive circuit inside.
ことを特徴とする請求項１記載の液晶表示装置。4. The liquid crystal display device according to claim 1, wherein the driving circuit includes a thin film transistor.
記透明電極に接続された薄膜トランジスタが配設されて
いることを特徴とする請求項１記載の液晶表示装置。5. The liquid crystal display device according to claim 1, wherein a thin film transistor connected to the transparent electrode is provided for each pixel in the pixel arrangement region.
部の前記層間絶縁膜の厚みにほぼ等しいことを特徴とす
る請求項１記載の液晶表示装置。6. The liquid crystal display device according to claim 1, wherein the depths of the concave portion and the step portion are substantially equal to the thickness of the interlayer insulating film in a peripheral portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000023984A JP3351774B2 (en) | 2000-02-01 | 2000-02-01 | Liquid crystal display |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000023984A JP3351774B2 (en) | 2000-02-01 | 2000-02-01 | Liquid crystal display |
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| Publication Number | Publication Date |
|---|---|
| JP2001215483A true JP2001215483A (en) | 2001-08-10 |
| JP3351774B2 JP3351774B2 (en) | 2002-12-03 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004101976A (en) * | 2002-09-11 | 2004-04-02 | Sony Corp | Thin-film circuit board |
| US7582903B2 (en) | 2002-11-14 | 2009-09-01 | Samsung Electronics Co., Ltd. | Thin film transistor array panel |
| US7795796B2 (en) | 2005-01-18 | 2010-09-14 | Seiko Epson Corporation | Wiring substrate, electro optic device and electronic equipment |
| CN104600029A (en) * | 2015-01-16 | 2015-05-06 | 昆山工研院新型平板显示技术中心有限公司 | Flexible display device and manufacture method thereof |
| CN104752365A (en) * | 2013-12-27 | 2015-07-01 | 昆山国显光电有限公司 | Flexible display and manufacturing method thereof |
| CN105845701A (en) * | 2015-01-16 | 2016-08-10 | 昆山工研院新型平板显示技术中心有限公司 | Flexible display device and making method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109768054B (en) * | 2019-02-25 | 2020-11-10 | 云谷（固安）科技有限公司 | Array substrate and display screen |
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2000
- 2000-02-01 JP JP2000023984A patent/JP3351774B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004101976A (en) * | 2002-09-11 | 2004-04-02 | Sony Corp | Thin-film circuit board |
| US7582903B2 (en) | 2002-11-14 | 2009-09-01 | Samsung Electronics Co., Ltd. | Thin film transistor array panel |
| US7795796B2 (en) | 2005-01-18 | 2010-09-14 | Seiko Epson Corporation | Wiring substrate, electro optic device and electronic equipment |
| CN104752365A (en) * | 2013-12-27 | 2015-07-01 | 昆山国显光电有限公司 | Flexible display and manufacturing method thereof |
| CN104600029A (en) * | 2015-01-16 | 2015-05-06 | 昆山工研院新型平板显示技术中心有限公司 | Flexible display device and manufacture method thereof |
| CN105845701A (en) * | 2015-01-16 | 2016-08-10 | 昆山工研院新型平板显示技术中心有限公司 | Flexible display device and making method thereof |
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| Publication number | Publication date |
|---|---|
| JP3351774B2 (en) | 2002-12-03 |
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