JP2001210445A - Chip-type surge absorption element and its manufacturing method - Google Patents

Chip-type surge absorption element and its manufacturing method

Info

Publication number
JP2001210445A
JP2001210445A JP2000022340A JP2000022340A JP2001210445A JP 2001210445 A JP2001210445 A JP 2001210445A JP 2000022340 A JP2000022340 A JP 2000022340A JP 2000022340 A JP2000022340 A JP 2000022340A JP 2001210445 A JP2001210445 A JP 2001210445A
Authority
JP
Japan
Prior art keywords
pair
internal electrodes
area
discharge space
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000022340A
Other languages
Japanese (ja)
Inventor
Haruki Hoshi
晴輝 保志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tokin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokin Corp filed Critical Tokin Corp
Priority to JP2000022340A priority Critical patent/JP2001210445A/en
Publication of JP2001210445A publication Critical patent/JP2001210445A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a chip-type surge absorption element and its manufacturing method having a small electrostatic capacity and an easy surface mounting capability to a substrate and an easy manufacturing procedure. SOLUTION: The chip-type surge absorption element in which in the inside of a ceramic sintering object having insulation characteristic which has a pair of external electrode, a 1st internal electrode 2a, 2b with a small area, a 2nd internal electrode 3a, 3b with a large area, and an electric discharge space 4 are formed, a ratio of the area of the above first internal electrode 2a, 2b of the exposed to the electric discharge space 4 and the area of the above 2nd internal electrode 3a, 3b exposed to the electric discharge space 4 is in the range of 1 to 99, to 40 to 60, and the 2nd internal electrodes 3a, 3b are placed opposite to each other, and the 1st internal electrodes 2a, 2b exists in the middle of the distance between the 2nd internal electrode 3a and 3b so that the distance 11 between two gaps closest to each other may become equal. And moreover, the 1st internal electrodes 2a, 2b and the 2nd internal electrodes 3a, 3b do not exist on the same plane.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子回路や電子部
品をサージから保護するのに好適なサージ吸収素子で、
プリント基板への自動実装に好適な積層タイプのチップ
型サージ吸収素子およびその製造方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surge absorbing element suitable for protecting electronic circuits and electronic components from surges.
The present invention relates to a multilayer chip-type surge absorbing element suitable for automatic mounting on a printed circuit board and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、通信機器等をサージから保護する
サージ吸収素子として、電圧非直線性を有する高抵抗素
子よりなるバリスタや放電空間を気密容器内に封入した
放電式サージ吸収素子等が広く利用されている。
2. Description of the Related Art Conventionally, as a surge absorbing element for protecting a communication device from a surge, a varistor composed of a high resistance element having a voltage non-linearity and a discharge type surge absorbing element having a discharge space sealed in an airtight container have been widely used. It's being used.

【0003】従来のバリスタは、サージ吸収の応答性に
優れると共に、素子の小型化や表面実装化が容易である
とういう利点を有している。しかし、静電容量が大きく
信号系回路に不向きであるという欠点を有する。従来の
放電式サージ吸収素子は、静電容量が小さく信号系回路
にも広く利用される。しかし、気密構造とする必要があ
るため、ガラス封入しリード線を引き出す構造となって
いる。そのため、基板への実装には、リード線の適切な
長さへの切断、曲げ加工を行った後、基板の穴へ挿入し
半田付けするとう方法で工数が多くかかるものであっ
た。
Conventional varistors have the advantage of being excellent in responsiveness to surge absorption and of being easy to miniaturize and surface mount elements. However, there is a disadvantage that the capacitance is large and is not suitable for a signal system circuit. Conventional discharge-type surge absorbing elements have a small capacitance and are widely used in signal circuits. However, since it is necessary to have an airtight structure, the structure is such that glass is sealed and lead wires are drawn out. Therefore, mounting on a board requires a lot of man-hours by cutting and bending lead wires into appropriate lengths, and then inserting the leads into holes in the board and soldering.

【0004】[0004]

【発明が解決しようとする課題】従来のバリスタには、
以下の問題点があった。即ち、静電容量が大きく信号系
回路に不向きであるという欠点を有する。
[0007] Conventional varistors include:
There were the following problems. That is, there is a disadvantage that the capacitance is large and is not suitable for a signal system circuit.

【0005】また、従来の放電式サージ吸収素子には、
以下の問題点があった。即ち、気密構造とするため、ガ
ラス封入しリード線を引き出す構造となっているが、そ
のため基板への実装には、リード線の適切な長さへの切
断、曲げ加工を行った後、基板の穴へ挿入し半田付けす
るという方法を取り、工数が多くかかるものであった。
[0005] Further, in the conventional discharge type surge absorbing element,
There were the following problems. That is, in order to have an airtight structure, the structure is such that the lead wire is drawn out by enclosing the glass, but for mounting on the board, the lead wire is cut and bent to an appropriate length, The method of inserting into the hole and soldering was adopted, which required a lot of man-hours.

【0006】現在では、多くの電子部品が表面実装型へ
と移り変わっており、表面実装型のサージ吸収素子の提
案もなされている(特開平7−245878、出願人:
三菱マテリアル)。しかしながら、放電ギャップを気密
に保つため、数枚のセラミックス板を張り付ける等、工
数がかかり大量生産には不向きである。
At present, many electronic components have been switched to surface mount type devices, and surface mount type surge absorbing elements have been proposed (Japanese Patent Application Laid-Open No. Hei 7-245878, applicant:
Mitsubishi Materials). However, this method is not suitable for mass production because it requires a lot of man-hours such as attaching several ceramic plates to keep the discharge gap airtight.

【0007】従って、本発明の目的は、静電容量を小と
し、基板への表面実装が容易であり、かつ、製造容易
で、低コストなチップ型サージ吸収素子およびその製造
方法を提供することである。
Accordingly, it is an object of the present invention to provide a low-cost chip-type surge absorbing element which has a small capacitance, is easily surface-mounted on a substrate, is easy to manufacture, and has a low cost. It is.

【0008】[0008]

【課題を解決するための手段】本発明のチップ型サージ
吸収素子は、一対の外部電極を有する絶縁性セラミック
ス焼結体内部に放電空間と、第1の内部電極と第2の内
部電極とを形成したチップ型サージ吸収素子であって、
前記第1の内部電極の放電空間露出面の面積と、第2の
内部電極の放電空間露出面の面積比が、1対99から4
0対60の範囲であり、かつ面積の大きい方の第2の内
部電極は対面になるように存在し、この第2の電極間距
離の中間に、異極の小さい面積の第2の内部電極が存在
し、前記の両者の内部電極が、第2の内部電極と同一平
面に存在せず、第2の内部電極、および放電空間への露
出形状が円形であり、電極間ギャップに形成される放電
空間の平面の面積が、円形電極の直径により形成される
面積より大きい平面をもった空間であることを特徴とし
たチップ型サージ吸収素子である。
According to the present invention, there is provided a chip type surge absorbing element comprising a discharge space, a first internal electrode and a second internal electrode inside an insulating ceramic sintered body having a pair of external electrodes. The formed chip type surge absorbing element,
The area ratio of the discharge space exposed surface of the first internal electrode to the discharge space exposed surface of the second internal electrode is from 1:99 to 4
The second internal electrodes having a range of 0 to 60 and having a larger area exist so as to face each other, and a second internal electrode having a small area of a different polarity is provided in the middle of the distance between the second electrodes. Exists, the two internal electrodes do not exist on the same plane as the second internal electrode, the second internal electrode and the shape of exposure to the discharge space are circular, and are formed in the gap between the electrodes. The chip-type surge absorbing element is characterized in that the discharge space is a space having a plane having a larger area than the area formed by the diameter of the circular electrode.

【0009】このように、内部電極間の最近接部が、第
2の電極と同一平面上でないことによって、放電の切っ
掛けは、面積の大きい第2の内部電極と面積の小さい異
極の第2の内部電極間で起きるが、放電が進みアーク放
電に至るときには面対向となっている第2の内部電極で
放電経路が形成される。そのため、面積の小さい第1の
内部電極の放電による電極損傷は、最小限に押さえられ
る。
As described above, since the closest portion between the internal electrodes is not on the same plane as the second electrode, the discharge is started by the second internal electrode having a large area and the second electrode having a different area having a small area. However, when the discharge proceeds and reaches the arc discharge, a discharge path is formed by the second internal electrodes facing each other. Therefore, electrode damage due to the discharge of the first internal electrode having a small area is minimized.

【0010】つまり、繰り返し放電させた場合に、放電
の切っ掛け、言い換えると放電開始電圧が安定し繰り返
し放電による特性変動が少なくなる。さらには、放電空
間部の平面の面積を第2の内部電極より大きな平面面積
をもった空間にすることにより、第2の内部電極部ある
いは放電空間の電極以外の部分のスパッタ粒子により短
絡にいたるのを延命することが可能である。つまり、チ
ップ型サージ吸収素子の寿命を長くすることが可能であ
る。
[0010] That is, when the discharge is repeated, the discharge starts, in other words, the discharge starting voltage is stabilized, and the characteristic fluctuation due to the repeated discharge is reduced. Further, by setting the plane area of the discharge space to a space having a larger plane area than the second internal electrode, a short circuit may be caused by sputtered particles other than the second internal electrode or the electrode of the discharge space. It is possible to prolong life. That is, it is possible to prolong the life of the chip type surge absorbing element.

【0011】また、面積の小さい第1の内部電極と面積
の大きい第2の内部電極間の中間で、二箇所の最近接部
のギャップ間距離を等しくすることにより、基板に実装
する際、素子の取り付け方向を無くすことが可能であ
る。また、本発明の素子は、印刷法、グリーンシート法
によって作製することを特徴としており、従来技術のも
とで大量生産が可能である。
In addition, by equalizing the distance between the gaps at the two closest points in the middle between the first internal electrode having a small area and the second internal electrode having a large area, the element can be mounted on a substrate. It is possible to eliminate the mounting direction. Further, the element of the present invention is characterized by being manufactured by a printing method and a green sheet method, and can be mass-produced based on a conventional technique.

【0012】即ち、本発明は、一対の外部電極を有する
絶縁性セラミックス焼結体内部に、面積の小さい一対の
第1の内部電極と、面積の大きい一対の第2の内部電極
と、放電空間が形成されたチップ型サージ吸収素子にお
いて、前記一対の第1の内部電極の放電空間への露出部
の面積と、前記第2の内部電極の放電空間への露出部の
面積との比率が、1対99から40対60の範囲であ
り、一対の第2の内部電極が、各々対面になるように存
在し、この一対の電極間距離の中間に、一対の第1の内
部電極が二箇所のギャップ間距離が等しくなるように各
々存在し、かつ、前記一対の第1の内部電極と第2の内
部電極が、同一平面上に存在しないチップ型サージ吸収
素子である。
That is, according to the present invention, a pair of first internal electrodes having a small area, a pair of second internal electrodes having a large area, and a discharge space are provided inside an insulating ceramic sintered body having a pair of external electrodes. Is formed, the ratio of the area of the exposed portion of the pair of first internal electrodes to the discharge space to the area of the exposed portion of the second internal electrode to the discharge space is: It is in the range of 1:99 to 40:60, and a pair of second internal electrodes are present so as to face each other, and a pair of first internal electrodes is provided at two positions in the middle of the distance between the pair of electrodes. And the pair of first internal electrodes and second internal electrodes do not exist on the same plane.

【0013】また、本発明は、前記一対の第2の内部電
極の、放電空間への露出面の形状は円形であり、かつ電
極間ギャップ内に形成される放電空間の平面の面積が、
前記一対の第2の内部電極の面積より大きいチップ型サ
ージ吸収素子である。
Further, according to the present invention, the shape of the surface of the pair of second internal electrodes exposed to the discharge space is circular, and the plane area of the discharge space formed in the gap between the electrodes is:
The chip type surge absorbing element is larger than the area of the pair of second internal electrodes.

【0014】また、本発明は、一対の外部電極を有する
絶縁性セラミックス焼結体内部に、面積の小さい一対の
第1の内部電極と、面積の大きい一対の第2の内部電極
と、放電空間を形成するチップ型サージ吸収素子の製造
方法において、前記一対の第1の内部電極の放電空間へ
の露出部の面積と、前記第2の内部電極の放電空間への
露出部の面積との比率を、1対99から40対60の範
囲とし、一対の第2の内部電極が、各々対面になるよう
にし、一対の第2の内部電極間距離の中間に、一対の第
1の内部電極が二箇所のギャップ間距離が等しくなるよ
うに形成し、かつ、前記一対の第1の内部電極と第2の
内部電極が、同一平面上に存在しないようにしたチップ
型サージ吸収素子の製造方法である。
According to the present invention, a pair of first internal electrodes having a small area, a pair of second internal electrodes having a large area, and a discharge space are provided inside an insulating ceramic sintered body having a pair of external electrodes. The ratio of the area of the exposed portion of the pair of first internal electrodes to the discharge space to the area of the exposed portion of the second internal electrode to the discharge space. Is set in a range of 1:99 to 40:60, the pair of second internal electrodes are respectively opposed to each other, and the pair of first internal electrodes is provided in the middle of the distance between the pair of second internal electrodes. A method of manufacturing a chip-type surge absorbing element, wherein the distance between two gaps is formed to be equal, and the pair of first internal electrodes and second internal electrodes do not exist on the same plane. is there.

【0015】また、本発明は、前記チップ型サージ吸収
素子の製造方法は、印刷法あるいはグリーンシート法に
よって形成するチップ型サージ吸収素子の製造方法であ
る。
Further, in the present invention, the method for manufacturing a chip-type surge absorbing element is a method for manufacturing a chip-type surge absorbing element formed by a printing method or a green sheet method.

【0016】[0016]

【実施例】本発明によるチップ型サージ吸収素子および
その製造方法について、以下に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A chip type surge absorbing element and a method of manufacturing the same according to the present invention will be described below.

【0017】図1は、本発明の実施例によるチップ型サ
ージ吸収素子の側面図である。また図2は、図1のチッ
プ型サージ吸収素子でのA−A断面図を示す。
FIG. 1 is a side view of a chip type surge absorbing element according to an embodiment of the present invention. FIG. 2 is a sectional view taken along the line AA of the chip-type surge absorbing element of FIG.

【0018】図1のチップ型サージ吸収素子において、
絶縁性セラミック1,6として主成分NaO・B
・SiOのガラスを40重量%添加したステアタイ
トとした。また、第1の内部電極2a,2bと第2の内
部電極3a,3bは、Ag−30%Pdを用い、スクリ
ーン印刷法により作製し、1000℃で焼結を行った。
In the chip type surge absorbing element shown in FIG.
Main component Na 2 O · B 2 O as the insulating ceramic 1,6
3. Steatite to which 40% by weight of SiO 2 glass was added. Further, the first internal electrodes 2a and 2b and the second internal electrodes 3a and 3b were formed by a screen printing method using Ag-30% Pd, and were sintered at 1000C.

【0019】図1において、大面積の第2の内部電極3
a,3bと、小面積の第1の内部電極2a,2bとは、
同一材質としたが、お互いに異なる材質を用いてもよ
い。その場合、第1の内部電極2a,2bの抵抗値が、
第2の内部電極3a,3bの抵抗値より小さいことが望
ましい。放電空間4は、カーボンペーストをスクリーン
印刷で放電空間部に充填し、焼結時に焼失させて形成し
た。外部電極5a,5bは、600℃でAg電極を焼き
つけた後、Niめっきを施して形成した。
In FIG. 1, a large-area second internal electrode 3
a, 3b and the small-area first internal electrodes 2a, 2b
Although the same material is used, different materials may be used. In that case, the resistance value of the first internal electrodes 2a, 2b is
It is desirable that the resistance value is smaller than the resistance values of the second internal electrodes 3a and 3b. The discharge space 4 was formed by filling a discharge space portion with a carbon paste by screen printing and burning it out during sintering. The external electrodes 5a and 5b were formed by baking an Ag electrode at 600 ° C. and then applying Ni plating.

【0020】なお、前記絶縁性セラミック1,6、第1
の内部電極2a,2b、第2の内部電極3a,3b、外
部電極5a,5bの材質は、上記の材質に限るものでは
ない。また、チップ型サージ吸収素子の電極形状は、図
1の実施例に限るものではない。
The insulating ceramics 1, 6 and the first
The materials of the internal electrodes 2a and 2b, the second internal electrodes 3a and 3b, and the external electrodes 5a and 5b are not limited to the above materials. Further, the electrode shape of the chip type surge absorbing element is not limited to the embodiment of FIG.

【0021】実施例において、第2の内部電極3a,3
bの円形状電極の外径を、90μm、これに垂直になる
面の第1の内部電極2a,2bの円形状電極の外径を1
0μm、電極間での最近接部のギャップを50μm、放
電空間4の長辺を200μmとして放電実験を行った。
その結果、直流放電開始電圧は、約500Vであった。
In the embodiment, the second internal electrodes 3a, 3
The outer diameter of the circular electrode b is 90 μm, and the outer diameter of the circular electrodes of the first internal electrodes 2a and 2b on the surface perpendicular to this is 1 μm.
A discharge experiment was performed with 0 μm, a gap between electrodes closest to each other at 50 μm, and a long side of the discharge space 4 at 200 μm.
As a result, the DC start voltage was about 500V.

【0022】この素子に静電気サージ(10kV−15
0pF−330Ω)を10000回、印加した後の直流
放電開始電圧のばらつきは、初期値に対して±30%以
内の変動であった。
An electrostatic surge (10 kV-15) is applied to this element.
(0 pF-330Ω) was applied 10,000 times, and the variation of the DC discharge start voltage was within ± 30% of the initial value.

【0023】また、一対の第1の内部電極の面積と、一
対の第2の内部電極の面積の比を、1対99から40対
60の範囲としたのは、この範囲以外の場合に、放電開
始電圧のばらつきが大きくなるためである。さらに、絶
縁抵抗は、1010Ω以上の値を示した。この結果は、
従来のギャップ放電式サージ吸収素子の特性と同等もし
くはそれ以上の特性値である。
The ratio of the area of the pair of first internal electrodes to the area of the pair of second internal electrodes is set in the range of 1:99 to 40:60. This is because the variation in the discharge starting voltage increases. Furthermore, the insulation resistance showed a value of 10 10 Ω or more. The result is
The characteristic value is equal to or higher than the characteristic of the conventional gap discharge type surge absorbing element.

【0024】以上より、本発明によるチップ型サージ吸
収素子は、従来のスクリーン印刷技術等の量産性の高い
技術を利用した容易な製造工程で、サージ寿命特性の優
れた表面実装型サージ吸収素子が得られる。
As described above, the chip-type surge absorbing element according to the present invention is a surface-mount type surge absorbing element having excellent surge life characteristics in an easy manufacturing process utilizing a technique having high productivity such as a conventional screen printing technique. can get.

【0025】[0025]

【発明の効果】以上、本発明によれば、静電容量を小と
し、基板への表面実装が容易であり、かつ製造容易で、
低コストなチップ型サージ吸収素子およびその製造方法
を提供することができる。
As described above, according to the present invention, the capacitance is reduced, the surface mounting on the substrate is easy, and the manufacturing is easy.
A low-cost chip-type surge absorbing element and a method of manufacturing the same can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例によるチップ型サージ吸収素子
の側面図。
FIG. 1 is a side view of a chip type surge absorbing element according to an embodiment of the present invention.

【図2】図1のチップ型サージ吸収素子のA−A断面
図。
FIG. 2 is an AA cross-sectional view of the chip type surge absorbing element of FIG.

【符号の説明】[Explanation of symbols]

1,6 絶縁性セラミック 2a,2b 第1の内部電極 3a,3b 第2の内部電極 4 放電空間 5a,5b 外部電極 11 最近接部のギャップ間距離 1,6 Insulating ceramic 2a, 2b First internal electrode 3a, 3b Second internal electrode 4 Discharge space 5a, 5b External electrode 11 Distance between gaps of closest part

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 一対の外部電極を有する絶縁性セラミッ
クス焼結体内部に、面積の小さい一対の第1の内部電極
と、面積の大きい一対の第2の内部電極と、放電空間が
形成されたチップ型サージ吸収素子において、前記一対
の第1の内部電極の放電空間への露出部の面積と、前記
第2の内部電極の放電空間への露出部の面積との比率
が、1対99から40対60の範囲であり、一対の第2
の内部電極が、各々対面になるように存在し、一対の第
2の内部電極間距離の中間に、一対の第1の内部電極が
二箇所のギャップ間距離が等しくなるように各々存在
し、かつ、前記一対の第1の内部電極と第2の内部電極
が、同一平面上に存在しないことを特徴とするチップ型
サージ吸収素子。
1. A pair of first internal electrodes having a small area, a pair of second internal electrodes having a large area, and a discharge space are formed inside an insulating ceramic sintered body having a pair of external electrodes. In the chip-type surge absorbing element, the ratio of the area of the exposed portion of the pair of first internal electrodes to the discharge space to the area of the exposed portion of the second internal electrode to the discharge space is from 1:99. Range of 40:60, and a pair of second
Are present such that they face each other, and between the pair of second internal electrodes, a pair of first internal electrodes are present such that the distance between the two gaps is equal, The chip-type surge absorbing element is characterized in that the pair of first internal electrodes and second internal electrodes do not exist on the same plane.
【請求項2】 前記一対の第2の内部電極の、放電空間
への露出面の形状は円形であり、かつ電極間ギャップ内
に形成される放電空間の平面の面積が、前記一対の第2
の内部電極の面積より大きいことを特徴とする請求項1
記載のチップ型サージ吸収素子。
2. The shape of the surface of the pair of second internal electrodes exposed to the discharge space is circular, and the area of the plane of the discharge space formed in the gap between the electrodes is equal to that of the pair of second internal electrodes.
The area of the internal electrode is larger than the area of the internal electrode.
The chip-type surge absorbing element as described.
【請求項3】 一対の外部電極を有する絶縁性セラミッ
クス焼結体内部に、面積の小さい一対の第1の内部電極
と、面積の大きい一対の第2の内部電極と、放電空間を
形成するチップ型サージ吸収素子の製造方法において、
前記一対の第1の内部電極の放電空間への露出部の面積
と、前記第2の内部電極の放電空間への露出部の面積と
の比率を、1対99から40対60の範囲とし、一対の
第2の内部電極が、各々対面になるようにし、この一対
の第2の内部電極間距離の中間に、一対の第1の内部電
極が二箇所のギャップ間距離が等しくなるように形成
し、かつ、前記一対の第1の内部電極と第2の内部電極
が、同一平面上に存在しないように形成することを特徴
とするチップ型サージ吸収素子の製造方法。
3. A chip forming a pair of first internal electrodes having a small area, a pair of second internal electrodes having a large area, and a discharge space inside an insulating ceramics sintered body having a pair of external electrodes. In the method of manufacturing a type surge absorbing element,
The ratio of the area of the exposed portion of the pair of first internal electrodes to the discharge space and the ratio of the area of the exposed portion of the second internal electrode to the discharge space is in the range of 1:99 to 40:60, The pair of second internal electrodes are made to face each other, and a pair of first internal electrodes are formed so that the distance between two gaps is equal to the middle of the distance between the pair of second internal electrodes. And forming the pair of first internal electrodes and second internal electrodes so that they do not exist on the same plane.
【請求項4】 前記チップ型サージ吸収素子の製造方法
は、印刷法あるいはグリーンシート法によって形成する
ことを特徴とする請求項3記載のチップ型サージ吸収素
子の製造方法。
4. The method of manufacturing a chip-type surge absorbing element according to claim 3, wherein the method of manufacturing the chip-type surge absorbing element is formed by a printing method or a green sheet method.
JP2000022340A 2000-01-31 2000-01-31 Chip-type surge absorption element and its manufacturing method Pending JP2001210445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000022340A JP2001210445A (en) 2000-01-31 2000-01-31 Chip-type surge absorption element and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000022340A JP2001210445A (en) 2000-01-31 2000-01-31 Chip-type surge absorption element and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2001210445A true JP2001210445A (en) 2001-08-03

Family

ID=18548658

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2001210445A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100817485B1 (en) 2007-08-28 2008-03-31 김선호 Discharge element with discharge-control electrode and the control circuit thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100817485B1 (en) 2007-08-28 2008-03-31 김선호 Discharge element with discharge-control electrode and the control circuit thereof
WO2009028881A3 (en) * 2007-08-28 2009-04-23 Surgelab Korea Discharge element with discharge-control electrode and the control circuit thereof
AU2008293219B2 (en) * 2007-08-28 2011-05-12 Seonho Kim Discharge element with discharge-control electrode and the control circuit thereof
US8227989B2 (en) 2007-08-28 2012-07-24 Surgelab Korea Discharge element with discharge-control electrode and the control circuit thereof

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