JP2001204947A - Pachinko game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pachinko game machine, which judges whether or not power is shut off, and when it is not, avoids a trouble that a game controller remains stopped to prevent playing games in spite of power recovery. SOLUTION: A controller 1 receives a voltage reduction signal outputted by a power voltage monitoring circuit IC2 at the NM1 terminal and input terminal thereof. The pachinko game machine comprises a processing means which monitors the presence or absence of the voltage reduction signal through an input port at NMI interrupt operation in response to the voltage reduction signal inputted to the NMI terminal to stop the controller 1 judging that power is off when the voltage reduction signal is received for a predetermined period of time while finish the NMI interruption and perform the normal operation of the controller 1 judging that the power is not off when the voltage reduction signal is not received for the predetermined period of time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention monitors a power supply voltage drop in case the operating power supply (power supply voltage) supplied to a control device is cut off for some reason, and forcibly acts when the power supply voltage falls below a predetermined voltage. The present invention relates to a pachinko game machine having a processing means for generating an interrupt (NMI interrupt), prohibiting writing to a RAM until the power is turned off within the interrupt, and putting the control device into a sleep state.

[0002]

2. Description of the Related Art Game control C mounted on a pachinko machine
In preparation for a case where the operating power supply (power supply voltage) supplied to the PU is cut off for some reason, a power supply voltage drop is monitored, and when the power supply voltage falls below a predetermined voltage, a forced interrupt (NMI interrupt) is generated. Until the power is turned off, the predetermined process [writing to the RAM is prohibited and the game control C
Putting PU into Halt State].

[0003] When monitoring a power supply voltage drop, a forced interrupt (NMI interrupt) may occur due to the occurrence of noise or a momentary voltage drop (hereinafter referred to as an instantaneous voltage drop). In this case, writing to the RAM is performed. Prohibit game control CPU
Is performed, the game control CPU remains in a paused state and cannot play a game, even though the operating power supply has returned to normal.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to determine whether power is off or not, that is, whether noise or a momentary voltage drop occurs.
It is an object of the present invention to provide a pachinko gaming machine capable of avoiding a problem that a control device relating to game control remains inactive and a game cannot be performed even though an operation power supply has returned to normal.

[0005]

SUMMARY OF THE INVENTION A pachinko gaming machine according to the present invention comprises a control device and a power supply voltage monitoring circuit for outputting a voltage drop signal in response to a drop in power supply voltage. The power supply voltage monitoring circuit has an output terminal connected to an NMI terminal and an input port of the control device, and a voltage drop signal output from the power supply voltage monitoring circuit is input to an NMI terminal and an input terminal of the control device. And providing the control device with the NMI of the voltage drop signal.
In an NMI interrupt in response to an input to a terminal, the presence or absence of the voltage drop signal is monitored through the input port, and if the voltage drop signal has been input for a predetermined period of time, the power is turned off and the control is performed. While the apparatus is in the sleep state, if the voltage drop signal has not been input for a predetermined time, it is determined that the power supply is not interrupted, the NMI interrupt is terminated, and processing means for processing the normal state of the control apparatus is provided. It is characterized by having been provided.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a part of a control system provided in the pachinko gaming machine of the present embodiment. The control device 1, the power supply voltage monitoring IC 2 and the power supply voltage monitoring IC 3 shown in FIG. 1 are mounted on one control board (not shown).

[0007] The control device 1 is for transmitting and receiving control signals and data to and from an external device, including a CPU, a ROM storing control programs executed by the CPU, a RAM from which data can be read and written at any time. And a microcontroller provided with an internal I / O port, an internal bus (including a data bus), and the like in a single chip. The illustration of the specific internal configuration of the control device 1 is omitted.

Power supply voltage monitoring IC 2 and power supply voltage monitoring IC
Reference numeral 3 is a signal for outputting a voltage reduction signal (reset signal) from the RESET terminal when the operating voltage is reduced due to, for example, power-off. Voltage input terminal V of power supply voltage monitoring IC2
A DC of 12 V generated by a power supply circuit (not shown) is input to SD. Power supply voltage monitoring IC
The voltage input terminal VSD of No. 3 is supplied with DC 5 V similarly generated in the power supply circuit.

The voltage drop signal 1 output from the RESET terminal of the power supply voltage monitoring IC 2 is supplied to the P / P of the built-in I / O port of the control device 1 through the signal lines L1 and L2.
It is input to the B0 terminal. The voltage drop signal 1 is
Control device 1 through signal line L1 and signal line L3
XNMI terminal (non-maskable interrupt terminal).

The voltage drop signal 2 output from the RESET terminal of the power supply voltage monitoring IC 3 is supplied to the XSRST terminal (system reset terminal) of the control device 1 through the signal line L4.
It is configured to be input to. In FIG. 1, the voltage drop signal 1 and the voltage drop signal 2 are active at a low level. The first character “X” at the XNMI terminal and the XSRST terminal indicates that the signal is negative logic.

An NMI interrupt process according to the voltage drop signal 1 output from the RESET terminal of the power supply voltage monitoring IC 2 in the control device 1 of the embodiment configured as described above will be described. Note that the RESE of the power supply voltage monitoring IC 2
It is determined whether the voltage drop signal 1 output from the T terminal is due to power-off or not due to power-off, that is, whether noise or an instantaneous voltage drop occurs. The determination is made by monitoring the input state of the terminal for a predetermined time.

FIG. 2 is a time chart showing the level states of the PB0 terminal, the XNMI terminal, and the XSRST terminal of the control device 1 when the power is turned off. FIG.
6 is a time chart showing the level states of the PB0 terminal, the XNMI terminal, and the XSRST terminal of the control device 1 when noise or a momentary voltage drop occurs.

First, the case where the power is turned off will be described. Since the power supply voltage signal 1 is active at the low level and the voltage drop signal 2 is active at the low level, the power supply voltage signal 1 and the voltage drop signal 2 are at the high level before the power failure occurs.

When the power supply is cut off (when the power supply voltage drops), first, the voltage applied to the voltage input terminal VSD of the power supply voltage monitoring IC 2 drops from 12 V to the GND level (ground level). I will do it. When the voltage applied to the voltage input terminal VSD falls below the 12V threshold level, the RES of the power supply voltage monitoring IC 2
The output of the ET terminal changes from high level to low level. That is, the power supply voltage monitoring IC 2 outputs the voltage drop signal 1.

The voltage drop signal 1 is output from PB0 of the control device 1.
Terminal and the XNMI terminal. In the control device 1, X
When a low level is input to the NMI terminal, an NMI interrupt occurs, and NMI interrupt processing is started.

After the voltage drop signal 1 is output from the RESET terminal of the power supply voltage monitoring IC 2, the voltage applied to the voltage input terminal VSD of the power supply voltage monitoring IC 3 is changed from 5 V to the GND level (ground level). Start descent towards. Then, when the voltage applied to the voltage input terminal VSD falls below the 5V threshold level,
The output of the RESET terminal of the power supply voltage monitoring IC 3 changes from the high level to the low level. That is, the power supply voltage monitoring IC 3 outputs the voltage drop signal 2. The power supply voltage monitoring I
When the voltage drop signal 2 is output from the RESET terminal of C3, the voltage applied to the voltage input terminal VSD of the power supply voltage monitoring IC 2 is reduced to the GND level (ground level).

The voltage drop signal 2 output from the power supply voltage monitoring IC 3 is input to the XSRST terminal of the control device 1. In the control device 1, when a low level is input to the XSRST terminal, a system reset is performed.

The control device 1 activates the NMI interrupt processing when the voltage drop signal 1 is input to the PB0 terminal and the XNMI terminal, and starts the time T1 from this time until the voltage drop signal 2 is input to the XSRST terminal. , The writing to the RAM is prohibited in the NMI interrupt processing, the input state of the PB0 terminal is monitored for a predetermined time from this point, and it is determined whether or not the input state of the PB0 terminal is at a high level. In this case, since the input of the PB0 terminal remains at the low level, the control device 1 is set to the HALT state.

Next, a case where the power is not cut off, that is, a case where a voltage drop occurs due to noise or a momentary voltage drop will be described. As shown in FIG. 3, even when the voltage drop is caused by the occurrence of noise or a momentary voltage drop, the voltage applied to the voltage input terminal VSD of the power supply voltage monitoring IC 2 is changed from 12 V to the GND level (ground level). Descend toward it. However, the voltage applied to the voltage input terminal VSD of the power supply voltage monitoring IC 2 does not fall to the GND level (ground level), and
A certain voltage equal to or lower than the 2V threshold level rises again as the minimum voltage, and returns to the normal voltage of 12V.

The voltage input terminal VSD of the power supply voltage monitoring IC 2
At the time when the voltage supplied to the power supply voltage monitoring IC2 falls below the 12V threshold level, the output of the RESET terminal of the power supply voltage monitoring IC2 changes from the high level to the low level, and the voltage drop signal 1 is output from the power supply voltage monitoring IC2. Then, the voltage drop signal 1 is input to the PB0 terminal and the XNMI terminal of the control device 1. Therefore, in the control device 1, the XNMI
When a low level is input to the terminal, an NMI interrupt occurs, and NMI interrupt processing starts. The control device 1 is an NM
In I interrupt processing, writing to RAM is prohibited. After the voltage drop signal 1 is output from the RESET terminal of the power supply voltage monitoring IC 2, the voltage applied to the voltage input terminal VSD of the power supply voltage monitoring IC 3 is changed from 5 V to GN.
Start descending toward D level (ground level).

Thereafter, when the voltage applied to the voltage input terminal VSD of the power supply voltage monitoring IC 2 drops to a certain voltage (minimum voltage) below the 12V threshold level, it starts rising again and is applied to the voltage input terminal VSD. When the voltage exceeds the 12V threshold level, the output of the RESET terminal of the power supply voltage monitoring IC 2 changes from the low level to the high level, and the output of the voltage drop signal 1 from the power supply voltage monitoring IC 2 turns off. At this point, the P
The input of the B0 terminal changes from a low level to a high level. Then, the voltage applied to the voltage input terminal VSD further increases and returns to the normal voltage of 12V.

In the NMI interrupt processing, the control device 1 inhibits writing to the RAM, monitors the input state of the PB0 terminal for a predetermined time from this point, and determines whether the input state of the PB0 terminal is at a high level. Is determined. When the power is not turned off, the input to the PB0 terminal changes from the low level to the high level, so that it can be determined that the power is not properly turned off. In this case, the writing to the RAM is permitted, and the normal state processing is performed after the NMI interrupt processing.

On the other hand, the voltage applied to the voltage input terminal VSD of the power supply voltage monitoring IC 3 starts dropping from 5 V, but when the voltage applied to the voltage input terminal VSD returns to the normal voltage of 12 V, the power supply voltage monitoring The voltage applied to the voltage input terminal VSD of the IC 3 starts to increase. When the power is not turned off, the voltage applied to the voltage input terminal VSD of the power supply voltage monitoring IC 3 does not drop to the 5 V threshold level. Therefore, the power supply voltage monitoring I
The output of the RESET terminal of C3 is maintained at a high level. Then, the voltage input terminal VS of the power supply voltage monitoring IC 3
The voltage applied to D further rises and the normal voltage 5V
Return to

The operation of the control device 1 in response to the above-described voltage drop signal 1 will be described with reference to a flowchart. FIG.
5 is a flowchart of an NMI interrupt process performed by the control device 1. As described above, the voltage drop signal 1 is output from the power supply voltage monitoring IC 2 when the power is turned off, when noise or a momentary voltage drop occurs, and the PB0 terminal and the XNMI terminal of the control device 1 are connected to the PB0 terminal and the XNMI terminal. Is entered,
In the control device 1, a low level is input to the XNMI terminal to generate an NMI interrupt, and the NMI interrupt process is started.

When the NMI interrupt process is started, the control device 1 saves the register. That is, the current state (contents) of the register is written in a predetermined area of the RAM (step S01). Next, a power-off flag is set (step S02), and writing to the RAM is prohibited (step S03).

Next, the control device 1 sets a count value (predetermined value) in a register as a loop counter (step S04). This predetermined value corresponds to time T1 in FIG. Next, the control device 1 determines whether or not the input state of the PB0 terminal is at a high level, that is, whether or not the input of the voltage drop signal 1 is off (step S0).
5).

If the input state of the PB0 terminal is not at the high level, the control device 1 decrements the count value set in the register by one (step S06), and determines whether or not the reduced count value is greater than zero. (Step S07).
When the count value is greater than 0, the control device 1 returns to step S05, and thereafter repeats steps S05, S06, and S07 until the register count value reaches 0. Therefore, the control device 1
Determines whether there is an input of the voltage drop signal 1 for a predetermined time (time corresponding to the time T1 in FIG. 2) from the point in time when writing to the RAM is prohibited.

As described above, in the case where the voltage drop is caused by the power cutoff, the voltage drop signal 1 from the power supply voltage monitoring IC 2
Is maintained, and the input of the PB0 terminal remains at the low level and does not change (see FIG. 2). Therefore, in the case of a voltage drop due to power-off, the determination result in step S05 is always false. Therefore, the count value of the register reaches 0. When the count value of the register reaches 0, the control device 1 determines that step S07 is false, performs an unconditional loop, and enters a standby state (becomes a pause state).
(Step S11).

After that, the voltage drop signal 2 is output from the power supply voltage monitoring IC 3 and the X
It is input to the SRST terminal. In the control device 1, XSRS
When a low level is input to the T terminal, a system reset is performed.

On the other hand, when the power supply is not cut off, that is, when the voltage drop is caused by the occurrence of noise or an instantaneous voltage drop, when the time T2 elapses from the time when the voltage drop signal 1 is input to the XNMI terminal, The voltage applied to the voltage input terminal VSD starts to rise and exceeds the 12V threshold level, and accordingly, the output of the voltage drop signal 1 from the power supply voltage monitoring IC 2 turns off and the input of the PB0 terminal turns to low level ( (See FIG. 3).

Therefore, if the voltage drop is caused by the occurrence of noise or an instantaneous voltage drop, the result of the determination in step S05 becomes true while steps S05, S06 and S07 are repeated. The control device 1 proceeds to step S08, permits writing to the RAM (step S08), and clears the power-off flag (step S0).
9), the contents of the register written in a predetermined area of the RAM are loaded into the register and restored (step S10),
Returning to the main routine (not shown), the normal state processing is performed.

As described above, the control device 1 according to the embodiment generates an NMI interrupt in response to a decrease in the power supply voltage, prohibits writing to the RAM in the NMI interrupt processing,
From this point, the input state of the PB0 terminal is monitored for a predetermined time. If the input of the PB0 terminal remains at the low level and does not change, the power is cut off and the control device 1 is suspended (H
(ALT) state while the input of the PB0 terminal changes from the low level to the high level, it is determined that the power is not turned off, that is, noise or an instantaneous voltage drop occurs, and RAM writing is permitted. In the case where noise or a momentary voltage drop occurs, the control device 1 for game control remains inactive even though the operating power supply has returned to normal. It is possible to avoid a problem that the player cannot play the game.

The type of the control device 1 in the embodiment is not limited as long as it is a control device provided in a pachinko game machine. That is, the control device 1 may be, for example, a main control device for game control that comprehensively controls a pachinko game, or may be a payout control device for performing payout control of a prize ball.

[0034]

According to the pachinko gaming machine of the present invention, when the power supply voltage drops, the presence or absence of the voltage drop signal is determined through the input port in the NMI interrupt corresponding to the input of the voltage drop signal to the NMI terminal. The monitoring is performed, and if the voltage drop signal is input for a predetermined period of time, the power supply is cut off and the control device is set to a halt state, while if the voltage drop signal is not input for a predetermined time, Performs the processing of the normal state of the control device after terminating the NMI interrupt as the power supply is not interrupted. Therefore, in the case of the occurrence of noise or a momentary voltage drop, despite the fact that the operating power supply has returned to normal, It is possible to avoid a problem that the control device 1 relating to the game control is stopped and cannot play a game.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a part of a control system provided in a pachinko gaming machine according to an embodiment.

FIG. 2 shows a PB0 terminal of the control device when the power is turned off;
Time chart showing the level states of the XNMI terminal and the XSRST terminal

FIG. 3 is a time chart showing the level states of the PB0 terminal, the XNMI terminal, and the XSRST terminal of the control device when noise or a momentary voltage drop occurs;

FIG. 4 is a flowchart of an NMI interrupt process performed by the control device according to the embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control apparatus 2 Power supply voltage monitoring IC 3 Power supply voltage monitoring IC L1 signal line L2 signal line L3 signal line L4 signal line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2C088 BC58 CA08 CA16 3E044 AA05 CC10 DB12 DD06

Claims (1)

[Claims] 1. A pachinko game machine comprising a control device and a power supply voltage monitoring circuit for outputting a voltage drop signal in response to a drop in power supply voltage, wherein an output terminal of the power supply voltage monitoring circuit is connected to an NMI terminal of the control device and A voltage drop signal connected to an input port and output from the power supply voltage monitoring circuit is input to an NMI terminal and an input terminal of the control device,
In the NMI interrupt in response to the input of the voltage drop signal to the NMI terminal, the control device monitors the presence or absence of the voltage drop signal through the input port, and the voltage drop signal is input for a predetermined time. While the power supply is turned off and the control device is put into a sleep state,
A pachinko machine, wherein when the voltage drop signal has not been input for a predetermined period of time, processing means for terminating the NMI interrupt and processing the control device in a normal state is provided, assuming that power is not cut off. Gaming machine.