JP2001203304A - Semiconductor device, electronic device and manufacturing method thereof - Google Patents

Semiconductor device, electronic device and manufacturing method thereof

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Publication number
JP2001203304A
JP2001203304A JP2000013952A JP2000013952A JP2001203304A JP 2001203304 A JP2001203304 A JP 2001203304A JP 2000013952 A JP2000013952 A JP 2000013952A JP 2000013952 A JP2000013952 A JP 2000013952A JP 2001203304 A JP2001203304 A JP 2001203304A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor chip
wafer
semiconductor
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000013952A
Other languages
Japanese (ja)
Inventor
Mamoru Onda
護 御田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2000013952A priority Critical patent/JP2001203304A/en
Publication of JP2001203304A publication Critical patent/JP2001203304A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To manufacture a WPP type semiconductor device at an inexpensive cost. SOLUTION: A semiconductor device, which a plurality of semiconductor chips made of outer electrodes and circuit elements are formed on a major forming surface of a wafer and which is obtained by separating from the wafer for each semiconductor chip, is provided with bumps formed using conductive material on each outer electrode.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置、電子
装置、及びそれらの製造方法に関し、特に、ＷＰＰ（Wa
fer Process Package ）型半導体装置と、そのＷＰＰ型
半導体装置を搭載した電子装置、及びそれらの製造方法
に適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, an electronic device, and a method of manufacturing the same, and more particularly, to a WPP (Wa).
The present invention relates to a technology effective when applied to a semiconductor device, an electronic device equipped with the WPP semiconductor device, and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】図９は、従来のＷＰＰ型半導体装置の構
成を説明するための図であり、図９（ａ）は立体図、図
９（ｂ）は図９（ａ）に示すＡ−Ａ線で切った断面図で
ある。2. Description of the Related Art FIG. 9 is a view for explaining the structure of a conventional WPP type semiconductor device. FIG. 9 (a) is a three-dimensional view, and FIG. 9 (b) is an A-type semiconductor device shown in FIG. It is sectional drawing cut | disconnected by the A line.

【０００３】従来のＷＰＰ型半導体装置は、図９に示す
ように、周辺配置された外部電極７０を有する半導体チ
ップ１０と、その半導体チップ１０上の外部電極７０の
形成部分以外に設けられた絶縁基材２０（ポリイミド）
の層と、その絶縁基材２０の層の上に形成された配線パ
ターン３０と、その配線パターン３０と半導体チップ１
０の外部電極７０とを電気的に接続するボンディングワ
イヤ６０と、配線パターン３０と電気的に接続されるソ
ルダボール４０と、外部電極７０と配線パターン３０と
それらの接続部分とを封止する封止樹脂５０とから構成
される。As shown in FIG. 9, a conventional WPP-type semiconductor device has a semiconductor chip 10 having external electrodes 70 arranged peripherally and an insulating layer provided on the semiconductor chip 10 except for the portion where the external electrodes 70 are formed. Base material 20 (polyimide)
Layer, a wiring pattern 30 formed on the insulating base 20 layer, the wiring pattern 30 and the semiconductor chip 1
Bonding wires 60 for electrically connecting the external electrodes 70 to the external electrodes 70; solder balls 40 for electrically connecting to the wiring patterns 30; and sealing for sealing the external electrodes 70 and the wiring patterns 30 and their connection parts. And a stopper resin 50.

【０００４】次に、上述した従来のＷＰＰ型半導体装置
の製造方法について説明する。Next, a method of manufacturing the above-mentioned conventional WPP type semiconductor device will be described.

【０００５】図１０、図１１は、従来のＷＰＰ型半導体
装置の製造方法を説明するための図である。FIGS. 10 and 11 are views for explaining a method of manufacturing a conventional WPP type semiconductor device.

【０００６】従来のＷＰＰ型半導体装置の製造は、図１
０（ａ）に示すように、まず、外部電極７０を含む回路
素子を形成したウエハ１０ａを用意し、図１０（ｂ）に
示すように、そのウエハ１０ａ上に絶縁基材２０（ポリ
イミド）の層をラミネートし、図１０（ｃ）に示すよう
に、ワイヤボンディングのためのボンディング窓２１を
ヒドラジンアルカリ水によるエッチング、または炭酸ガ
スレーザによる光分解により形成する。A conventional WPP type semiconductor device is manufactured by the method shown in FIG.
First, as shown in FIG. 10A, a wafer 10a on which circuit elements including the external electrodes 70 are formed is prepared, and as shown in FIG. 10B, an insulating base material 20 (polyimide) is formed on the wafer 10a. The layers are laminated, and as shown in FIG. 10C, a bonding window 21 for wire bonding is formed by etching with hydrazine alkaline water or photolysis with a carbon dioxide gas laser.

【０００７】そして、図１１（ａ）に示すように、絶縁
基材（ポリイミド）２０の層の上に銅箔３０ａを設け
る。なお、図１１は、その工程がわかりやすいようにウ
エハ１０ａから切り出した１つの半導体チップ１０を基
に示してある。Then, as shown in FIG. 11A, a copper foil 30a is provided on the layer of the insulating base material (polyimide) 20. FIG. 11 is based on one semiconductor chip 10 cut out from the wafer 10a so that the process can be easily understood.

【０００８】次に、銅箔３０ａにフォトレジストを貼り
付けてエッチングを行って、図１１（ｂ）に示すよう
に、配線パターン３０を形成し、図１１（ｃ）に示すよ
うに、外部電極７０と配線パターン３０とをボンディン
グワイヤ６０により接続する。Next, a photoresist is attached to the copper foil 30a and etching is performed to form a wiring pattern 30 as shown in FIG. 11B, and external electrodes are formed as shown in FIG. 70 and the wiring pattern 30 are connected by bonding wires 60.

【０００９】次に、図１１（ｄ）に示すように、配線パ
ターン３０上にソルダボール４０を形成し、図１１
（ｅ）に示すように、外部電極７０と配線パターン３０
とそれらの接続部分とを封止樹脂５０によって封止す
る。Next, as shown in FIG. 11D, a solder ball 40 is formed on the wiring pattern 30, and
As shown in (e), the external electrode 70 and the wiring pattern 30
And their connection parts are sealed with a sealing resin 50.

【００１０】[0010]

【発明が解決しようとする課題】上述した従来のＷＰＰ
型半導体装置では、図９に示すように、半導体チップ１
０上にポリイミド等の絶縁基材２０の層を形成して、そ
の上に配線を形成する再配線構造を有している。SUMMARY OF THE INVENTION The above-mentioned conventional WPP
In the semiconductor device, as shown in FIG.
A re-wiring structure is provided in which a layer of an insulating base material 20 such as polyimide is formed on the substrate 0 and a wiring is formed thereon.

【００１１】しかし、絶縁基材２０に用いられるポリイ
ミドは大変高価であり、ＷＰＰ型半導体装置が高価にな
ってしまうという問題点があった。However, the polyimide used for the insulating substrate 20 is very expensive, and there is a problem that the WPP type semiconductor device becomes expensive.

【００１２】また、図１０，図１１に示すように、従来
のＷＰＰ半導体装置では、配線を再配線したり、ワイヤ
ボンディングのためのボンディング窓２１を形成したり
しなければならず、その製造工程が多くなり、製造コス
トが増大するという問題点があった。Further, as shown in FIGS. 10 and 11, in the conventional WPP semiconductor device, the wiring must be redistributed and a bonding window 21 for wire bonding must be formed. And the production cost increases.

【００１３】本発明は、上記問題点を解決するために成
されたものであり、その目的は、ＷＰＰ型半導体装置を
安価に製造することが可能な技術を提供することにあ
る。The present invention has been made to solve the above problems, and an object of the present invention is to provide a technique capable of manufacturing a WPP type semiconductor device at low cost.

【００１４】[0014]

【課題を解決するための手段】本発明において開示され
る発明のうち、代表的なものの概要を簡単に説明すれ
ば、下記のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present invention, typical ones will be briefly described as follows.

【００１５】（１）ウエハの主形成面上に、外部電極及
び回路素子からなる半導体チップが複数組形成され、前
記各半導体チップ毎に前記ウエハから切り離して得られ
る半導体装置であって、導電材料で形成したバンプを前
記各外部電極上に設けたことを特徴とする。(1) A semiconductor device comprising a plurality of sets of semiconductor chips comprising external electrodes and circuit elements formed on a main forming surface of a wafer, wherein each of the semiconductor chips is separated from the wafer and comprises a conductive material. Characterized in that the bumps formed in (1) are provided on each of the external electrodes.

【００１６】（２）（１）の半導体装置において、前記
半導体チップとその半導体チップが接続される電子装置
の配線基板との間に生じる熱応力を緩衝する応力緩衝材
（エラストマ）、または未硬化の封止材を前記半導体チ
ップの主形成面に設けたことを特徴とする。(2) In the semiconductor device of (1), a stress buffer (elastomer) for buffering thermal stress generated between the semiconductor chip and a wiring board of an electronic device to which the semiconductor chip is connected, or uncured Is provided on the main formation surface of the semiconductor chip.

【００１７】（３）（２）の半導体装置において、前記
応力緩衝材は、ガラス転移温度がソルダボールの溶融温
度より小さく、１５０℃における弾性率が１００ＭＰａ
以下である樹脂であることを特徴とする。(3) In the semiconductor device of (2), the stress buffering material has a glass transition temperature lower than the melting temperature of the solder ball and an elastic modulus at 150 ° C. of 100 MPa.
It is characterized by being the following resin.

【００１８】（４）（２）または（３）のうちいずれか
１つの半導体装置において、前記バンプの先端面上にソ
ルダボールを設けたことを特徴とする。(4) The semiconductor device according to any one of (2) and (3), wherein a solder ball is provided on a tip end surface of the bump.

【００１９】（５）（１）乃至（４）のうちいずれか１
つの半導体装置を電子装置の配線基板に搭載したことを
特徴とする。(5) Any one of (1) to (4)
The semiconductor device is mounted on a wiring board of an electronic device.

【００２０】（６）ウエハの主形成面上に複数組形成さ
れた、外部電極及び回路素子からなる半導体チップと、
前記外部電極上に金で形成したバンプとからなり、前記
各半導体チップ毎に前記ウエハから切り離して得られる
半導体装置と、錫めっきされた配線パターンを有する配
線基板と、を備えた電子装置であって、前記バンプと前
記配線パターンとの接続は、金錫の第一共晶点の温度以
上で前記絶縁基材に影響を与える温度以下での加熱を行
い、第一共晶点の融点を利用した拡散反応による金錫接
合であることを特徴とする。(6) A plurality of sets of semiconductor chips, each including external electrodes and circuit elements, formed on the main formation surface of the wafer;
An electronic device comprising: a semiconductor device comprising bumps formed of gold on the external electrodes, obtained by separating each semiconductor chip from the wafer; and a wiring substrate having a tin-plated wiring pattern. The connection between the bump and the wiring pattern is performed by heating at a temperature equal to or higher than the temperature of the first eutectic point of gold tin and equal to or lower than the temperature affecting the insulating base material, and utilizing the melting point of the first eutectic point. It is a gold-tin junction by the diffusion reaction described above.

【００２１】（７）半導体装置の製造方法において、ウ
エハの主形成面上に外部電極及び回路素子からなる半導
体チップを複数組形成する第１の工程と、前記ウエハの
外部電極上に導電材料のバンプを形成する第２の工程
と、前記各半導体チップ毎に前記ウエハから切り離して
得られる第３の工程を有することを特徴とする。(7) In a method of manufacturing a semiconductor device, a first step of forming a plurality of sets of semiconductor chips each including an external electrode and a circuit element on a main formation surface of a wafer; and a step of forming a conductive material on the external electrodes of the wafer. The method includes a second step of forming a bump and a third step of obtaining each semiconductor chip by separating the semiconductor chip from the wafer.

【００２２】（８）（７）の半導体装置の製造方法にお
いて、前記第２の工程の後に、前記半導体チップとその
半導体チップが接続される電子装置の配線基板との間に
生じる熱応力を緩衝する応力緩衝材（エラストマ）、ま
たは未硬化の封止材を前記半導体チップの主形成面に設
ける工程を有することを特徴とする。(8) In the method of manufacturing a semiconductor device according to (7), after the second step, thermal stress generated between the semiconductor chip and a wiring board of an electronic device to which the semiconductor chip is connected is buffered. A step of providing a stress buffer (elastomer) or an uncured sealing material on the main formation surface of the semiconductor chip.

【００２３】（９）（８）の半導体装置の製造方法にお
いて、前記応力緩衝材（エラストマ）、または未硬化の
封止材を前記半導体チップの主形成面に設ける工程の後
に、前記バンプの先端にソルダボールを形成する工程を
有することを特徴とする。(9) In the method of manufacturing a semiconductor device according to (8), after the step of providing the stress buffering material (elastomer) or the uncured sealing material on the main forming surface of the semiconductor chip, the tip of the bump may be formed. And a step of forming a solder ball.

【００２４】（１０）（９）の半導体装置の製造方法に
おいて、前記ソルダボールを形成する工程は、１ウエハ
単位でソルダペーストを前記バンプの先端面上に印刷
し、その印刷されたウエハに対してリフロー処理を行
い、前記バンプの先端にソルダボールを形成することを
特徴とする。(10) In the method of manufacturing a semiconductor device according to (9), the step of forming the solder ball is performed by printing a solder paste on the tip surface of the bump in units of one wafer, and applying the solder paste to the printed wafer. A reflow process to form a solder ball at the tip of the bump.

【００２５】[0025]

【発明の実施の形態】図１は、本実施形態のＷＰＰ型半
導体装置の構成を説明するための図であり、図１（ａ）
は立体図、図１（ｂ）は図１（ａ）に示すＡ−Ａ線で切
った断面図である。FIG. 1 is a diagram for explaining a configuration of a WPP type semiconductor device according to the present embodiment.
1 is a three-dimensional view, and FIG. 1B is a cross-sectional view taken along line AA shown in FIG.

【００２６】本実施形態のＷＰＰ型半導体装置１００
は、図１に示すように、主形成面に回路素子と、その周
辺に配置された外部電極７０とが形成された半導体チッ
プ１０と、その外部電極７０上に形成される金線ワイヤ
を用いて製造されるバンプ（以下、金ワイヤバンプ８０
と記す）と、から構成される。The WPP type semiconductor device 100 of the present embodiment
As shown in FIG. 1, a semiconductor chip 10 having a circuit element formed on a main forming surface and an external electrode 70 disposed around the semiconductor element 10 and a gold wire formed on the external electrode 70 are used. (Hereinafter referred to as gold wire bump 80)
).

【００２７】この金ワイヤバンプ８０は、冷熱温度サイ
クルにより半導体チップ１０とそれを接続する他の電子
装置の配線基板との間に生じる熱応力を緩衝する応力緩
衝の役割を果たす。The gold wire bumps 80 play a role of buffering a thermal stress generated between the semiconductor chip 10 and a wiring board of another electronic device connecting the semiconductor chip 10 by a thermal cycle.

【００２８】図２は、本実施形態の金ワイヤバンプ８０
の構成を説明するための図であり、図２（ａ）は図１
（ａ）に示す１つの金ワイヤバンプ８０を上から見た俯
瞰図であり、図２（ｂ）は図１（ｂ）に示す金ワイヤバ
ンプ８０の拡大図である。FIG. 2 shows a gold wire bump 80 according to this embodiment.
FIG. 2A is a diagram for explaining the configuration of FIG.
FIG. 2A is an overhead view of one gold wire bump 80 shown in FIG. 2A, and FIG. 2B is an enlarged view of the gold wire bump 80 shown in FIG.

【００２９】金ワイヤバンプ８０は、図２に示すよう
に、アルミで形成された約５０μｍ四方の外部電極７０
上に、ワイヤボンダーで金線のボンディングワイヤを接
合し、そのワイヤを所定長でカットすることによって形
成する。また、金めっきまたはニッケルコア上の金めっ
きによりバンプを形成してもよい。As shown in FIG. 2, a gold wire bump 80 is formed of an external electrode 70 of about 50 μm square made of aluminum.
A bonding wire of a gold wire is bonded thereon with a wire bonder, and the wire is cut by a predetermined length. Alternatively, the bumps may be formed by gold plating or gold plating on a nickel core.

【００３０】図２に示すように、半導体チップ１０の外
部電極７０以外には、ＰＩＱ（ポリイミドコート不動態
化膜）、またはＰＩＸ（感光性ポリイミドコート不動態
化膜）等の保護膜９０が回路素子形成面を保護するため
に設けられている（図１には図示せず）。金ワイヤバン
プ８０は、図２に示すように、外部電極７０と接続部分
は４０〜５０μｍ径であり、先端部分は約３０μｍ径で
ある。As shown in FIG. 2, a protective film 90 such as PIQ (polyimide passivation film) or PIX (photosensitive polyimide coat passivation film) is provided on the circuit other than the external electrodes 70 of the semiconductor chip 10. It is provided to protect the element formation surface (not shown in FIG. 1). As shown in FIG. 2, the gold wire bump 80 has a diameter of 40 to 50 μm at a portion connected to the external electrode 70 and a diameter of about 30 μm at a tip portion.

【００３１】なお、本発明に用いられるバンプは、金ワ
イヤバンプ８０に限定されるものではなく、例えばこの
金ワイヤバンプ８０の代わりに、凸状にめっき形成した
バンプを用いても構わない。さらに、バンプの形状も、
先端部分が応力緩衝材等を突き破ることが可能な細さで
あればよく、その場合、凸状でなくても構わない。The bumps used in the present invention are not limited to the gold wire bumps 80. For example, bumps plated in a convex shape may be used instead of the gold wire bumps 80. Furthermore, the shape of the bump
It is sufficient if the tip portion is thin enough to break through the stress buffering material or the like, and in that case, it does not have to be convex.

【００３２】次に、上述した本実施形態のＷＰＰ型半導
体装置１００の製造方法について説明する。図３は、本
実施形態のＷＰＰ型半導体装置１００の製造方法を説明
するための図である。Next, a method of manufacturing the above-described WPP type semiconductor device 100 of the present embodiment will be described. FIG. 3 is a diagram for explaining a method of manufacturing the WPP type semiconductor device 100 of the present embodiment.

【００３３】本実施形態のＷＰＰ型半導体装置の製造
は、図３（ａ）に示すように、まず、ウエハ１０ａに外
部電極７０を含む回路素子を形成し、図３（ｂ）に示す
ように、その外部電極７０上にワイヤボンダーによって
金線のボンディングワイヤを接合して金ワイヤバンプ８
０を形成し、図３（ｃ）に示すように、各半導体チップ
１０を細断して図１に示すＷＰＰ型半導体装置１００を
得る。In manufacturing the WPP type semiconductor device of this embodiment, first, as shown in FIG. 3A, circuit elements including the external electrodes 70 are formed on the wafer 10a, and as shown in FIG. Bonding a gold bonding wire to the external electrode 70 with a wire bonder to form a gold wire bump 8
0 is formed, and as shown in FIG. 3C, each semiconductor chip 10 is shredded to obtain the WPP type semiconductor device 100 shown in FIG.

【００３４】このように、約５０μｍ四方の外部電極
（ランド）７０には従来の０．３mm径の半田バンプは直
接搭載できないが、３０〜５０μｍ径の金ワイヤバンプ
８０は直接搭載が可能になる。As described above, the conventional solder bump having a diameter of 0.3 mm cannot be directly mounted on the external electrode (land) 70 of about 50 μm square, but the gold wire bump 80 having a diameter of 30 to 50 μm can be directly mounted.

【００３５】次に、電子装置の一例であるメモリモジュ
ールに本実施形態のＷＰＰ型半導体装置１００を搭載し
た場合について説明する。Next, a case where the WPP type semiconductor device 100 of this embodiment is mounted on a memory module which is an example of an electronic device will be described.

【００３６】図４は、本実施形態のＷＰＰ型半導体装置
１００を搭載したメモリモジュールの構成を説明するた
めの図である。FIG. 4 is a diagram for explaining a configuration of a memory module on which the WPP type semiconductor device 100 of the present embodiment is mounted.

【００３７】図４に示すように、メモリモジュール配線
基板２０１の配線パターン２０２の接続部分を錫めっき
して、金ワイヤバンプ８０との金錫の拡散反応によって
接続が行われ、本実施形態のＷＰＰ型半導体装置１００
はメモリモジュール２００に搭載される。なお、図示し
ていないが、配線パターン２０２の接続部分以外はソル
ダレジスト（図示せず）をコーティングしてある。As shown in FIG. 4, the connection portion of the wiring pattern 202 of the memory module wiring substrate 201 is tin-plated, and the connection is made by the diffusion reaction of gold and tin with the gold wire bump 80. Semiconductor device 100
Are mounted on the memory module 200. Although not shown, a portion other than the connection portion of the wiring pattern 202 is coated with a solder resist (not shown).

【００３８】この金錫接続部の接合層は、接合界面の金
と錫の反応溶融層（高融点層）とそこからはみ出した部
分（フィレット）とからなる。そのフィレットは、第１
共晶点（融点２１７℃）の組成を中心とした、金５〜２
０重量％（残り錫）の組成からなり、反応溶融層（高融
点層）は金１０〜４０重量％（残り錫）の組成からな
る。The bonding layer at the gold-tin connection portion is composed of a reaction-melted layer of gold and tin (high-melting point layer) at the bonding interface and a portion (fillet) protruding therefrom. The fillet is the first
Gold 5 to 2 centered on eutectic point (melting point 217 ° C) composition
The reaction molten layer (high melting point layer) has a composition of 0% by weight (remaining tin) and a composition of 10 to 40% by weight of gold (remaining tin).

【００３９】また、この金錫接続は、上述のように接合
界面がＡｕ１０〜４０重量％−Ｓｎ６０〜９０重量％に
する第一共晶点における接続を行うと、低温で接続強度
が大きくなる。As described above, when the connection at the first eutectic point where the bonding interface is Au 10 to 40% by weight-Sn 60 to 90% by weight is performed as described above, the connection strength increases at a low temperature.

【００４０】なお、この金錫接続は、上述したように第
一共晶点における接続が接合強度も大きいことから理想
的ではあるが、本発明は接合界面が必ずしもこの成分に
限定されるものではなく、金錫の第一共晶点の温度以上
で配線基板に影響を与える温度以下での加熱を行い、第
一共晶点の融点を利用した接合であれば、Ａｕ１０〜４
０重量％−Ｓｎ６０〜９０重量％以外の成分であっても
よい。Although the gold-tin connection is ideal because the connection at the first eutectic point has a large bonding strength as described above, the present invention does not limit the bonding interface to this component. However, if heating is performed at a temperature higher than the temperature of the first eutectic point of gold tin and lower than the temperature that affects the wiring substrate, and the bonding is performed using the melting point of the first eutectic point, Au10-4
It may be a component other than 0% by weight-Sn 60 to 90% by weight.

【００４１】以上、説明してきたように、本実施形態の
ＷＰＰ型半導体装置１００では、外部電極７０上に他の
電子装置の配線基板と接続可能な金ワイヤバンプ８０を
設けることで、他の電子装置の配線基板との接続のため
の再配線をする必要がなくなるため、絶縁基材２０であ
る高価なポリイミドを設けなくてもよく、且つそのポリ
イミドの加工工程も必要なくなるので、ＷＰＰ型半導体
装置を安価に製造することが可能となる。As described above, in the WPP type semiconductor device 100 of the present embodiment, by providing the gold wire bump 80 connectable to the wiring board of another electronic device on the external electrode 70, Since it is not necessary to perform rewiring for connection with the wiring substrate, it is not necessary to provide expensive polyimide which is the insulating base material 20, and the processing step of the polyimide is not required. It can be manufactured at low cost.

【００４２】また、従来のワイヤボンダーを用いて金ワ
イヤバンプを形成できるため、特別に設備を設ける必要
がない。Further, since a gold wire bump can be formed using a conventional wire bonder, no special equipment is required.

【００４３】また、ビッカース硬度がＨｖ６０〜８０程
度の軟質材である金を金ワイヤバンプ８０として設ける
ことで、その金ワイヤバンプ８０が半導体チップ１０と
その接続先である他の電子装置の配線基板との熱膨張係
数の差で生じる熱応力を緩衝するので、冷熱温度サイク
ルにおいて接続部分の信頼性が向上する。Further, by providing gold, which is a soft material having a Vickers hardness of about Hv 60 to 80, as the gold wire bump 80, the gold wire bump 80 can be connected to the semiconductor chip 10 and a wiring board of another electronic device to which the semiconductor chip 10 is connected. Since the thermal stress generated due to the difference in the thermal expansion coefficient is buffered, the reliability of the connection portion in the thermal cycle is improved.

【００４４】なお、０．３mm径のソルダバンプとは違っ
て金ワイヤバンプは、径が０．０５mmと一桁小さいの
で、静電容量が大きくなることにより生じるノイズの影
響が小さいので、半導体チップ１０のアクティブライン
（回路素子形成面）上にも金ワイヤバンプ８０を形成可
能である。Unlike the solder bumps having a diameter of 0.3 mm, the gold wire bumps have a diameter of 0.05 mm, which is one digit smaller, so that the influence of noise caused by an increase in capacitance is small. Gold wire bumps 80 can also be formed on active lines (circuit element formation surface).

【００４５】このため、本実施形態では周辺バンプを有
するＷＰＰ型半導体装置１００について説明してきた
が、エリアバンプを有するＷＰＰ型半導体装置にも適応
可能である。For this reason, in the present embodiment, the WPP type semiconductor device 100 having peripheral bumps has been described, but the present invention is also applicable to a WPP type semiconductor device having area bumps.

【００４６】（実施例１）本実施例１では、上述した実
施形態のＷＰＰ型半導体装置１００に、半導体チップ１
０と他の電子装置の配線基板との間に生じる熱応力を緩
衝する熱応力緩衝材（エラストマ）を設けた場合につい
て説明する。Example 1 In Example 1, a semiconductor chip 1 was added to the WPP type semiconductor device 100 of the above-described embodiment.
A case will be described in which a thermal stress buffer (elastomer) for buffering thermal stress generated between the zero and a wiring board of another electronic device is provided.

【００４７】図５は、本実施例１のＷＰＰ型半導体装置
の構成を説明するための図であり、図５（ａ）は立体
図、図５（ｂ）は図５（ａ）に示すＡ−Ａ線で切った断
面図である。FIGS. 5A and 5B are diagrams for explaining the configuration of the WPP type semiconductor device of the first embodiment. FIG. 5A is a three-dimensional view, and FIG. It is sectional drawing cut | disconnected by the -A line.

【００４８】本実施例１のＷＰＰ型半導体装置１００ａ
は、図５に示すように、主形成面に回路素子と、その周
辺に配置された外部電極７０とが形成された半導体チッ
プ１０と、その外部電極７０上に形成される金ワイヤバ
ンプ８０と、その金ワイヤバンプ８０の先端面８１が少
し突出するように半導体チップ１０の主形成面上に設け
られた応力緩衝材（エラストマ）１１０と、から構成さ
れる。The WPP type semiconductor device 100a of the first embodiment
As shown in FIG. 5, a semiconductor chip 10 in which a circuit element is formed on a main forming surface and an external electrode 70 arranged around the semiconductor chip 10, a gold wire bump 80 formed on the external electrode 70, And a stress buffering material (elastomer) 110 provided on the main forming surface of the semiconductor chip 10 so that the distal end surface 81 of the gold wire bump 80 slightly projects.

【００４９】このエラストマ１１０は、金ワイヤバンプ
８０だけでは緩衝しきれなかった熱応力を面全体で緩衝
するものであり、冷熱温度サイクルにおける接続部分の
信頼性をさらに向上させるものである。The elastomer 110 buffers the thermal stress on the entire surface which could not be buffered by the gold wire bumps 80 alone, and further improves the reliability of the connection portion in the cooling / heating temperature cycle.

【００５０】このエラストマ１１０としては、例えば、
ガラス転移温度（３７ｍａｓｓ％Ｐｂ−Ｓｎのソルダボ
ールの半田溶融温度１８０℃より小さい）を有するエポ
キシ樹脂等を用いる。また、例えば、未硬化の封止樹脂
や１５０℃における弾性率が１００ＭＰａ以下である樹
脂等を用いることも可能である。As the elastomer 110, for example,
An epoxy resin or the like having a glass transition temperature (less than the solder melting temperature of a solder ball of 37 mass% Pb-Sn of 180 ° C.) is used. Further, for example, an uncured sealing resin or a resin having an elastic modulus at 150 ° C. of 100 MPa or less can be used.

【００５１】本実施例１のＷＰＰ型半導体装置の製造１
００ａは、上記実施形態のＷＰＰ型半導体装置１００の
工程にエラストマ１１０を形成する工程（貼り付ける工
程、または塗布する工程）を追加しただけである。つま
り、図３（ｃ）に示す細断の前に半導体チップ１０にエ
ラストマ１１０を形成する工程を有するだけである。こ
のエラストマ１１０は金ワイヤバンプ８０の高さと同じ
厚さを有するものを用いる。その形成工程は、エラスト
マ１１０の先端面８１が露出するように行われる。貼り
付け工程では、エラストマ１１０のテープを金ワイヤバ
ンプ８０がエラストマ１１０を突き破るように貼り付け
る。Manufacturing 1 of WPP type semiconductor device of the first embodiment
00a is obtained by simply adding a step of forming the elastomer 110 (adhering step or applying step) to the steps of the WPP type semiconductor device 100 of the above embodiment. That is, only the step of forming the elastomer 110 on the semiconductor chip 10 before the shredding shown in FIG. The elastomer 110 having the same thickness as the height of the gold wire bump 80 is used. The forming process is performed so that the tip surface 81 of the elastomer 110 is exposed. In the attaching step, the tape of the elastomer 110 is attached so that the gold wire bumps 80 penetrate the elastomer 110.

【００５２】なお、金ワイヤバンプ８０の先端面８１
は、必ずしもこのエラストマ形成時にエラストマ１１０
から出るようにしなくても良い場合がある。これは、エ
ラストマ１１０の中に金ワイヤバンプ８０が包み込まれ
ている状態であっても、他の電子装置との接続時にエラ
ストマ１１０がガラス転移温度以上に加熱されて溶融す
ることで、金ワイヤバンプ８０の先端面８１がエラスト
マ１１０から露出するからである。The tip surface 81 of the gold wire bump 80
Is not necessarily required when forming the elastomer.
Sometimes you do not have to leave. This is because even when the gold wire bumps 80 are wrapped in the elastomer 110, the elastomer 110 is heated to a glass transition temperature or higher and melted at the time of connection with another electronic device, so that the gold wire bumps 80 are formed. This is because the tip surface 81 is exposed from the elastomer 110.

【００５３】次に、電子装置に本実施例１のＷＰＰ型半
導体装置１００を搭載した場合について説明する。な
お、本実施例１のＷＰＰ型半導体装置１００ａは、上記
実施形態と同様にメモリモジュール等に搭載されるが、
ここではその接続部分について説明する。Next, the case where the WPP type semiconductor device 100 of the first embodiment is mounted on an electronic device will be described. Note that the WPP type semiconductor device 100a according to the first embodiment is mounted on a memory module or the like as in the above-described embodiment.
Here, the connection portion will be described.

【００５４】図６は、本実施例１のＷＰＰ型半導体装置
１００ａの電子装置への搭載を説明するための図であ
る。FIG. 6 is a diagram for explaining mounting of the WPP type semiconductor device 100a of the first embodiment on an electronic device.

【００５５】図６に示すように、本実施例１のＷＰＰ型
半導体装置１００ａの電子装置の配線基板２０１への搭
載は、メモリモジュール配線基板２０１の配線パターン
２０２の接続部分を錫めっきして、金ワイヤバンプ８０
との金錫の拡散反応によって行われる。この金錫接続
は、実施形態と同様に行われる。As shown in FIG. 6, when mounting the WPP type semiconductor device 100a of the first embodiment on the wiring board 201 of the electronic device, the connection portion of the wiring pattern 202 of the memory module wiring board 201 is plated with tin. Gold wire bump 80
The reaction is carried out by a diffusion reaction of gold and tin. This gold-tin connection is performed in the same manner as in the embodiment.

【００５６】その際に、エラストマ１１０が溶融して配
線基板２０１に接着し、金ワイヤバンプ８０と配線パタ
ーン２０２との接続部分を封止する。すなわち、ＷＰＰ
型半導体装置１００ａの搭載と、その接続部分を封止す
るアンダフィル工程は同時に行われることになる。At this time, the elastomer 110 is melted and adhered to the wiring board 201, and the connection between the gold wire bump 80 and the wiring pattern 202 is sealed. That is, WPP
The mounting of the semiconductor device 100a and the underfill step of sealing the connection portion are performed simultaneously.

【００５７】したがって、説明してきたように、本実施
例１のＷＰＰ型半導体装置１００ａでは、金ワイヤバン
プ８０を包み込む（先端部分８１が少し突出する）よう
に半導体チップ１０上にエラストマ１１０を設けること
により、冷熱温度サイクルにおける接続部分の信頼性を
さらに向上させることが可能である。また、他の電子装
置に搭載する際の接続部分の封止をも同時に行うことが
可能になる。Therefore, as described above, in the WPP type semiconductor device 100a of the first embodiment, the elastomer 110 is provided on the semiconductor chip 10 so as to enclose the gold wire bump 80 (the tip portion 81 projects slightly). Further, it is possible to further improve the reliability of the connection part in the cooling / heating temperature cycle. In addition, it is possible to simultaneously seal the connection portion when mounting on another electronic device.

【００５８】なお、本実施例１では、周辺バンプを有す
るＷＰＰ型半導体装置１００ａについて説明してきた
が、上記実施形態と同様にエリアバンプを有するＷＰＰ
型半導体装置にも適応可能である。In the first embodiment, the description has been given of the WPP type semiconductor device 100a having the peripheral bumps.
The present invention is also applicable to a type semiconductor device.

【００５９】（実施例２）本実施例２では、本実施例１
のＷＰＰ型半導体装置の金ワイヤバンプ８０の先端部分
８１にソルダボールを搭載したＷＰＰ型半導体装置につ
いて説明する。(Embodiment 2) In Embodiment 2, Embodiment 1
A WPP type semiconductor device in which a solder ball is mounted on a tip portion 81 of a gold wire bump 80 of the WPP type semiconductor device will be described.

【００６０】図７は、本実施例２のＷＰＰ型半導体装置
１００ｂの構成を示す図であり、図７（ａ）は立体図、
図７（ｂ）は図７（ａ）に示すＡ−Ａ線で切った断面図
である。FIG. 7 is a diagram showing a configuration of a WPP type semiconductor device 100b according to the second embodiment. FIG.
FIG. 7B is a cross-sectional view taken along the line AA shown in FIG.

【００６１】図７に示すように、本実施例２のＷＰＰ型
半導体装置１００ａは、主形成面に回路素子とその周辺
に配置された外部電極７０とが形成された半導体チップ
１０と、その外部電極７０上に形成される金ワイヤバン
プ８０と、その金ワイヤバンプ８０の先端面８１が少し
突出するように半導体チップ１０の主形成面上に設けら
れた応力緩衝材（エラストマ）１１０と、金ワイヤバン
プ８０の先端面８１上に設けられたソルダボール１２０
と、から構成される。As shown in FIG. 7, the WPP type semiconductor device 100a of the second embodiment has a semiconductor chip 10 in which a circuit element and an external electrode 70 disposed around the circuit element are formed on the main formation surface, A gold wire bump 80 formed on the electrode 70; a stress buffer (elastomer) 110 provided on the main forming surface of the semiconductor chip 10 so that a tip surface 81 of the gold wire bump 80 slightly projects; Solder ball 120 provided on the tip surface 81 of the
And

【００６２】次に、本実施例２のＷＰＰ型半導体装置１
００ｂの製造方法について説明する。Next, the WPP type semiconductor device 1 of the second embodiment
00b will be described.

【００６３】この本実施例２のＷＰＰ型半導体装置１０
０ｂでは、ソルダボール１２０を搭載する前までの工程
は実施例１と同様であるので、ここではソルダボール形
成工程についてのみ説明する。The WPP type semiconductor device 10 of the second embodiment
In step 0b, the steps before mounting the solder balls 120 are the same as those in the first embodiment, and therefore, only the solder ball forming steps will be described here.

【００６４】図８は、本実施例２のＷＰＰ型半導体装置
１００ｂのソルダボール形成工程を説明するための図で
ある。FIG. 8 is a view for explaining a solder ball forming step of the WPP type semiconductor device 100b of the second embodiment.

【００６５】本実施例２のＷＰＰ型半導体装置１００ｂ
のソルダボール形成工程は、図８（ａ）に示すように、
まず、印刷ツール（スキージー）１３０により、１ウエ
ハ単位でソルダペースト１２１を金ワイヤバンプ８０の
先端面８１上に印刷し（印刷マスクについては省略して
ある）、その印刷されたウエハ１０ａにリフロー（２５
０℃で１０秒）を行うと、図８（ｃ）に示すように、金
ワイヤバンプ８０の先端部分８１にソルダボール１２０
（約０．１μｍ径）が形成される。これを１チップ毎に
細断して図７に示す本実施例２のＷＰＰ型半導体装置１
００ｂを得る。The WPP type semiconductor device 100b of the second embodiment
In the solder ball forming step of FIG.
First, the solder paste 121 is printed on the front end surface 81 of the gold wire bump 80 in units of one wafer by a printing tool (squeegee) 130 (the print mask is omitted), and reflow (25) is performed on the printed wafer 10a.
8C, a solder ball 120 is attached to the tip 81 of the gold wire bump 80, as shown in FIG.
(Approximately 0.1 μm diameter) is formed. The WPP type semiconductor device 1 according to the second embodiment shown in FIG.
00b.

【００６６】ソルダペースト１２１はリフロー時に溶融
してボール状になり、エラストマ１１０より接合性が高
い金ワイヤバンプ８０の先端面８１と接合してソルダボ
ール１２０として形成される。The solder paste 121 is melted at the time of reflow to be in a ball shape, and is joined to the front end surface 81 of the gold wire bump 80 having a higher bonding property than the elastomer 110 to form a solder ball 120.

【００６７】このように、金ワイヤバンプ８０の先端面
８１にソルダボール１２０を形成することによって、他
の電子装置の配線基板へのソルダボール１２０による接
続が可能になる。As described above, by forming the solder ball 120 on the tip end surface 81 of the gold wire bump 80, connection to the wiring board of another electronic device by the solder ball 120 becomes possible.

【００６８】なお、ソルダボール１２０は静電容量が大
きくなり、ノイズが発生するため、半導体チップ１０の
アクティブライン（回路素子形成面）上には直接形成す
ることができない。このため、本実施例２では、エラス
トマ１１０が低誘電率を示すものであれば、エリアバン
プ型のＷＰＰ半導体装置を形成することが可能である
が、エラストマ１１０が低誘電率を示すものでなけれ
ば、周辺バンプ型のＷＰＰ型半導体装置に限られる。The solder ball 120 cannot be formed directly on the active line (circuit element forming surface) of the semiconductor chip 10 because the capacitance becomes large and noise is generated. Therefore, in the second embodiment, an area bump type WPP semiconductor device can be formed as long as the elastomer 110 has a low dielectric constant. However, the elastomer 110 must have a low dielectric constant. For example, it is limited to a peripheral bump type WPP type semiconductor device.

【００６９】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

【００７０】[0070]

【発明の効果】本発明において開示される発明のうち代
表的なものによって得られる効果を簡単に説明すれば、
下記のとおりである。The effects obtained by the representative inventions among the inventions disclosed in the present invention will be briefly described.
It is as follows.

【００７１】外部電極上に他の電子装置の配線基板と接
続可能な金ワイヤバンプを設けることで、他の電子装置
の配線基板との接続のための再配線をする必要がなくな
るため、絶縁基材である高価なポリイミドを設けなくて
もよく、且つそのポリイミドの加工工程も必要なくなる
ので、ＷＰＰ型半導体装置を安価に製造することが可能
となる。By providing gold wire bumps on external electrodes that can be connected to a wiring board of another electronic device, it is not necessary to perform rewiring for connection to a wiring board of another electronic device. It is not necessary to provide expensive polyimide, and the processing step of the polyimide is not required, so that the WPP type semiconductor device can be manufactured at low cost.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施形態にかかるＷＰＰ型半導体装
置の構成を説明するための図である。FIG. 1 is a diagram illustrating a configuration of a WPP type semiconductor device according to an embodiment of the present invention.

【図２】本実施形態の金ワイヤバンプ８０の構成を説明
するための図である。FIG. 2 is a diagram for explaining a configuration of a gold wire bump 80 of the present embodiment.

【図３】本実施形態のＷＰＰ型半導体装置１００の製造
方法を説明するための図である。FIG. 3 is a diagram illustrating a method of manufacturing the WPP type semiconductor device 100 according to the embodiment.

【図４】本実施形態のＷＰＰ型半導体装置１００を搭載
したメモリモジュール２００の構成を説明するための図
である。FIG. 4 is a diagram illustrating a configuration of a memory module 200 including the WPP type semiconductor device 100 according to the embodiment.

【図５】本実施例１のＷＰＰ型半導体装置１００ａの構
成を説明するための図である。FIG. 5 is a diagram illustrating a configuration of a WPP type semiconductor device 100a according to the first embodiment.

【図６】本実施例１のＷＰＰ型半導体装置１００ａの電
子装置への搭載を説明するための図である。FIG. 6 is a diagram for explaining mounting of the WPP type semiconductor device 100a of the first embodiment on an electronic device.

【図７】本実施例２のＷＰＰ型半導体装置１００ｂの構
成を示す図である。FIG. 7 is a diagram illustrating a configuration of a WPP type semiconductor device 100b according to a second embodiment.

【図８】本実施例２のＷＰＰ型半導体装置１００ｂのソ
ルダボール形成工程を説明するための図である。FIG. 8 is a diagram for explaining a solder ball forming step of the WPP type semiconductor device 100b according to the second embodiment.

【図９】従来のＷＰＰ型半導体装置の構成を説明するた
めの図である。FIG. 9 is a diagram illustrating a configuration of a conventional WPP type semiconductor device.

【図１０】従来のＷＰＰ型半導体装置の製造方法を説明
するための図である。FIG. 10 is a view illustrating a method of manufacturing a conventional WPP semiconductor device.

【図１１】従来のＷＰＰ型半導体装置の製造方法を説明
するための図である。FIG. 11 is a view illustrating a method of manufacturing a conventional WPP type semiconductor device.

【符号の説明】[Explanation of symbols]

１０ 半導体チップ ２０ 絶縁基材 ３０ 配線パターン ４０、１２０ ソルダボール ５０ 封止樹脂 ６０ ボンディングワイヤ ７０ 外部電極 ８０ 金ワイヤバンプ ９０ ソルダレジスト １００ ＷＰＰ型半導体装置 １１０ エラストマ ２００ メモリモジュール ２０１ メモリモジュールの配線基板 ２０２ メモリモジュールの配線パターン DESCRIPTION OF SYMBOLS 10 Semiconductor chip 20 Insulating base material 30 Wiring pattern 40, 120 Solder ball 50 Sealing resin 60 Bonding wire 70 External electrode 80 Gold wire bump 90 Solder resist 100 WPP type semiconductor device 110 Elastomer 200 Memory module 201 Memory module wiring board 202 Memory module Wiring pattern

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】ウエハの主形成面上に、外部電極及び回路
素子からなる半導体チップが複数組形成され、前記各半
導体チップ毎に前記ウエハから切り離して得られる半導
体装置であって、 導電材料で形成したバンプを前記各外部電極上に設けた
ことを特徴とする半導体装置。1. A semiconductor device comprising a plurality of sets of semiconductor chips each comprising an external electrode and a circuit element formed on a main forming surface of a wafer, wherein each of the semiconductor chips is obtained by separating the semiconductor chips from the wafer. A semiconductor device, wherein the formed bump is provided on each of the external electrodes. 【請求項２】前記請求項１に記載の半導体装置におい
て、 前記半導体チップとその半導体チップが接続される電子
装置の配線基板との間に生じる熱応力を緩衝する応力緩
衝材（エラストマ）、または未硬化の封止材を前記半導
体チップの主形成面に設けたことを特徴とする半導体装
置。2. The semiconductor device according to claim 1, wherein a stress buffer (elastomer) for buffering a thermal stress generated between the semiconductor chip and a wiring board of an electronic device to which the semiconductor chip is connected, or A semiconductor device, wherein an uncured sealing material is provided on a main forming surface of the semiconductor chip. 【請求項３】前記請求項２に記載の半導体装置におい
て、 前記応力緩衝材は、ガラス転移温度がソルダボールの溶
融温度より小さく、１５０℃における弾性率が１００Ｍ
Ｐａ以下の樹脂であることを特徴とする半導体装置。3. The semiconductor device according to claim 2, wherein the stress buffer has a glass transition temperature lower than a melting temperature of the solder ball and an elastic modulus at 150 ° C. of 100 M.
A semiconductor device comprising a resin of Pa or less. 【請求項４】前記請求項２または３のうちいずれか１項
に記載の半導体装置において、 前記バンプの先端面上にソルダボールを設けたことを特
徴とする半導体装置。4. The semiconductor device according to claim 2, wherein a solder ball is provided on a tip end surface of said bump. 【請求項５】前記請求項１乃至４のうちいずれか１項に
記載の半導体装置を配線基板に搭載したことを特徴とす
る電子装置。5. An electronic device comprising the semiconductor device according to claim 1 mounted on a wiring board. 【請求項６】ウエハの主形成面上に複数組形成された、
外部電極及び回路素子からなる半導体チップと、前記外
部電極上に金で形成したバンプとからなり、前記各半導
体チップ毎に前記ウエハから切り離して得られる半導体
装置と、錫めっきされた配線パターンを有する配線基板
と、を備えた電子装置であって、 前記バンプと前記配線パターンとの接続は、金錫の第一
共晶点の温度以上で前記絶縁基材に影響を与える温度以
下での加熱を行い、第一共晶点の融点を利用した拡散反
応による金錫接合であることを特徴とする電子装置。6. A plurality of sets formed on a main forming surface of a wafer.
A semiconductor device comprising a semiconductor chip including external electrodes and circuit elements, and a bump formed of gold on the external electrode, and having a semiconductor device obtained by separating the semiconductor chip from the wafer for each semiconductor chip, and a tin-plated wiring pattern; A wiring board, wherein the connection between the bump and the wiring pattern is performed by heating at a temperature equal to or higher than the temperature of the first eutectic point of gold tin and equal to or lower than the temperature that affects the insulating base material. An electronic device, comprising: a gold-tin junction by a diffusion reaction using a melting point of a first eutectic point. 【請求項７】ウエハの主形成面上に外部電極及び回路素
子からなる半導体チップを複数組形成する第１の工程
と、前記ウエハの外部電極上に導電材料のバンプを形成
する第２の工程と、前記各半導体チップ毎に前記ウエハ
から切り離して得られる第３の工程を有することを特徴
とする半導体装置の製造方法。7. A first step of forming a plurality of sets of semiconductor chips comprising external electrodes and circuit elements on a main forming surface of a wafer, and a second step of forming bumps of a conductive material on the external electrodes of the wafer. And a third step of obtaining each semiconductor chip by separating the semiconductor chip from the wafer. 【請求項８】前記請求項７に記載の半導体装置の製造方
法において、 前記第２の工程の後に、前記半導体チップとその半導体
チップが接続される電子装置の配線基板との間に生じる
熱応力を緩衝する応力緩衝材（エラストマ）、または未
硬化の封止材を前記半導体チップの主形成面に設ける工
程を有することを特徴とする半導体装置の製造方法。8. The method of manufacturing a semiconductor device according to claim 7, wherein, after the second step, thermal stress generated between the semiconductor chip and a wiring board of an electronic device to which the semiconductor chip is connected. Providing a stress buffer material (elastomer) or an uncured sealing material for buffering the main forming surface of the semiconductor chip. 【請求項９】前記請求項８に記載の半導体装置の製造方
法において、 前記応力緩衝材（エラストマ）、または未硬化の封止材
を前記半導体チップの主形成面に設ける工程の後に、前
記バンプの先端にソルダボールを形成する工程を有する
ことを特徴とする半導体装置の製造方法。9. The method for manufacturing a semiconductor device according to claim 8, wherein the step of providing the stress buffering material (elastomer) or the uncured sealing material on a main formation surface of the semiconductor chip is performed. Forming a solder ball at the tip of the semiconductor device. 【請求項１０】前記請求項９に記載の半導体装置の製造
方法において、 前記ソルダボールを形成する工程は、１ウエハ単位でソ
ルダペーストを前記バンプの先端面上に印刷し、その印
刷されたウエハに対してリフロー処理を行い、前記バン
プの先端にソルダボールを形成することを特徴とする半
導体装置の製造方法。10. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the solder ball includes: printing a solder paste on a tip surface of the bump in units of one wafer; A reflow process for forming solder balls at the tips of the bumps.
JP2000013952A 2000-01-18 2000-01-18 Semiconductor device, electronic device and manufacturing method thereof Pending JP2001203304A (en)

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