JP2001202329A - Device and method for transferring data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for transferring data, with which the number of wiring between a register block and a data transfer part can be reduced and operation with a high speed clock is enabled. SOLUTION: According to the count value of a counter 22, one of register blocks A13, B33 and C53 is selected and further one of plural registers is selected out of the selected register block. Thus, the number of data buses between the register blocks A13, B33 and C53 and a data transfer part 24 can become one and the number of wiring between the register blocks A13, B33 and C53 and the data transfer part 24 can be reduced. Further, since the register blocks A13, B33 and C53 are provided with buffers 15, 35 and 55, the gate delay of multiplexers 12, 32 and 52 in the register blocks A13, B33 and C53 can be avoided and high speed clock operation is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer device and a data transfer method.

[0002]

2. Description of the Related Art Conventionally, LSIs and FPGAs (Field Progra
In digital circuits such as mmabIe Gate Arrays), when transferring data from multiple registers to other circuit blocks, if all registers and other circuits are directly connected by wiring, the number of wirings becomes enormous, so the data is divided. And transfer it. For example, in Japanese Patent Application Laid-Open No. 4-308956, data is selectively transferred via a multiplexer and a buffer.

FIG. 7 is a block diagram showing a configuration of a conventional data transfer device. The data transfer device shown in FIG.
Each of the plurality of registers 1011, 1031, 1051
Blocks A1031, B1033, and C1
053, the counter 1019 and the multiplexer 102
0, a data transfer unit 1024, and a block A101.
3 and a data bus 1012 for transmitting data of each register 1011 of the block B 1033.
Data bus 1032 for transmitting data 031
And a data bus 1052 for transmitting data of each register 1051 of the block C1053.

[0004] The block A1031 is operated from <0> to <a-
The block B 1033 holds the b registers 1031 from <a> to <a + b−1>. Block C10
53 holds c registers 1051 from <a + b> to <a + b + c−1>.

The counter 101 in the data transfer unit 1024
9 is changed from 0 to (a + b + c−) in synchronization with the clock CLK.
This is a counter for counting up to 1). The multiplexer 1020 in the data transmission unit 1024 is connected to the data bus 1012 from the block A 1013 and the block B
The data bus 1032 of 1033 and the block C1053
Is a circuit that selects one type of data bus corresponding to the count value of the counter 1019 from the data bus 1052 of FIG. FIG. 8 is a table showing the relationship between the count value, the output of the data transfer unit, and the register to be selected in the data transfer device having the above configuration.

Next, the operation of the data transfer device having the above configuration will be described. The counter 1019 has a clock CLK
The multiplexer 1020 selects one data bus corresponding to the count value from the data buses 1012, 1032, and 1052 of the register in synchronization with (a), (b) and (c). The output of the data transfer unit of the data transfer unit 1024 includes the counter 10
When the count value of the block 19 is 0 to (a-1), each register 1 in the block A1013 <0 to <a-1>
011 is output.

The count value of the counter 1019 is 10
When 21 is from a to (a + b-1), the data held in each register 1031 from <a> to <a + b-1> of the block B 1033 is output. Further, the count value 1021 of the counter 1019 is (a +
In the case of b) to (a + b + c-1), block C
Data held in each register 1051 from <a + b> to <a + b + c−1> in 1053 is output.

As described above, in the above-described conventional data transfer device, the data in the register is sequentially read in accordance with the counter value.

[0009]

However, in the conventional data transfer device, the data buses 1012, 1032, and 1032 have the same number of registers as the number of registers in the block A1013, the block B1033, and the block C1053.
1052, blocks A1013, B1
033, C1053, and the number of wirings between the data transfer unit 1024 are increased, and when these are realized by an LSI or the like, the ratio of the wiring area increases, which leads to an increase in chip size and a resulting increase in cost. There is a problem. If the number of registers is large, the multiplexer 10
Since the circuit scale of the circuit 20 is also large, there is also a problem that the circuit delay becomes large and it is difficult to operate with a high-speed clock.

The present invention has been made in view of the above points, and provides a data transfer device and a data transfer method capable of reducing the number of wirings between a register block and a data transfer unit and operating at a high speed clock. The purpose is to do.

[0011]

According to the present invention, there is provided a data transfer apparatus comprising: a plurality of register blocks each having a plurality of registers; counter means for generating a repetitive count value; First selecting means for selecting one of a plurality of register blocks; and selecting one of the plurality of registers according to a count value generated by the counter means provided in each of the plurality of register blocks. And a holding means provided in each of the plurality of register blocks to hold the output of the second selecting means.

According to this configuration, since the data is selectively transferred between the register block and the data transfer unit, the number of wires between the block and the data transfer unit can be reduced.
Wiring efficiency can be improved. Since the output of the second selecting means is held by the holding means,
Electrical delay of the selection means can be avoided, and a high-speed clock operation can be performed.

Further, the data transfer device of the present invention comprises a plurality of register blocks each having a plurality of registers;
Counter means for generating a repeated count value, and selection for selecting one or all bit "0" data in the plurality of registers according to the count value generated by the counter means provided in each of the plurality of register blocks Means, holding means provided in each of the plurality of register blocks and holding the output of the selection means, and OR operation means for performing a logical OR operation on data from each of the plurality of register blocks bit by bit, Is adopted.

According to this configuration, since data is selectively transferred between the register block and the data transfer unit, the number of wires between the block and the data transfer unit can be reduced.
Wiring efficiency can be improved. Further, since the output of the selection unit is held by the holding unit, an electrical delay of the selection unit can be avoided, and a high-speed clock operation can be performed.

Further, the data transfer apparatus of the present invention has a plurality of register blocks each having a plurality of registers, a counter means for generating a repetition count value, and a counter means provided in each of the plurality of register blocks. Selecting means for selecting one or all bits "1" data from the plurality of registers according to the set count value; holding means provided in each of the plurality of register blocks to hold an output of the selecting means; AND operation means for performing an AND operation on data from each of the plurality of register blocks bit by bit.

According to this configuration, since data is selectively transferred between the register block and the data transfer unit, the number of wires between the block and the data transfer unit can be reduced.
Wiring efficiency can be improved. Further, since the output of the selection unit is held by the holding unit, an electrical delay of the selection unit can be avoided, and a high-speed clock operation can be performed.

A wireless communication terminal according to the present invention employs a configuration including the above data transfer device.

A radio communication base station according to the present invention employs a configuration including the above data transfer device.

According to the data transfer method of the present invention, one data block corresponding to the count value is selected and held from a plurality of data blocks based on the count value repeatedly generated, and from the held data, One piece of data corresponding to the count value is selected.

Further, according to the data transfer method of the present invention, one data block corresponding to the count value is selected from a plurality of data blocks based on the count value repeatedly generated. A data value is output by selecting one data of all bits “0” and performing a logical OR operation on data from all data blocks for each bit.

Further, according to the data transfer method of the present invention, one data block corresponding to the count value is selected from a plurality of data blocks based on the count value repeatedly generated. A data value is output by selecting one data of all bits “1” and performing an AND operation on data from all data blocks for each bit.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The gist of the present invention is to select and hold one data block corresponding to a count value from a plurality of data blocks based on a count value repeatedly generated, One is to select one of the data corresponding to the count value from the data.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a configuration of a data transfer apparatus according to Embodiment 1 of the present invention.

In this figure, block A13 has a value of <0
> To <a-1>, a multiplexer 12 for selecting one of the a registers 11 in addition to the a registers 11
A data bus 14 for transmitting data of each of the a registers 11 to the multiplexer 12, a buffer 15 for holding the data of the register 11 selected by the multiplexer 12 in synchronization with the clock CLK, and a multiplexer 12. And a data bus 16 for connecting the buffer 15.

The block B33 is composed of <a> to <a + b−
1> a multiplexer 32 for selecting one of the b registers 31 in addition to the b registers 31; a data bus 34 for transmitting data of each of the b registers 31 to the multiplexer 32; A buffer 35 for holding the data of the register 31 selected by the multiplexer 32 in synchronization with the clock CLK;
2 and a data bus 36 connecting the buffer 35.

The block C53 is composed of <a + b> to <a +
b + c-1> c registers 51, a multiplexer 52 for selecting one of the c registers 51, c
The data of each of the registers 51 is
Data bus 54 for transmission to the
2, a buffer 55 for holding the data of the register 51 selected in synchronization with the clock CLK, and a data bus 56 for connecting the multiplexer 52 and the buffer 55.
And is provided.

The multiplexer 20 in the data transfer unit 24
Is a data bus 18 for transmitting data held in the buffer 15 of the block A13, and a block B33.
Of the data bus 38 for transmitting the data held by the buffer 35 of the block C53 and the data bus 58 for transmitting the data held by the buffer 55 of the block C53. The data transmitted by the data bus is output to the outside.

The counter 22 in the data transfer unit 24 starts counting from 0 in synchronization with the clock CLK, increases the count value by one clock, and counts up to (a + b + c). Then, the count value is stored in the data bus 21.
To the multiplexer 20, the multiplexer 12 in the block A13, the multiplexer 32 in the block B33, and the multiplexer 52 in the block C53.

FIG. 2 shows count values and multiplexers 12, 32, 52, and 20 in the data transfer device having the above configuration.
Is a table showing the relationship between the selection logic of the data bus, the values of the data buses 18, 38 and 58, and the output values of the data transfer unit.

Next, the operation of the data transfer device according to the first embodiment of the present invention will be described with reference to FIGS.

In FIG. 1, the counter 22 counts from 0 to (a + b + c) to generate a count value. In the multiplexer 20, the data buses 18, 38 of the block corresponding to the count value of the counter 22,
One is selected. As shown in FIG. 2, in the multiplexer 12, the count value of the counter 22 is changed from 0 to (a
In the cases up to -1), one of the registers 11 of <0> to <a-1> is selected. In the multiplexer 32, the count value of the counter 22 is changed from a to (a + b-1).
<a> to <a + b−1> in register 3
One of the ones is selected. In the multiplexer 52,
The count value of the counter 22 changes from (a + b) to (a + b +
In cases up to c-1), <a + b> to <a + b + c−
One of the registers 51>1> is selected.

The data of the register 11 is output from the buffer 15 of the block A13 with a delay of one clock from the time when one register 11 is selected by the multiplexer 12. From the buffer 35 of the block B33,
The data of the register 31 is output one clock later than the time when one register 31 is selected by the multiplexer 32. The data of the register 51 is output from the buffer 55 of the block C53 with a delay of one clock from the time when one register 51 is selected by the multiplexer 52.

The data output from the multiplexer 20 of the data transfer unit 24 has a counter value of 1
In the case from to a, the block A13 from <0> to <a−
1> is the data of the register 11. Also, counter 2
When the count value of 2 is from (a + 1) to (a + b), the data of the register 31 from <a> to <a + b−1> in the block B33 is obtained. Further, when the count value of the counter 22 is from (a + b + 1) to (a + b + c),
The data of the register 51 from <a + b> to <a + b + c−1> in the block C53 is obtained.

As described above, the data transfer device according to the first embodiment selects one of the register blocks A13, B33, and C53 according to the count value of the counter 22,
Further, a configuration in which one of a plurality of registers is selected from the selected register blocks, that is, a register block A1
3, B33, C53 and the data transfer unit 24 are configured to selectively transfer data, so that a single data bus can be used between the register blocks A13, B33, C53 and the data transfer unit 24. Register blocks A13, B3
3. The number of wires between the C53 and the data transfer unit 24 can be reduced. As a result, when the circuit is implemented by an LSI or the like, the wiring area can be reduced, and the chip size can be reduced.

The register blocks A13, B33,
By providing the buffers 16, 36, and 56 in the C53, gate delays of the multiplexers 14, 34, and 54 of the register blocks A13, B33, and C53 can be avoided, and high-speed clock operation can be performed.

(Embodiment 2) FIG. 3 is a block diagram showing a configuration of a data transfer apparatus according to Embodiment 2 of the present invention. In the first embodiment described above, the data transfer unit 24 using the multiplexer is provided. In the second embodiment, the data transfer unit 124 using the OR circuit is used.
It has.

In FIG. 3, the block A113 has a value of <0
> To <a-1>, a multiplexer 112 for selecting one of the a registers 111 and all 0 inputs, and a multiplexer 112 for selecting the data of each of the a registers 111 And a data bus 114 for transmitting data to the multiplexer 1
12, a buffer 116 for holding the data of the register 111 selected by the multiplexer 112 or all "0" data in synchronization with the clock CLK, and a data for connecting the multiplexer 112 and the buffer 116. And a bus 117.

The block B133 is formed from <a> to <a + b
−1> b registers 131 and b registers 1
A multiplexer 132 for selecting one of the inputs 31 and all 0 inputs, and a data bus 134 for transmitting data of each of the b registers 131 to the multiplexer 132
A data bus 135 for transmitting all “0” data to the multiplexer 132;
The buffer 136 holds the data of the register 131 selected by 2 or all “0” data in synchronization with the clock CLK, and the data bus 137 connecting the multiplexer 132 and the buffer 136.

The block C 153 is composed of <a + b> to <a
+ B + c-1> in addition to the c registers 151, the multiplexer 152 for selecting one of the c registers 151 and the all-zero input, and the respective data of the c registers 151 for transmission to the multiplexer 152. Data bus 154 and the multiplexer 1
52, a buffer 156 for holding the data of the register 151 or all “0” data selected by the multiplexer 152 in synchronization with the clock CLK, and a data for connecting the multiplexer 152 and the buffer 156. And a bus 157.

OR circuit 120 in data transfer section 124
The data bus 118 for transmitting the data held by the buffer 116 of the block A 113, the data bus 138 for transmitting the data held by the buffer 136 of the block B 133, and the buffer 156 of the block C 153 The data bus 158 for transmitting the held data is subjected to a logical OR operation for each bit, and the result is output.

The counter 122 in the data transfer unit 124
Starts counting from the count value 0 in synchronization with the clock CLK, increases one count value in one clock,
Count up to (a + b + c). Then, the count value is output to the multiplexer 112 of the block A113, the multiplexer 132 of the block B133, and the multiplexer 152 of the block C153 via the data bus 121.

FIG. 4 shows the count value of the counter 122 and the multiplexer 11 in the data transfer device having the above configuration.
2, 132, 152 selection logic, data bus 118, 1
38 is a table showing the relationship between the values of S.38 and S.158 and the output value of the data transfer unit 124. Next, the operation of the data transfer device according to the second embodiment of the present invention will be described with reference to FIGS.

In FIG. 3, the counter 122 of the data transfer unit 124 performs counting from 0 to (a + b + c) to generate a count value. In the OR circuit 120,
One of the data buses 118, 138 and 158 of the block corresponding to the count value of the counter 122 is selected.

As shown in FIG. 4, in the multiplexer 112 of the block A113, when the count value of the counter 122 ranges from 0 to (a-1), <0> to <a-1>.
Of the registers 111 are selected. Counter 1
Except for the case where the count value of 22 is from 0 to (a-1), an all-zero input in which all bits are all "0" is selected.

The multiplexer 132 of the block B 133
Then, the count value of the counter 122 is changed from a to (a + b−
In the cases up to 1), one of the registers 131 from <a> to <a + b−1> is selected. Except for the case where the count value of the counter 122 is from a to (a + b-1), an all 0 input in which all bits are all "0" is selected.

The multiplexer 152 of the block C153
In the case where the count value of the counter 122 is from (a + b) to (a + b + c-1), the count value from <a + b> to <a +
One of the registers 151 of b + c-1> is selected. The count value of the counter 122 is changed from (a + b) to (a
Except for the case up to + b + c−1), an all 0 input in which all bits are all “0” is selected.

The buffer 11 of the block A113
6 from the multiplexer 112 to one register 1
The data of the selected register 111 or the data of all 0 is output with a delay of one clock from the time when the 11 or all 0 input is selected. The buffer 136 of the block B 133 outputs the data of the selected register 131 or the data of all 0 with a delay of one clock from the time when one of the registers 131 or all 0 inputs is selected by the multiplexer 132. From the buffer 156 of the block C 153, 1 is output from the time when one register 151 or all 0 input is selected by the multiplexer 152.
The data of the selected register 151 or the data of all 0 is output with a delay of the clock.

In the OR circuit 120 of the data transfer unit 124, the data held in the buffer 116 of the block A 113 and transmitted via the data bus 118 and the data held in the buffer 136 of the block B 133 and transmitted via the data bus 138 The transmitted data and the block C1
An operation of performing a logical OR operation on the data held in the 53 buffers 156 and transmitted via the data bus 158 is performed for each bit.

As a result, when the count value of the counter 122 is 1 to a, the data output from the OR circuit 120 is the data of the register 111 of <0> to <a-1> of the block A113. Also, the counter 122
Is from (a + 1) to (a + b), the data of the register 131 from <a> to <a + b−1> in the block B133. Further, when the count value of the counter 122 is from (a + b + 1) to (a + b + c), <a + b> to <a + b +
c-1> is the data of the register 151.

As described above, the data transfer device according to the second embodiment selects one of the register blocks 113, 133, and 153 according to the count value of the counter 122, and outputs all the outputs of the unselected register blocks. 0 ", and the data from the selected register block and the unselected register block are logically ORed bit by bit. Therefore, the register blocks A113 and B1
33, C153 and the data transfer unit 124 can be combined into one data bus, and the register blocks A113, B13
3, the number of wires between the C 153 and the data transfer unit 124 can be reduced. As a result, when the circuit is implemented by an LSI or the like, the wiring area can be reduced, and the chip size can be reduced.

The register blocks A113, B13
3, by providing buffers 116, 136, and 156 in C153, register blocks A113, B133,
The gate delay of the multiplexers 112, 132, and 152 of C153 can be avoided, and a high-speed clock operation can be performed.

(Embodiment 3) FIG. 5 is a block diagram showing a configuration of a data transfer apparatus according to Embodiment 3 of the present invention. In the above-described second embodiment, the data transfer unit 124 using the OR circuit is provided. However, in the third embodiment, the data transfer unit 224 using the AND circuit is provided.

In FIG. 5, the block A213 has a value of <0
> To <a-1>, a multiplexer 212 for selecting one of the a registers 211 and one of all 1 inputs, and a multiplexer 212 for selecting data of each of the a registers 211 Bus 214 for transmitting data to all
12, a buffer 216 for holding the data of the register 211 selected by the multiplexer 212 or all “1” data in synchronization with the clock CLK, and a data for connecting the multiplexer 212 and the buffer 216. And a bus 217.

The block B 233 is composed of <a> to <a + b
−1> b registers 231 and b registers 2
And a data bus 234 for transmitting the data of each of the b registers 231 to the multiplexer 232.
A data bus 235 for transmitting all “1” data to the multiplexer 232;
The buffer 236 holds the data of the register 231 selected by 2 or all “1” data in synchronization with the clock CLK, and the data bus 237 connecting the multiplexer 232 and the buffer 236.

The block C153 is composed of <a + b> to <a + b>.
+ B + c-1> in addition to the c registers 251, the c registers 251 and a multiplexer 252 that selects one of the all 1 inputs, and the respective data of the c registers 251 are transmitted to the multiplexer 252. Data bus 254 and the data of all "1"
52, a data bus 255 for transmitting data to the register 251 selected by the multiplexer 252, or a buffer 256 for holding data of all "1" in synchronization with the clock CLK; and data for connecting the multiplexer 252 and the buffer 256. And a bus 257.

AND circuit 220 in data transfer section 224
Is a data bus 218 for transmitting data held in the buffer 216 of the block A 213 and a block B 213.
The data bus 238 for transmitting the data held by the buffer 236 of the H.233 and the data bus 258 for transmitting the data held by the buffer 256 of the block C 253 perform an AND operation for each bit. Output the result.

The counter 222 in the data transfer unit 224
Starts counting from the count value 0 in synchronization with the clock CLK, increases one count value in one clock,
Count up to (a + b + c). Then, the count value is output to the multiplexer 212 of the block A213, the multiplexer 232 of the block B233, and the multiplexer 252 of the block C253 via the data bus 221.

FIG. 6 shows the count value of the counter 222 and the multiplexer 21 in the data transfer device having the above configuration.
2, 232, 252 selection logic, data buses 218, 2
38 is a table showing the relationship between values of the data transfer unit and the values of the data transfer unit and the data transfer unit; Next, the operation of the data transfer device according to the third embodiment of the present invention will be described with reference to FIGS.

In FIG. 5, the counter 222 of the data transfer unit 224 performs counting from 0 to (a + b + c) to generate a count value. In the AND circuit 220, one of the data buses 218, 238, 258 of the block corresponding to the count value of the counter 222 is selected.

As shown in FIG. 6, in the multiplexer 212 of the block A213, when the count value of the counter 222 ranges from 0 to (a-1), <0> to <a-1>.
One of the registers 211 is selected. Counter 2
Except for the case where the count value of 22 is from 0 to (a-1), an all 1 input in which all bits are all "1" is selected.

The multiplexer 232 of the block B233
Then, the count value of the counter 222 is changed from a to (a + b−
In the cases up to 1), one of the registers 231 from <a> to <a + b−1> is selected. Except for the case where the count value of the counter 222 is from a to (a + b-1), an all-one input in which all bits are all "1" is selected.

The multiplexer 252 of the block C253
In the case where the count value of the counter 222 is from (a + b) to (a + b + c-1), <a + b> to <a +
One of the registers 251 of b + c-1> is selected. The count value of the counter 222 is changed from (a + b) to (a
Except for the case up to + b + c-1), all 1 inputs in which all bits are all "1" are selected.

The buffer 21 of the block A 213
6 from the multiplexer 212 to one register 2
The data of the selected register 211 or the data which becomes all "1" is output one clock delay from the time when the 11 or all 1 input is selected. From the buffer 236 of the block B233, the data of the selected register 231 or the data of all "1" is output one clock delay from the time when one of the registers 231 or all 0 inputs is selected by the multiplexer 232. . From the buffer 256 of the block C253, the multiplexer 2
At 52, the data of the selected register 251 or the data which becomes all "1" is output one clock later than the time when one register 251 or all 1 input is selected.

In the AND circuit 220 of the data transfer unit 124, the data held in the buffer 216 of the block A 213 and transmitted via the data bus 218 and the data held in the buffer 236 of the block B 233 and transmitted via the data bus 238. The transmitted data and the block C2
The data held in the 53 buffers 256 and transmitted via the data bus 258 is subjected to a logical AND operation for each bit.

As a result, the data output from the AND circuit 220 indicates that the count value of the counter 222 is 1 to a.
Up to <a-1> in block A213.
> Data of the register 211. Also, counter 2
When the count value of 22 is from (a + 1) to (a + b), the data of the register 231 from <a> to <a + b−1> of the block B233 is used. Also, the counter 222
Is from (a + b + 1) to (a + b + c), <a + b> to <a + b in block C253
+ C-1> of the register 251.

As described above, the data transfer device according to the third embodiment selects one of the register blocks 213, 233, and 253 according to the count value of the counter 222, and outputs all the outputs of the register blocks that are not selected. 1 ", and the data from the selected register block and the unselected register block are logically ANDed bit by bit, so that the register blocks A213 and B2
33, C253 and the data transfer unit 224 can be made into one data bus, and the register blocks A213, B23
3, the number of wires between the C 253 and the data transfer unit 224 can be reduced. As a result, when the circuit is implemented by an LSI or the like, the wiring area can be reduced, and the chip size can be reduced.

The register blocks A213, B23
3, by providing buffers 216, 236, and 256 in C253, register blocks A213, B233,
The gate delay of the multiplexers 212, 232, and 252 of C253 can be avoided, and a high-speed clock operation can be performed.

It should be noted that the first to third embodiments are described.
In any of the above, it is needless to say that the present invention can be applied to any of a wireless communication terminal and a wireless communication base station (apparatus in a base station) that employ communication methods such as FDMA, TDMA, and CDMA.

[0069]

As described above, according to the present invention,
Select one of the register blocks according to the count value,
Furthermore, since one of the plurality of registers is selected from the register block and data is selectively transferred between the register block and the data transfer unit, the number of wires between the register block and the data transfer unit is reduced. In addition, it is possible to provide a data transfer device and a data transfer method that can operate with a high-speed clock.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer device according to a first embodiment of the present invention.

FIG. 2 is a view for explaining the operation of the data transfer device according to the first embodiment;

FIG. 3 is a block diagram showing a configuration of a data transfer device according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation of the data transfer device according to the second embodiment.

FIG. 5 is a block diagram showing a configuration of a data transfer device according to a third embodiment of the present invention.

FIG. 6 illustrates an operation of the data transfer device according to the third embodiment.

FIG. 7 is a block diagram showing a configuration of a conventional data transfer device.

FIG. 8 is a diagram for explaining the operation of a conventional data transfer device.

[Explanation of symbols]

24, 124, 224 Data transfer unit 13, 113, 213 Block A 33, 133, 233 Block B 53, 153, 253 Block C 11, 31, 51, 111, 131, 151, 211,
231,251 registers 14, 16, 18, 34, 36, 38, 54, 56, 5
8, 114 Data bus 117, 118, 134, 137, 138, 154, 1
57, 158, 214, 217, 218, 234, 23
7, 238, 254, 257, 258 Data bus 12, 32, 52, 20, 112, 132, 152, 2
12, 232, 252 multiplexer 15, 35, 55, 116, 136, 156, 216,
236, 256 buffer 22, 122, 222 counter

Claims (8)

[Claims] 1. A plurality of register blocks each having a plurality of registers; a counter means for generating a repeated count value; and selecting one of the plurality of register blocks according to the count value generated by the counter means. First
Selecting means provided in each of the plurality of register blocks, and selecting one of the plurality of registers in accordance with the count value generated by the counter means; The second
Holding means for holding the output of the selecting means. 2. A plurality of register blocks each having a plurality of registers; a counter means for generating a repetitive count value; and a plurality of register blocks provided in each of the plurality of register blocks in accordance with the count value generated by the counter means. Selecting means for selecting one or all bit "0" data in the register; holding means provided in each of the plurality of register blocks to hold the output of the selecting means; and each of the plurality of register blocks OR operation means for performing an OR operation for each bit of the data. 3. A plurality of register blocks each having a plurality of registers; a counter means for generating a repetitive count value; and a plurality of register blocks provided in each of the plurality of register blocks in accordance with the count value generated by the counter means. Selecting means for selecting one or all bit "1" data in the register; holding means provided in each of the plurality of register blocks to hold the output of the selecting means; and each of the plurality of register blocks AND operation means for performing an AND operation for each bit of the data. 4. A wireless communication terminal comprising the data transfer device according to claim 1. Description: 5. A wireless communication base station comprising the data transfer device according to claim 1. Description: 6. A data block corresponding to the count value is selected and held from a plurality of data blocks based on the count value repeatedly generated, and the data value corresponding to the count value is selected from the held data. A data transfer method, wherein one data is selected. 7. A data block corresponding to the count value is selected from a plurality of data blocks based on the count value repeatedly generated, and if not, the data value is set to all bits “0”. A data transfer method, wherein one data is selected and output, and data from all data blocks are subjected to a logical OR operation for each bit. 8. A data block corresponding to the count value is selected from a plurality of data blocks based on the count value repeatedly generated. If the data block does not correspond to the count value, all data bits are set to “1”. A data transfer method, wherein one data is selected and output, and data from all data blocks are subjected to logical AND operation for each bit.