JP2001196457A - Method for designing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent wiring process-time increase and wiring quality degradation due to congestion of wiring in designing a semiconductor integrated circuit. SOLUTION: A wiring-congestion extraction process 303 is carried out using logic-circuit connection information 302 that realizes a desired function. Area bonus cells for ensuring wiring areas are preferentially arranged (308) by considering information 307 on wiring congestion regions. The flip-flops concentrated in the same cell row are rearranged by exchanging them for the area bonus cells in upper and lower rows by an inter-cell swapping process 1001. The area bonus cells outside the wiring congestion regions are changed to repair bonus cells for circuit correction by a repair-bonus-cell arrangement process 602 executed after a wiring process 1002. Spare wiring for ensuring wiring areas is added by a repair-bonus-cell preliminary wiring process 802. The spare wiring for ensuring wiring areas is eliminated prior to mask making by a spare-wiring elimination process 804.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly, to an area bonus cell for securing a wiring area for reducing wiring congestion in an arrangement / wiring step in designing a semiconductor integrated circuit, and an area bonus cell. A bonus cell and a repair bonus cell having the same logical function are prepared to prevent the deterioration of the wiring quality of the semiconductor integrated circuit due to the wiring congestion, shorten the time required for the wiring process, and change the circuit after manufacturing the mask. The present invention relates to a method for designing a semiconductor integrated circuit, which facilitates correction of a wiring layer at the time of the above and further suppresses abnormal operation by suppressing fluctuation of a power supply voltage.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, a logic circuit block for realizing a specific or a plurality of functions is realized by laying down a cell row or securing wiring channels above and below the cell row. Standard cells having various standard logical functions are prepared as a standard cell library, and have the same height and the same height as the cell row.

FIG. 13 is a diagram showing steps of a conventional design method. The logic circuit connection information 1302 is prepared as information for connecting cells of the standard cell library 1301. In order to cope with the correction of the logic circuit connection information 1302 after manufacturing the mask, a repair bonus cell adding step 1303 is performed in advance, a repair bonus cell for correction is added to the logic circuit connection information, and an arrangement step 1304 and a wiring step 1305 are performed. After that, a semiconductor integrated circuit is designed.

[0004]

According to the conventional method shown in FIG. 13, in a wiring congestion portion of a logic circuit block corresponding to a portion where the connection information density of the logic circuit connection information 1302 is high or the like, it is difficult to place and route the logic circuit block. Requires a long processing time. Further, by generating a wiring that bypasses a wiring congested portion, deterioration of wiring quality such as a timing problem due to a wiring delay is induced. In addition, the arrangement position of the repair bonus cell is not controlled at all, and the result is that the repair bonus cell is concentrated in a specific area, and when the wiring layer is modified to respond to the circuit change, the existing wiring is This has an adverse effect, such as hindering correction, and conversely causing errors and wiring delays due to the correction of existing wiring. Furthermore, the concentration of flip-flops driven by the same synchronization signal in the same cell row causes a problem that the power supply voltage fluctuates and the circuit does not operate normally.

The present invention has been made to solve such a problem, and has as its object to prevent an increase in wiring processing due to wiring congestion and a deterioration in wiring quality in the design of a semiconductor integrated circuit.

[0006]

In order to achieve this object, the present invention preliminarily extracts a wiring congestion portion as wiring congestion portion information, and does not have a wiring layer itself in consideration of the wiring congestion portion information. Area bonus cells are preferentially arranged in advance to reduce wiring congestion. That is, the present invention extracts wiring congestion on a semiconductor integrated circuit, and increases the number of area bonus cells for securing a wiring area that does not have a wiring layer per se in a portion with high congestion and decreases in a portion with low congestion. , By prioritizing in advance,
It reduces wiring congestion and facilitates wiring processing by CAD tools, etc., thereby reducing the time required for wiring processing, suppressing the occurrence of wiring that bypasses congested parts, and reducing the quality of timing or electrical signals. It is to prevent.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of the present invention is a method for designing a standard cell type semiconductor integrated circuit in which a plurality of standard cells having a specific logic function are arranged. A wiring congestion extraction step of extracting wiring congestion information relating to the degree, and an area bonus cell which does not have a wiring layer itself and secures an area through which wiring passes, is preferentially arranged in a portion of the arrangement area where wiring congestion is remarkable. The wiring congestion extraction step is performed again, and the step of updating the wiring congestion information includes a priority arrangement step of an area bonus cell that repeats until the wiring congestion information becomes equal to or less than a specified value in the entire arrangement area. is there.

[0008] This reduces wiring congestion, facilitates wiring processing by a CAD tool or the like, shortens the time required for wiring processing, suppresses the generation of wiring that bypasses a congested part, and reduces timing or timing. It is possible to prevent quality deterioration of the electric signal. In the method of the present invention, a logic function cell having the same shape as the area bonus cell to be preferentially arranged is prepared as a repair bonus cell,
The number of wires on the already arranged area bonus cells is counted, and the area bonus cells whose number of wires passed is equal to or less than a specified value are replaced with repair bonus cells. That is, in the method of the present invention, an area bonus cell that does not actively function to alleviate wiring congestion is selected according to the number of wirings passing therethrough, and a standard logic or electric signal prepared in advance and having the same shape as the area bonus cell is selected. Is replaced with a repair bonus cell mounted with a drive transistor for preventing deterioration of the drive bonus cell.

The semiconductor integrated circuit of the present invention is designed by the above-described method for designing a semiconductor integrated circuit, and is configured so that the circuit can be changed only by correcting the wiring layer with respect to the circuit after the mask is manufactured. Things. In the semiconductor integrated circuit designed in this way, repair bonus cells for circuit correction are arranged in portions other than the wiring congested portion when the correction of the circuit after manufacturing the mask is performed only by correcting the wiring layer. ,
It can be easily modified. Further, the method of the present invention is to preliminarily connect a plurality of replaced repair bonus cells, and to remove the preliminary connection of the repair bonus cells before manufacturing a mask after a wiring process.

By doing so, the replaced repair bonus cells are connected in advance, and a wiring process using a CAD tool or the like is performed to secure a wiring area for use of the repair bonus cells. By removing the connection, it is possible to easily perform not only the repair bonus cells preliminarily wired but also the wiring correction between cells around the preliminary wiring.

In the method of the present invention, a flip-flop for taking in data in one cell column by the same synchronizing signal is replaced by area bonus cells arranged above and below the cell column. That is, when flip-flops are concentrated in the same cell row, the present invention replaces the flip-flops with area bonus cells arranged in the cell rows above and below, thereby minimizing the influence on timing and reducing the power supply voltage. Can be suppressed from occurring. In detail, a cell row in which flip-flops are concentrated is selected from the number of flip-flops arranged in the same cell row, and the area bonus cell or the repair bonus cell in the cell row above and below the selected flip-flop is replaced with the cell row in the cell row. By reducing the number of flip-flops driven at the same time,
Variations in power supply voltage that hinder signal propagation can be suppressed.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention. here,
The semiconductor integrated circuit 101 includes functional blocks 102, 103,.
Etc., and a plurality of hard blocks 104 specialized for analog signal processing. An IO cell row 106 including input / output cells 105 is arranged on the outer periphery of the semiconductor integrated circuit 101.

FIG. 2 is an enlarged view of a functional block 102 in the semiconductor integrated circuit 101. A functional block 201 corresponding to the functional block 102 in FIG. 1 is configured by regularly arranging a plurality of cell columns 202 via a wiring channel 203 as necessary. The standard cell 204 is prepared as a standard cell library 206 including a plurality of standard cells in which a standard logic function and a drive transistor for preventing deterioration of an electric signal are mounted. The standard cell library 206 stores the area bonus cell 20 having no wiring layer.
7 and a plurality of repair bonus cells 208 having exactly the same shape and a standard logic function implemented therein. The circuit information for realizing the function is realized as information for connecting a plurality of standard cells 204 of the standard cell library 206, and based on the information, the standard cells 204 are arranged in the cell column 202 and wired based on the connection information. , The functional block 201 is completed. 210 is an arranged standard cell, 211, 2
Reference numeral 14 denotes a repaired bonus cell that has been arranged, 212 denotes a wiring congested portion, and 213 denotes a wiring.

FIG. 3 schematically shows a process of arranging an area bonus cell for the functional block 102 and the like in FIG. Here, the standard cell library 30 corresponding to the standard cell library 206 of FIG.
1 and a logic congestion extraction step 303 using the logic circuit connection information 302 that implements the desired function using the logic of the standard cell. In the wiring congestion extraction step 303, after performing the general cell placement step 304,
A wiring prediction step 305 is performed, and a wiring congestion extraction step 306 is performed to generate wiring congestion information 307.

FIG. 4 schematically shows the functional blocks in the wiring congestion extraction step 303 of FIG. Function block 4
All of the standard cells 401 and the like arranged by the CAD tool 05 in FIG.
The area bonus cell 207 and the repair bonus cell 208 do not exist in this arrangement information. Here, the wiring processing is performed based on the connection information between the standard cells in the logic circuit connection information 302 of FIG. A congestion map 406 can be created. The unit area tile 40 having a large number of passing wirings
4 can be specified as a part like the wiring congestion part 402. The wiring 403 bypasses the congested part,
As a result, the wiring congestion portion 402
Is affecting.

In FIG. 3, the information of the wiring congestion degree thus predicted is extracted as wiring congestion portion information 307. In the area bonus cell priority arrangement step 308 of FIG. 3, the arrangement information of the general arrangement step 304 is deleted, and an arithmetic process is performed using the area bonus cell 207 in the standard cell library 301 and the wiring congestion section information 307. The cell 207 is preferentially arranged in a portion where wiring congestion is remarkable. Thereafter, the congested portion extraction step 306 is performed again, and the same process is repeated until the entire congested portion information 307 becomes equal to or smaller than the specified value. Thereafter, standard cells necessary for realizing the logic circuit connection information 302 are rearranged in a logic cell rearrangement step 309, and wiring processing is performed in a wiring step 310.

FIG. 5 is a schematic diagram of a layout block designed in this way. Site 4 where wiring was congested in FIG.
In the part 501 corresponding to 02, the area bonus cells are preferentially arranged more than other parts not congested with wiring, and a wiring area is secured. Reference numeral 502 denotes an arranged area bonus cell. Therefore, for example, the wiring 503 corresponding to the wiring 403 which has been detoured in FIG. 4 can be connected without using a wiring layer by using the wiring area of the arranged area bonus cell 502.

FIG. 6 is a process diagram in which a repair bonus cell arranging step 602 is added to the area bonus cell arranging step of FIG. Steps common to FIG. 3 are given the same numbers as in FIG. Area bonus cell 207 shown in FIG.
Is assigned to the area bonus cell 502 (FIG. 5) preferentially arranged with respect to the block layout information 601 arranged preferentially.
Is counted in a wiring counting step 603. Area bonus cells with a small number of passing wirings are inactive to alleviate wiring congestion, but the area around the area bonus cells is easy to modify wiring and places repair bonus cells required for circuit modification after mask fabrication. It is a desirable part. In consideration of the possibility of a circuit change according to the required semiconductor integrated circuit, an area bonus cell having a logic that is likely to be required is selected and replaced in the repair bonus cell replacement step 604. 6
Reference numeral 05 denotes a subsequent wiring step.

FIG. 7 is a schematic diagram of a layout block designed in this way. Note that components common to those in FIG. 5 are given the same numbers. There is little wiring congestion around the cells 701 to 704 replaced by the repair bonus cells in the step 604 of FIG. 6 and wiring can be easily connected at the time of wiring correction. Can be used effectively. The area bonus cell 502 is effective as a wiring area and reduces the congestion of the wiring around the area. It is difficult to use due to the congestion of wiring.

FIG. 8 is a schematic process diagram in which a repair bonus cell preliminary connection process is added to the process of FIG.
Steps common to FIG. 3 and FIG. 3 are given the same numbers. Based on the block layout information 801 that has passed through the area bonus cell arranging step 308 and the repair bonus cell arranging step 602, a repair bonus cell preliminary connecting step 802 for interconnecting a plurality of repair bonus cells for circuit correction is performed. This preliminary connection is made according to the logic circuit connection information 30.
2 are not connected to the standard cells connected. The wiring step 803 is performed based on the connection information on the preliminary connection between the repair bonus cells. Since the repair bonus cell is a replacement of the area bonus cell in the non-wiring congested portion, the damage to the wiring process in terms of time and wiring quality is small. In the preliminary connection deletion step 804,
The preliminary connection between the repair bonus cells connected in the wiring step 803 is deleted.

FIG. 9 is a schematic diagram of a block layout in which repair bonus cells are preliminarily connected to each other, and the same reference numerals as those in FIGS. 7 and 5 denote the same parts. Wirings 901 to 903 for pre-connecting repair bonus cells 701 to 704 are deleted before the mask is manufactured in a pre-connection deletion step 804 in FIG. Therefore, a wiring area for connecting the repair bonus cells 701 to 704 is more positively secured. In addition, the standard cells 904 to 906 near the wiring region can be easily corrected in the wiring layer.

FIG. 10 is a schematic diagram of a process obtained by adding a process 1001 for inter-cell-column swap of the area bonus cell 207 to the process of FIG. 8, and the steps common to FIG. 8, FIG. 6, and FIG. are doing. After the area bonus cells 207 are arranged in step 308, the number of cells such as flip-flops and the like operated by the same synchronization signal arranged in the same cell column is counted, and the number of cells is smaller than that of other columns. A process of exchanging cells such as flip-flops and area bonus cells operated by the same synchronizing signal is performed between a large number of cell rows and cell rows above and below. Reference numeral 1002 denotes a subsequent wiring step.

FIG. 11 is an enlarged view in a block showing the state. Of the cell columns 1101 to 1104, flip-flops 1116 to 1118 are concentrated on the cell column 1102. Reference numerals 1105 to 1108 denote power supply wirings, and reference numerals 1109 to 1112 denote ground wirings. When the flip-flops 1116 to 1118 in the cell column 1102 operate with the same clock, the transistors driven by the same power supply are instantaneously turned on, and the power supply wiring 1
An IR drop or power bounce occurs at which the power supply at 106 and 1107 becomes unstable. In the inter-cell-column swap step 1001 in FIG.
Flip-flops 1116 to 111
8 are concentrated, the upper and lower cell rows 1101, 11
Area bonus cells 1113-1 to priority arranged in 03
115 and flip-flop 111 in cell column 1102
Exchange 6-1118.

FIG. 12 is a diagram showing a state where the area bonus cell and the flip-flop in FIG. 11 are exchanged. The numbers correspond to those in FIG. Here, flip-flop 1117 and area bonus cell 1115
Are exchanged, whereby the number of flip-flops 1116 and 1118 in the cell column 1102 is reduced, and the number of flip-flops in each of the cell columns 1101 to 1104 is averaged.

[0025]

As described above, according to the present invention, area bonus cells are prepared in the design of a standard cell type semiconductor integrated circuit, and the area bonus cells are increased in the wiring congested portion of the functional block composed of the standard cells. By arranging, it is possible to reduce the wiring processing time and to improve the wiring quality by reducing the wiring congestion.

The area bonus cell in the non-wiring congested portion is replaced with a repair bonus cell, and the repair bonus cells are preliminarily connected to secure a wiring area, which is used for circuit correction after manufacturing a mask. A region for wiring is secured around the repair bonus cell for changing the function, and a semiconductor integrated circuit that can easily correct only the wiring layer can be provided.

Further, it is possible to alleviate the concentration of flip-flops and the like driven by the same synchronizing signal on the same cell row, thereby suppressing the fluctuation of the power supply voltage of the standard cell which adversely affects the operation of the semiconductor integrated circuit. is there.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit based on an embodiment of the present invention;

FIG. 2 is a schematic configuration diagram of a functional block in the semiconductor integrated circuit of FIG. 1;

FIG. 3 is a diagram showing a method for designing a semiconductor integrated circuit according to an embodiment of the present invention;

FIG. 4 is a schematic configuration diagram showing a wiring prediction of a functional block in the semiconductor integrated circuit according to the embodiment of the present invention;

FIG. 5 is a schematic configuration diagram showing wiring of functional blocks in a semiconductor integrated circuit designed by the method of the present invention.

FIG. 6 is a diagram showing a method for designing a semiconductor integrated circuit according to another embodiment of the present invention;

7 is a schematic configuration diagram showing a cell arrangement of functional blocks in a semiconductor integrated circuit designed by the method of FIG. 6;

FIG. 8 is a diagram showing a method of designing a semiconductor integrated circuit according to still another embodiment of the present invention.

FIG. 9 is a schematic diagram of a block layout in which repair bonus cells are pre-connected by the method of FIG. 8;

FIG. 10 is a diagram showing a method of designing a semiconductor integrated circuit according to still another embodiment of the present invention.

11 is a schematic configuration diagram showing a cell arrangement in a block before an exchange process based on the method of FIG. 10;

12 is a schematic configuration diagram showing a cell arrangement in a block after an exchange process based on the method of FIG. 10;

FIG. 13 is a diagram showing a conventional method of designing a semiconductor integrated circuit.

[Explanation of symbols]

 210 Standard cell (placed) 211, 214 Repair bonus cell (placed) 212 Wiring congestion part 301 Standard cell library 303 Wiring congestion extraction step 307 Wiring congestion information 308 Area bonus cell priority placement step 602 Repair bonus cell placement step 1001 Flip-flop Swap process between cell columns

Claims (5)

[Claims] 1. A method for designing a standard cell type semiconductor integrated circuit in which a plurality of standard cells having a specific logic function are arranged, wherein wiring congestion information relating to a congestion degree of wiring between standard cells is extracted. The wiring congestion extraction step and the area congestion cell that does not have a wiring layer itself and secures an area through which the wiring passes are preferentially arranged in a portion of the arrangement area where the wiring congestion is remarkable, and the wiring congestion extraction step is performed again. And performing a process of updating the wiring congestion information until the wiring congestion information becomes equal to or less than a specified value in the entire arrangement area. 2. A logic function cell having the same shape as an area bonus cell to be preferentially arranged is prepared as a repair bonus cell, and the number of wires on the already arranged area bonus cell is counted. 2. The method according to claim 1, wherein the area bonus cell is replaced with a repair bonus cell. 3. A semiconductor integrated circuit designed by the method for designing a semiconductor integrated circuit according to claim 2, wherein the circuit can be changed only by correcting the wiring layer with respect to the circuit correction after manufacturing the mask. 4. The method for designing a semiconductor integrated circuit according to claim 2, wherein the plurality of replaced repair bonus cells are preliminarily connected, and the preliminarily connected repair bonus cells are removed before a mask is manufactured after a wiring process. 5. The semiconductor integrated circuit design according to claim 1, wherein flip-flops for taking in data by the same synchronization signal in one cell row are replaced by area bonus cells arranged in the cell rows above and below the flip-flop. Method.