JP2001189429A - Semiconductor device, manufacturing method for the same, and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which no filicide layer is provided on a gate electrode and a manufacturing method therefor, where the semiconductor device can be reduced in apparent gate resistance. SOLUTION: A semiconductor device is equipped with gate electrodes 22 and 23 formed on the semiconductor layer of a silicon substrate 11 through the intermediary of a gate insulating layer 21, impurity diffused layers 24, 25, and 26 which form a source region and a drain region provided in the semiconductor layer in an active region, and contacts 42 to 44 and contacts 47 to 49 formed on the gate electrodes 22 and 23 located in the active region. Furthermore, in the region where contacts are formed, pad-shaped insulating layers 13 to 15 and 16 to 18 are formed under the gate electrodes 22 and 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device useful for an electrostatic protection circuit provided in an input / output circuit of a semiconductor integrated circuit device and a method of manufacturing the same.

[0002]

2. Description of the Related Art With miniaturization of semiconductor devices, a silicide layer is formed on the surface of an impurity diffusion layer in order to reduce the parasitic resistance of the impurity diffusion layer forming the source / drain region of a MOS transistor. Is often used. By thus reducing the parasitic resistance of the source / drain regions, the switching speed of the MOS transistor can be increased, and high-speed operation can be realized.

However, in a static electricity protection circuit provided in an input / output circuit of a semiconductor integrated circuit device, when a MOS transistor is used as a discharge element, reducing the parasitic resistance of the source / drain region requires an electrostatic discharge (ES).
D) There is a problem that the breakdown voltage is reduced. Thus E
The main reason for the decrease in the SD withstand voltage is that the parasitic resistance of the impurity diffusion layers constituting the source / drain regions is reduced, so that current concentration is likely to occur and thermal destruction occurs.

In order to avoid a decrease in the ESD withstand voltage due to a decrease in the parasitic resistance of the impurity diffusion layer constituting the source / drain region, the silicide layer in the source / drain region of the MOS transistor as a discharge element is partially or partially removed. A technique of not forming the entire surface is known (Japanese Unexamined Patent Publication No.
JP-A-259560, JP-A-2-271573, JP-A-4-271684, etc.).

Incidentally, a so-called full salicide process for forming a silicide layer on both the gate electrode and the source / drain regions (Full Salicide Pr)
It is extremely difficult to form a silicide layer on the gate electrode and not to form a silicide layer near the drain junction in the case of adopting the method of the prior art. That is, if a silicide layer is not formed near the drain junction, a mask (for example, an oxide layer) as salicide protection for preventing silicide from being formed
Is always formed on the gate electrode. as a result,
The silicide layer is not formed even on a part of the gate electrode, and the sheet resistance is, for example, on the order of kilo-ohms, so that high-speed operation cannot be expected. Further, the size of the silicide layer on the gate electrode is not large due to misalignment of the mask. Because of the uniformity, it is difficult to make the gate resistance constant between the transistors.

An object of the present invention is to provide a semiconductor device having no silicide layer on a gate electrode and capable of reducing an apparent gate resistance, and a method of manufacturing the same.

[0007]

According to the present invention, there is provided a semiconductor device comprising: a gate electrode formed on a semiconductor layer via a gate insulating layer; and a source region or a drain region formed on the semiconductor layer in an active region. And at least one contact portion formed on the gate electrode existing in the active region.

According to this semiconductor device, since at least one contact portion is provided on the gate electrode in the active region, even in the active region,
A predetermined potential can be supplied to the gate electrode via the contact portion, and the gate resistance can be reduced.

The semiconductor device of the present invention can further take the following aspects.

(1) In a region where the contact portion is formed, a pad-like insulating layer is formed below the gate electrode. Since the pad-like insulating layer exists between the semiconductor layer and the contact portion, it is possible to avoid the influence of the stress or the like at the time of forming the contact portion on the gate insulating layer, so that the transistor characteristics do not deteriorate. The pad-like insulating layer may have a width larger than the width of the gate electrode in a plan view in order to sufficiently achieve the above function.

(2) In the gate electrode, it is preferable that a width of the gate electrode in a region where the contact portion is formed is larger than other portions. By doing so, the formation region of the contact portion on the gate electrode is widened, and the formation is facilitated.

(3) The semiconductor device may further include a conductive layer for supplying a potential to the gate electrode, and the conductive layer may be electrically connected to the gate electrode via the contact portion. Through this conductive layer, the electric resistance of the gate electrode is substantially reduced, and high-speed operation is enabled. Therefore, it is desirable that the conductive layer is made of a material having higher conductivity than the gate electrode. For example, the conductive layer is made of a metal wiring layer. In consideration of further reducing the electric resistance of the gate electrode, it is preferable that a plurality of the contact portions are provided, and the contact portions are arranged at equal intervals.

The contact portion may be formed on the gate electrode, and its arrangement is not particularly limited. Examples of the arrangement of the contact portion include a case where the contact portion is arranged substantially along the center of the gate electrode and a case where the contact portion is displaced from the center of the gate electrode.

In particular, in the latter case, the contact portion is
It is preferable that the gate electrode is disposed in a region protruding toward the impurity diffusion layer forming the source region, and that the gate electrode has a substantially linear shape in plan view on the impurity diffusion layer forming the drain region. . in this way,
By making the side surface of the gate electrode on the drain region side straight, the drain junction can be formed smoothly, and the occurrence of electric field concentration leading to electrostatic breakdown can be prevented.

As a typical embodiment of the present invention, the following semiconductor device can be given.

A semiconductor device according to a first aspect includes a semiconductor layer, a gate electrode formed on the semiconductor layer via a gate insulating layer, and a source region or a drain region formed in a semiconductor layer of an active region. An impurity diffusion layer to be formed, a plurality of contact portions formed on a gate electrode present in the active region, a pad-like insulating layer formed under the gate electrode in a region where the contact portion is formed, and A metal wiring layer electrically connected through the contact portion to supply a potential to the gate electrode.

A semiconductor device according to a second aspect comprises a semiconductor layer, a gate electrode formed on the semiconductor layer via a gate insulating layer, and a source region or a drain region formed in a semiconductor layer of an active region. An impurity diffusion layer, a plurality of contact portions formed on a gate electrode present in the active region, a pad-like insulating layer formed under the gate electrode in a region where the contact portion is formed, and A metal wiring layer electrically connected through a contact portion to supply a potential to the gate electrode, wherein the contact portion is displaced from a center of the gate electrode toward an impurity diffusion layer forming a source region. And the gate electrode has a substantially linear shape in plan view on the side of the impurity diffusion layer constituting the drain region. To.

Further, in the semiconductor device according to the second aspect, in the impurity diffusion layer forming the source region,
The contact portions formed on the adjacent gate electrodes are arranged in pairs, and the pair of contact portions can be arranged on a single pad-shaped insulating layer.

The method for manufacturing a semiconductor device according to the present invention comprises:
The method may include the following steps (a) to (d).

(A) forming an element isolation region in a region other than the active region of the semiconductor layer; (b) forming a gate electrode on the semiconductor layer in the active region via a gate insulating layer; A) forming an impurity diffusion layer constituting a source region or a drain region in the semiconductor layer of the active region; and (d) forming at least one contact portion on a gate electrode existing in the active region.

Further, in the above manufacturing method, in the step (a), a pad-like insulating layer can be formed in a region where the contact portion is formed at the same time as the formation of the element isolation region.

In the step (d), the contact portion includes forming an interlayer insulating layer on the semiconductor layer on which the gate electrode and the impurity diffusion layer are formed, forming a contact hole in the interlayer insulating layer, It can be formed by embedding a conductive layer in the contact hole.

The method may further include forming a conductive layer for supplying a potential to the gate electrode, and the conductive layer may be electrically connected to the gate electrode via the contact portion.

Further, the pad-like insulating layer, the contact portion, and the conductive layer can be formed so as to have the characteristics of the semiconductor device described above.

The semiconductor device according to the first representative embodiment of the present invention can be obtained by a manufacturing method including the following steps (a) to (e).

(A) forming an element isolation region in a region other than the active region of the semiconductor layer, and forming a pad-like insulating layer in a region where a contact portion is formed;
(B) a step of forming a gate electrode on the semiconductor layer of the active region via a gate insulating layer; and (c) forming an impurity diffusion layer constituting a source region or a drain region in the semiconductor layer of the active region. And (d) forming a plurality of contact portions on the gate electrode existing in the active region, wherein the contact portions are:
And (e) forming a metal wiring layer electrically connected through the contact portion to supply a potential to the gate electrode. Process.

Further, the semiconductor device according to the second aspect can be obtained by a manufacturing method including the following steps. That is, the contact portion is displaced from the center of the gate electrode toward the impurity diffusion layer forming the source region, and the gate electrode is planarly arranged on the impurity diffusion layer forming the drain region. As a result, it is patterned so as to have a substantially linear shape.

Further, in this manufacturing method, the contact portions formed on the adjacent gate electrodes with the impurity diffusion layer constituting the source region interposed therebetween are arranged in pairs, and a pair of contact portions is formed. Can be formed to be disposed on a single pad-like insulating layer.

A semiconductor integrated circuit device according to the present invention includes an electrostatic protection circuit having the semiconductor device according to the present invention. This static electricity protection circuit usually has an input / output circuit (a circuit having an input circuit, an output circuit, an input circuit and an output circuit).
include.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] (Structure of Semiconductor Device) FIG. 1 is a plan view schematically showing a semiconductor device according to a first embodiment of the present invention. FIG.
FIG. 2 is a sectional view taken along line AA shown in FIG. 1. FIG.
FIG. 2 is a sectional view taken along line BB shown in FIG. 1. This semiconductor device has a M
It has an OS transistor and is designed to protect against static electricity by salicide protection. FIG. 1 shows only a part of a semiconductor device, and the structure shown in FIG. 1 can be repeated in one active region.

The semiconductor device according to the present embodiment has the first and second gate electrodes 22 made of doped polysilicon.
23. The gate electrode 22 is disposed on the gate insulating layer 21 and the pad-shaped insulating layers 13, 14, 15 formed on the silicon substrate 11, as shown in FIGS. Then, the pad-like insulating layers 13, 14, 15
The contact portions 42, 43, and 44 are formed on the gate electrode 22 in the region where is formed. further,
Each end of the gate electrode 22 is disposed on an insulating layer forming the element isolation region 12, and contact portions 41 and 45 are formed at each end of the gate electrode 22.

Similarly, the gate electrode 23 is disposed on the gate insulating layer 21 and the pad-shaped insulating layers 16, 17, 18 formed on the silicon substrate 11. Then, contact portions 47, 48, and 4 are formed on the gate electrode 23 in the regions where the pad-like insulating layers 16, 17, and 18 are formed, respectively.
9 are formed. Further, each end of the gate electrode 23 is disposed on the insulating layer 12 constituting an element isolation region, and contact portions 46 and 50 are formed at each end.

The silicon substrate 11 on both sides of each of the first and second gate electrodes 22 and 23 has an impurity diffusion layer (hereinafter referred to as “source / drain region impurity diffusion layer”) constituting a source region or a drain region. 24)
25 and 26 are formed. Part of the source / drain regions on the impurity diffusion layers 24, 25, and 26 is provided with a silicide layer 3 such as a titanium silicide layer.
3, 34, 35 are formed. Silicide layer 33,
34 and 35 are electrically connected to a wiring layer (not shown) by contact portions 51, 52 and 53. This wiring layer includes impurity diffusion layers 24, 25,
26 for supplying current.

The silicide layers 33, 34, 35 are part of the source / drain regions on the impurity diffusion layers 24, 25, 26, more specifically, on the impurity diffusion layers 24, 25, 26 and the gate electrodes. It is formed at a position away from 22,23. Therefore, the impurity diffusion layers 24, 25, 26 other than the regions where the silicide layers 33, 34, 35 are formed.
Above, and on the first and second gate electrodes 22 and 23,
Silicon oxide layer as salicide protection,
A protection insulating layer 31 such as a silicon nitride layer is provided.

Under the first gate electrode 22, a plurality of pad-like insulating layers (in this example, first, second, and third pad-like insulating layers 13, 14, and 15) are formed. . Similarly, a plurality of pad-like insulating layers (in this example, fourth, fifth, and sixth pad-like insulating layers 16, 17, and 18) are formed below the second gate electrode 23.

The portion of the first gate electrode 22 located on the pad-like insulating layers 13, 14, 15 is wider than the gate electrode 22 in the region where the pad-like insulating layers 13, 14, 15 are not formed. The planar shape is formed large. Similarly, the portion of the second gate electrode 23 located on the pad-like insulating layers 16, 17, 18 has a larger width than the gate electrode 23 in a region where the pad-like insulating layers 16, 17, 18 are not formed. The planar shape is formed large. By forming the gate electrode in this manner, the formation region of the contact portion on the gate electrode is widened, and the formation of the contact portion is facilitated.

The pad-like insulating layers (pad-like insulating layers 13 to 18 in this example) are provided with gate electrodes (in this example, contact areas 42 to 44 and 47 to 49) in regions where contact portions are formed. It is formed below the gate electrodes 22, 23). Since the pad-like insulating layer is present between the silicon substrate and the contact portion, it is possible to avoid the influence of the stress at the time of forming the contact portion on the gate insulating layer, so that the transistor characteristics are not reduced. The pad-like insulating layer is preferably larger in plan view than the gate electrode in order to sufficiently achieve the above function.

The contact portions 41 to 41 of the first gate electrode 22
45 and contact portions 46-5 of the second gate electrode 23
0s are formed at equal intervals. in this way,
By providing a plurality of contact portions at equal intervals, a predetermined potential can be applied evenly to the gate electrode.

In order to arrange the contact portions in this way, pad-like insulating layers are also formed at equal intervals. That is,
First, second, and third pad-shaped insulating layers 13, 14, 15
Are arranged at a predetermined interval W2 from each other.
The pad-shaped insulating layer 13 and one end of the first gate electrode 22 have an interval W2, and the third pad-shaped insulating layer 1
5 and the other end of the first gate electrode 22 have an interval W2. The first, second, and third pad-shaped insulating layers 13, 14,
Reference numeral 15 denotes impurity diffusion layers 24, 2 of source / drain regions.
5, and is formed at a position in contact with the silicide layer 33,
34 are arranged between them.

Similarly, the fourth, fifth, and sixth pad-shaped insulating layers 16, 17, and 18 are arranged at a predetermined interval W2 from each other, and the fourth pad-shaped insulating layer 16 and the second pad-shaped insulating layer 16 are separated from each other. It has an interval W2 with one end of the gate electrode 23, and
The pad-shaped insulating layer 18 and the other end of the second gate electrode 23 have an interval W2. The fourth, fifth, and sixth pad-shaped insulating layers 16, 17, and 18 are formed at positions in contact with the impurity diffusion layers 25 and 26 in the source / drain regions.
Further, it is arranged between the silicide layers 34 and 35.

The first gate electrode 22 has a contact portion 41
To 45 electrically connect to the first metal wiring layer 55. Similarly, the second gate electrode 23 is
6 to 50 are electrically connected to the second metal wiring layer 57. These metal wiring layers 55 and 57 are for supplying a potential to the first and second gate electrodes 22 and 23, and have a plurality of contact portions for shortening a current supply path to the gate electrodes. It is connected to the gate electrode through the gate.

In the MOS transistor according to the present embodiment, its size is exemplified by an overall width W1 of 50 μm.
The width W2 of each segment divided by the island of the pad-shaped insulating layer is about 10 μm.

(Method of Manufacturing Semiconductor Device) Next, a method of manufacturing the above-described semiconductor device will be described with reference to FIGS.

(1) As shown in FIGS. 2 and 3, first, an element isolation region 12 and pad-like insulating layers 13 to 15, 16 to 17 are formed on a surface of a silicon substrate 11 by a LOCOS method or a trench isolation method. Form. Next, a gate insulating layer 21 is formed on the silicon substrate 11 by a thermal oxidation method. Next, the gate insulating layer 21
First and second gate electrodes 22 and 23 made of doped polysilicon are formed thereon. Then, ion implantation is performed using the first and second gate electrodes 22 and 23 as a mask to form an extension layer (not shown) such as a low-concentration impurity diffusion layer constituting an LDD structure on the silicon substrate 11. Is done. This extension layer is formed as necessary depending on the structure of the device.

(2) Thereafter, sidewall spacers 27 are provided on both side walls of the first and second gate electrodes 22 and 23 by a known method. Further, the gate electrodes 22 and 2
3 and the sidewall spacer 27 as a mask, the source /
Impurity diffusion layers 24, 25, 26 of the drain region are formed.

(3) Next, the first and second gate electrodes 2
2, 23 and impurity diffusion layers 2 of source / drain regions
CVD (Chemical Vap)
or Deposition) to deposit an insulating layer for a protective insulating layer. As the protective insulating layer, silicon oxide, silicon nitride, or the like can be used. Thereafter, an opening is formed in a predetermined region by etching, and the protection insulating layer 31 is formed. The opening is formed in a region where silicide layers 33, 34, 35 described later are formed. Next, a metal layer (not shown) for a silicide layer such as a titanium layer is deposited on the entire surface including the impurity diffusion layers 24, 25, and 26 of the source / drain regions exposed by the openings. Thereafter, heat treatment is performed to form silicide layers 33, 34, 35 on the exposed surfaces of the impurity diffusion layers 24, 25, 26.

(4) Thereafter, the silicide layers 33, 34,
An interlayer insulating layer 32 is deposited on the entire surface including the insulating layer 35, and contact holes are provided in the interlayer insulating layer 32 and the protection insulating layer 31. Next, in the contact hole and the interlayer insulating layer 3
A metal layer having a predetermined pattern is deposited on the second metal layer 2 to form contact portions 41 to 45, 46 to 50 and metal wiring layers 55, 57.
To form

Through the above steps, the semiconductor device according to the present embodiment can be formed.

According to the first embodiment, the gate electrode is formed in the region where the first to third pad-shaped insulating layers 13 to 15 and the fourth to sixth pad-shaped insulating layers 16 to 18 are formed. Contact portions 42 to 44, 47 to 4 on 22, 23
9 are provided. The first gate electrode 22 and the first metal wiring layer 55 are connected via the contact portions 41 to 45, and similarly, the second gate electrode 23 and the second metal wiring layer 57 are connected via the contact portions 46 to 50. And are connected. That is, each gate electrode is connected to the metal wiring layer at a plurality of contact portions.

For this reason, in the present embodiment, as compared with a semiconductor device of a type in which only one end of the gate electrode is in contact with the metal wiring layer in the element isolation region, the apparent appearance of the gate electrode is different in this embodiment. Resistance can be reduced. In the present embodiment, since no silicide layer is formed on the gate electrode, there is no need for a mask alignment margin required when the silicide layer is formed on the gate electrode. Specifically, the gate length can be reduced to 0.6 μm or less. Therefore, not only can the transistor be operated at high speed, but also the transistor can be further integrated.

In this embodiment, since no silicide layer is formed on the gate electrode, there is no variation in gate resistance due to a change in the size of the silicide layer. Therefore, it is possible to make the gate resistance constant between the transistors, and to reduce variations in transistor characteristics.

[Second Embodiment] FIG. 4 is a plan view schematically showing a semiconductor device according to a second embodiment of the present invention. FIG. 5 is a sectional view taken along the line CC shown in FIG. This semiconductor device has a MOS transistor constituting an electrostatic protection circuit of an input / output circuit, and achieves electrostatic protection by salicide protection. Hereinafter, features of the present embodiment that are different from the first embodiment will be mainly described, and portions having substantially the same functions as those of the semiconductor device according to the first embodiment will be denoted by the same reference numerals. Description is omitted.

This embodiment is different from the first embodiment in the area of forming the contact portion. That is,
In the first embodiment, the contact portion is provided substantially along the center of the gate electrode, whereas in the second embodiment, the contact portion is displaced toward the impurity diffusion layer constituting the source region. It is formed with.

As shown in FIG. 4, in the first gate electrode 22, the contact portions 42, 43, and 44 are displaced toward the impurity diffusion layer 24 constituting one of the source regions. In the second gate electrode 23, the contact portions 47, 48, and 49 are provided displaced toward the impurity diffusion layer 26 constituting the other source region.
Specifically, the gate electrode 22 has contact portions 42 and 4
Protruding portions 22a, 22 including the regions where
Similarly, the gate electrode 23 has protrusions 23a, 23b, and 23c including regions where the contact portions 47, 48, and 49 are formed.

As shown in FIG. 5, pad-like insulating layers 13, 14, 15 are formed below the protruding portions 22a, 22b, 22c of the gate electrode 22, respectively. Similarly, pad-like insulating layers 16, 17, and 18 are formed below the protruding portions 23a, 23b, and 23c of the gate electrode 23, respectively. Therefore, in this semiconductor device, the pad-like insulating layers 13, 14, 15 and 16, 17, 18 are displaced from the centers of the gate electrodes 22, 23 toward the source region. Then, the pad-like insulating layers 13, 14,
15 and 16, 17, 17, and 18 on the gate electrodes 22, 2
3 projections 22a, 22b, 22c and 23a, 23
b, 23c are arranged, and on these projections,
Contact portions 42, 43, 44 and 47, 48, 49
Is arranged.

By displacing the contact portion from the gate electrode toward the source region in this manner, the gate electrodes 22 and 2 are displaced.
Nos. 3 are formed such that no projecting portion exists on the side of the impurity diffusion layer 25 constituting the drain region.
Therefore, the side surfaces of the gate electrodes 22 and 23 on the side of the impurity diffusion layer 25 constituting the drain region are formed substantially linearly. As a result, it is possible to form a drain junction which does not have an uneven shape in which electric field concentration easily occurs.

The first metal wiring layer 55 is
There is no particular limitation as long as they are connected to .about.45. For example, they can have a pattern that overlaps with the gate electrode 22 and its protruding portions 22a to 22c. Similarly, second metal wiring layer 57 is not particularly limited as long as it is connected to contact portions 46 to 50, and may have a pattern overlapping gate electrode 23 and protrusions 23a to 23c thereof, for example.

The method of manufacturing a semiconductor device according to the present embodiment
Basically, the same method as described in the first embodiment can be adopted. Then, in forming the pad-like insulating layer, the gate electrode, and the metal wiring layer, these are patterned so as to have a predetermined pattern.

According to this embodiment, in addition to the functions and effects described in the first embodiment, the following features are provided. That is, since the gate electrode has a substantially linear shape on the side of the impurity diffusion layer constituting the drain region, the drain junction can be formed smoothly, and thus, the electric field concentration leading to electrostatic breakdown can be more reliably avoided. .

(Modification) FIG. 6 is a plan view schematically showing a modification of the second embodiment. This example is the same as the above-described embodiment in that the contact portion is displaced from the center of the gate electrode toward the source region. The same parts as those in the second embodiment will be described with the same reference numerals.

In this example, in the impurity diffusion layer forming the source region, a plurality of pairs of contact portions formed on adjacent gate electrodes are arranged in pairs, and a pair of contact portions is Each is arranged on a single pad-like insulating layer.

In FIG. 6, impurity diffusion layers 25 and 28 constituting the drain region are arranged with impurity diffusion layer 24 constituting the source region interposed therebetween, and a pair of contact portions 62 formed in impurity diffusion layer 24 are provided. , 64. Protrusions 22a and 29a protruding toward the impurity diffusion layer 24 constituting the source region are formed on the gate electrode 22 and the gate electrode 29 adjacent thereto. One pad-shaped insulating layer 60 is formed below these adjacent protruding portions 22a and 29a. The pad-like insulating layer 60 is formed so as to include at least regions of the contact portions 62 and 64 formed on the protruding portions 22a and 29a when viewed in plan. Therefore, the pad-like insulating layer 60
In the region where is formed, the contact portion 51 of the source region 24 is not formed. 6, reference numeral 36 denotes a silicide layer formed on the surface of the impurity diffusion layer 28, and reference numeral 54 denotes a contact portion.

In this example, by forming a pair of contact portions 62 and 64 adjacent to each other in the source region 24 on a single pad-like insulating layer 60, the contact portions 62 and 64 are formed more than in the semiconductor device shown in FIGS. Can have a compact structure.

The present invention is not limited to the above embodiment,
Various modifications can be made within the scope of the present invention. For example, the interval W2 between the pad-shaped insulating layers can be changed depending on the design of the device, and the interval between the pad-shaped insulating layers provided in the active region is made unequal. It is also possible.

In the above embodiment, the semiconductor substrate is used as the semiconductor layer. However, the present invention is not limited to this.
It is also possible to use a semiconductor layer of an SOI substrate.

In the above embodiment, the silicide layer is formed in a part of the source / drain region on the impurity diffusion layer. However, such a silicide layer is not an essential requirement of the present invention. Therefore, the present invention can have a MOS transistor in which a silicide layer is not formed.

In the present embodiment, the contact portions with the metal wiring layer are formed at a plurality of positions of the gate electrode existing in the active region. However, the contact portions are formed at one position of the gate electrode existing in the active region. It is also possible to form

The semiconductor device according to the present invention can constitute at least a part of an electrostatic protection circuit. Such an electrostatic protection circuit is not particularly limited, and can be configured to include at least one of a MOS transistor, a diode, a bipolar transistor, a thyristor, and the like. The electrostatic protection circuit is usually included in an input / output circuit (a circuit having an input circuit, an output circuit, an input circuit, and an output circuit).

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA shown in FIG.

FIG. 3 is a sectional view taken along line BB shown in FIG.

FIG. 4 is a plan view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view taken along the line CC shown in FIG.

FIG. 6 is a plan view showing a modification of the second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Silicon substrate 12 Element isolation region 13-18,60 Pad-shaped insulating layer 21 Gate insulating layer 22 First gate electrode 23 Second gate electrode 24-26,28 Impurity diffusion layer constituting source / drain region 27 Sidewall spacer 31 Protective insulating layer 32 Interlayer insulating layer 33-36 Silicide layer 41-50,62,64 Contact part 55,57 Metal wiring layer

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) AA02 AC01 BA20 BB05 BC01 BF00 BF06 BF07 BF15 BF16 BG12 CC04 CC11

Claims (31)

[Claims] A gate electrode formed on a semiconductor layer with a gate insulating layer interposed therebetween; an impurity diffusion layer forming a source region or a drain region formed on the semiconductor layer in an active region; A semiconductor device including at least one contact portion formed on an existing gate electrode. 2. The semiconductor device according to claim 1, wherein a pad-like insulating layer is formed under the gate electrode in a region where the contact portion is formed. 3. The semiconductor device according to claim 2, wherein a part of the pad-like insulating layer is formed deeper than the gate insulating layer with respect to the semiconductor layer. 4. The semiconductor device according to claim 2, wherein the pad-like insulating layer has a width larger than a width of the gate electrode in plan view. 5. The semiconductor device according to claim 1, wherein a width of the gate electrode in a region where the contact portion is formed is larger than a width of the gate electrode in a region where the contact portion is not formed. 6. The semiconductor device according to claim 1, further comprising a conductive layer for supplying a potential to the gate electrode, wherein the conductive layer is electrically connected to the gate electrode via the contact portion. The semiconductor device is connected to. 7. The semiconductor device according to claim 6, wherein the conductive layer is a metal wiring layer. 8. The semiconductor device according to claim 1, wherein the number of the contact portions is plural. 9. The semiconductor device according to claim 8, wherein the contact portions are arranged at equal intervals. 10. The semiconductor device according to claim 1, wherein a silicide layer is formed on the impurity diffusion layer at a distance from the gate electrode. 11. The semiconductor device according to claim 1, wherein the contact portion is arranged substantially along a center in a width direction of the gate electrode. 12. The semiconductor device according to claim 1, wherein the contact portion is displaced from a center in a width direction of the gate electrode. 13. The semiconductor device according to claim 12, wherein the contact portion is disposed in a region protruding toward an impurity diffusion layer constituting a source region. 14. The semiconductor device according to claim 13, wherein the gate electrode has a substantially linear shape in plan view on the side of the impurity diffusion layer forming the drain region. 15. A semiconductor layer, a gate electrode formed on the semiconductor layer via a gate insulating layer, an impurity diffusion layer forming a source region or a drain region formed on the semiconductor layer of the active region, A plurality of contact portions formed on a gate electrode present in a region, a pad-like insulating layer formed below the gate electrode in a region where the contact portion is formed, and an electric connection via the contact portion. And a metal wiring layer for supplying a potential to the gate electrode. 16. A semiconductor layer, a gate electrode formed on the semiconductor layer via a gate insulating layer, an impurity diffusion layer forming a source region or a drain region formed on a semiconductor layer of an active region, A plurality of contact portions formed on a gate electrode present in a region, a pad-like insulating layer formed below the gate electrode in a region where the contact portion is formed, and an electric connection via the contact portion. And a metal wiring layer for supplying a potential to the gate electrode, the contact portion being displaced from the center of the gate electrode to the side of the impurity diffusion layer constituting the source region, and The semiconductor device, wherein the gate electrode has a substantially linear shape in plan view on the side of the impurity diffusion layer forming the drain region. 17. The impurity diffusion layer forming the source region according to claim 16, wherein contact portions formed on adjacent gate electrodes are arranged in pairs, and the pair of contact portions are A semiconductor device disposed on one pad-like insulating layer. 18. A method for manufacturing a semiconductor device, comprising the following steps (a) to (d). (A) a step of forming an element isolation region in a region other than the active region of the semiconductor layer; (b) a step of forming a gate electrode on the semiconductor layer of the active region via a gate insulating layer; Forming an impurity diffusion layer constituting a source region or a drain region in a semiconductor layer of the region; and (d) forming a gate electrode on the active region on the gate electrode.
Forming at least one contact portion; 19. The method of manufacturing a semiconductor device according to claim 18, wherein in the step (a), a pad-like insulating layer is formed in a region where the contact portion is formed at the same time as the formation of the element isolation region. 20. The pad-like insulating layer according to claim 19, wherein the pad-like insulating layer is formed in the step (b) in plan view.
A method of manufacturing a semiconductor device, wherein the semiconductor device is patterned so as to have a width larger than the width of the gate electrode formed in step (a). 21. The method according to claim 18, wherein in the step (b), the width of the gate electrode in a region where the contact portion is formed is smaller than the width of the gate electrode in a region where the contact portion is not formed. A method for manufacturing a semiconductor device, wherein the patterning is performed so as to be larger than the width. 22. The method according to claim 18, wherein in the step (d), the contact portion forms an interlayer insulating layer on a semiconductor layer on which the gate electrode and the impurity diffusion layer are formed, A method for manufacturing a semiconductor device, comprising: forming a contact hole in the interlayer insulating layer; and burying a conductive layer in the contact hole. 23. The semiconductor device according to claim 18, further comprising a step of forming a conductive layer for supplying a potential to the gate electrode, wherein the conductive layer is connected to the gate via the contact portion. A method for manufacturing a semiconductor device electrically connected to an electrode. 24. The method according to claim 23, wherein the conductive layer is a metal wiring layer. 25. The method of manufacturing a semiconductor device according to claim 18, wherein the contact portion is formed at a plurality of locations. 26. The method according to claim 25, wherein the contact portions are formed at equal intervals. 27. The method of manufacturing a semiconductor device according to claim 18, further comprising a step of forming a silicide layer on the impurity diffusion layer at a distance from the gate electrode. 28. A method for manufacturing a semiconductor device, comprising the following steps (a) to (e). (A) forming an element isolation region in a region other than the active region of the semiconductor layer and forming a pad-like insulating layer in a region where a contact portion is formed; (b) forming a pad-like insulating layer on the semiconductor layer in the active region; A step of forming a gate electrode via a gate insulating layer; (c) a step of forming an impurity diffusion layer constituting a source region or a drain region in the semiconductor layer of the active region; and (d) a gate existing in the active region. On the electrode,
Forming a plurality of contact portions, wherein the contact portions are formed so as to be respectively located on the pad-shaped insulating layers; and (e) electrically connected via the contact portions. Forming a metal wiring layer for supplying a potential to the gate electrode. 29. The impurity element according to claim 28, wherein the contact portion is displaced from a center of the gate electrode toward an impurity diffusion layer forming a source region, and the gate electrode is formed of an impurity forming a drain region. A method for manufacturing a semiconductor device, wherein a pattern is formed on a diffusion layer side so as to have a substantially linear shape in plan view. 30. The contact portion according to claim 29, wherein the contact portions formed on the adjacent gate electrodes with the impurity diffusion layer forming the source region therebetween are arranged in pairs, and the contact portions are formed in pairs. Is
A method for manufacturing a semiconductor device, which is formed so as to be disposed on a single pad-shaped insulating layer. 31. A semiconductor integrated circuit device including an electrostatic protection circuit having the semiconductor device according to claim 1. Description: