JP2001188752A - Device and method for controlling asynchronous data transfer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a writing speed in a buffer faster than a reading speed, and to generate overwrite when the writing of input data in the buffer is continued. SOLUTION: Data inputted from a transmission side are stored in buffers 1-6 in 6 levels. A write control circuit 11 writes data in the buffers according to a strobe clock, and a read control circuit 10 transmits a read address to a selector 12 in response to a RDY synchronizing pulse. The sector 12 selects the buffer corresponding to the read address, and outputs the read data. The RDY synchronizing pulse is generated by flip flops 7-9, an inverter 13, and an AND gate 14 in response to the RDY synchronizing with the strobe clock and a chip clock asynchronizing with the strobe clock. The read control circuit 10 preliminarily detects the overwrite, and transmits a BUSY to a transmission side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous data transfer control, and more particularly, to an asynchronous data transfer control suitable for suppressing overwrite in a computer device and other electronic devices.

[0002]

2. Description of the Related Art An example of this kind of prior art is disclosed in Japanese Unexamined Patent Publication No.
No. 43283 describes this as a "data rate converter". This device is a computer device,
The purpose of the present invention is to perform highly reliable data rate conversion that prevents data in the buffer buffer from being lost, and FIG. 9 is a block diagram showing an example thereof.

In FIG. 9, data buffers 101, 1
02 and 103 are writable, the chip selector control circuit 114 controls the switch 116 via the chip selector 4.
Are switched in the order of the terminals a, b, c, a..., So that data input from the [A] side is written in the order of the data buffers 1, 2, 3, 1,. Next, when these data buffers are made readable, the chip selector control circuit 115 synchronously operates
05 to the terminals c, a, b, c,.
Data buffer 1 by switching in the order of
.. Are read in order from 03, 101, 102, 103,... And output to [B]. At this time, the same data buffer is controlled so as not to be simultaneously used for writing and reading, and the speed of input data and output data is converted.

[0004]

In this type of asynchronous data transfer control device, as described above, when input data is written to a data buffer, and then when data is read and output, the data write speed and the read speed are read. When the writing speed is higher than the reading speed, the number of stages of the data buffer is finite. Therefore, according to the above-described related art, if the writing of the input data to the data buffer is continuous, the same It is possible that the data buffer is used simultaneously for reading and writing data. In such a case, if new data is written by overwriting before reading the data written in the data buffer, the already written data will be lost and the newly written data will be read instead. There is a problem that there is a possibility that a problem of being issued may occur.

It is an object of the present invention to provide an asynchronous data transfer control device and method which does not cause overwriting even when the writing speed is higher than the reading speed.

It is another object of the present invention to provide an asynchronous data transfer control device and method which can achieve the above object with a simple circuit.

[0007]

According to a first aspect of the present invention, there is provided an asynchronous data transfer control device for converting an input data rate into an output data rate. A means for detecting an overwrite in advance and a means for transmitting the detection to the input data input side are provided to suppress overwriting to the buffer buffer.

According to a second aspect of the present invention, there is provided an asynchronous data transfer control device for converting the speed of input data and outputting the data asynchronously and sequentially, wherein a buffer buffer for storing the input data is provided. A write control circuit for sequentially writing the input data to the buffer buffer in synchronization with a write clock; a read preparation pulse synchronized with the write clock; and a read synchronization pulse generated from a read clock asynchronous with the write clock. A synchronization circuit that generates a read address for reading the input data stored in the buffer buffer in response to the read synchronization signal, and detects an overwrite to the buffer buffer in advance. A read control circuit for transmitting the detection to the input data input side. To.

According to a third aspect of the present invention, there is provided an asynchronous data transfer control device for converting the speed of input data and outputting the data asynchronously and sequentially. A buffer buffer for storing a start bit or end bit indicating whether the word is the last word, and a write control circuit for sequentially writing the input data to the buffer buffer together with the start bit or end bit in synchronization with a write clock. A synchronization circuit that generates a read synchronization pulse from a read preparation pulse synchronized with the write clock and a read clock that is asynchronous with the write clock; and a synchronization circuit that is stored in the buffer buffer in response to the read synchronization signal. Issue a read address to read the input data A read control circuit, and a BUSY notification circuit for detecting an overwrite to the buffer buffer in advance based on the start bit or the end bit when reading the buffer buffer and transmitting the detection to the input data input side. It is characterized by having.

According to the present invention, in asynchronous data transfer control for converting the speed of input data and outputting the data asynchronously and sequentially, first, input data is sequentially written to a buffer buffer in synchronization with a write clock. Then, a read synchronizing pulse is generated from a read preparation pulse synchronized with the write clock and a read clock asynchronous with the write clock. The REATE address is generated in response to a read synchronization signal. At this time, overwriting to the buffer buffer is detected in advance, and this detection is transmitted to the input data input side.

In addition, input data and a start bit or an end bit indicating whether the input data is the first word or the last word are sequentially written in the buffer buffer in synchronization with the write clock. Based on the start bit or end bit, the overwrite to the buffer is detected in advance,
The detection may be transmitted to an input of the input data.

As described above, by recognizing the state immediately before the buffer buffer is overwritten, the data input side is notified and the data transfer can be made to wait, so that the data in the buffer buffer is lost. Can be prevented.

In addition, since the optimum number of buffer buffers is obtained by a calculation formula and installed in the apparatus, the necessary minimum buffer buffer configuration can be obtained.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention having a function of suppressing overwriting to a buffer buffer.

This data transfer control device is a device for reading data written in a buffer buffer at a different speed from that at the time of writing without changing the order of the data. Therefore, the data structure included in one transaction must not be changed, and there must be no data of an address that is not read. Note that writing and reading are performed asynchronously.

In FIG. 1, reference numerals 1, 2, 3, 4, 5, and 6 denote buffer buffers for reading and writing data whose transmission speed is to be converted and an END signal indicating the end of one transaction transfer. Reference numerals 7, 8 and 9 denote flip-flops used for synchronization, 10 denotes a read control circuit for controlling reading of data from the buffer buffers 1 to 6, and 11 denotes writing of data to the buffer buffers 1 to 6. A write control circuit 12 for performing control is a selector for performing control for selecting one of the buffer buffers 1 to 6.

Next, the operation of the present embodiment will be described with reference to a time chart. One transaction transfer amount is four words. Here, one word has a bit length of one stage of the buffer buffer.

The buffer buffers 1 to 6 become writable when WE (write enable) input from the data transmission side is at a high level. When WE is at a high level, the write control circuit 11 increments the write address from 1 to 6 in ascending order in synchronization with the strobe clock, as shown in FIG. 3, and repeats it. Therefore, the write address is sequentially incremented as 1, 2, 3, 4, 5, 6, 1,.... The data input from the transmitting side is synchronized with the strobe clock, and the buffer buffer 1, buffer buffer 2, buffer buffer 3, buffer buffer 4, buffer buffer 5, buffer buffer 6, buffer buffer corresponding to the value indicated by the write address are used. Writing is performed in the order of 1.... At the same time, a write address indicating which word is stored in these buffer buffers 1 to 6 is also written.

The RDY synchronization pulse is as shown in FIG.
First, RDY synchronized with the strobe clock input from the transmission side is input to the flip-flop 7 which operates in synchronization with the chip clock. Next, it is created by taking the leading edge differential of the output of the flip-flop 8 from the flip-flop 8 and the flip-flop 9 operating in synchronization with the chip clock. That is, the AND result of the AND gate 14 of the output of the flip-flop 8 and the output of the flip-flop 9 inverted by the inverter 13 is R
It becomes a DY synchronization pulse.

Here, the width of RDY is required to be greater than the width of the chip clock. Because the strobe clock and the chip clock are asynchronous, the flip-flop 7
Data and the transition point of the chip clock are almost the same,
This is because meta stable (undefined state) occurs. However, if the RDY has a width equal to or larger than the width of the chip clock, even if a metastable occurs due to the above operation, the RDY does not transition in the next chip clock, and the metastable does not continue, so that it becomes stable.

As shown in FIG. 3, the read control circuit 10 uses the RDY synchronization pulse as a trigger in synchronization with the chip clock to set the read address to 1, 2, 3, 4, 5,
.. Are incremented by four words in the order of 6, 1,. Data is read from the buffer buffer via the selector 12 in the order of buffer buffer 1, buffer buffer 2, buffer buffer 3, buffer buffer 4, buffer buffer 5, buffer buffer 6, buffer buffer 1,.

Here, when the frequency of the strobe clock is equal to the frequency of the chip clock, the high-level timing of the RDY synchronizing pulse in the metastable in both the first and second transactions as shown in FIG. At the same time, reading from the buffer buffer can be normally and continuously performed using the RDY synchronization pulse as a trigger.

As shown in FIG. 6 (2), when the first transaction is normally synchronized and the second transaction is tilted to a high level due to the metastable of the synchronization, The RDY synchronization pulse may go high at the same timing as the read timing of the last word (read address 4). In this case, if the data is read as it is, the read address 4 deviates from the first transaction and is treated as the first word of the second transaction. Therefore, in such a case, control may be performed so that the data of the second transaction is read from the timing delayed by 1T of the RDY synchronization pulse. As a result, reading from the buffer buffer is performed continuously without changing the data structure in the transaction.

Under the condition that the frequency of the strobe clock is equal to the frequency of the chip clock, the RDY synchronizing pulse does not go high at the same timing as the timing of the third word. When the RDY synchronizing pulse goes high at the same timing as the timing of the third word, at this time, as will be described in detail later, it is not related to the previous transaction but to the overwriting in its own transaction. The problem emerges.

As shown in FIG. 4C, when the output of the flip-flop 7 is inclined to a high level by the metastable of the first transaction and the second transaction is normally synchronized, RDY is used. The synchronization pulse goes high 1 T after the end of reading of the first transaction. Therefore, 1T is left between the end of the first transaction and the start of reading of the second transaction, so that continuous reading from the buffer buffer can be performed without any trouble.

As described above, when the strobe clock width is equal to the chip clock width, FIG.
In any of the cases (2) and (3), the RDY synchronization pulse goes high at the same timing as the last word (FIG. 6 (2)) or the first word (FIG. 6 (1)). However, since the RDY synchronization pulse does not go high at the same timing as the third word (read address 3), continuous reading from the buffer buffer can be performed without any trouble.

In the case where the frequency of the strobe clock is higher than the frequency of the chip clock, that is, in the case where writing is fast, when the transaction is continuous, the read timing is compared with the write timing as shown in FIG. Gradually delays. Then, as the delay progresses, the RDY synchronization pulse which should be at the high level at the timing of the first word as shown in FIG.
As shown in the figure, a state occurs in which the level becomes high at the timing of the third word. This process is described in RDY in FIG.
For the generation part of the synchronization pulse, RDY in FIG.
It can be understood by trying to draw a graph in which the repetition of the pulse is increased relative to that of the chip clock.

When the delay further progresses, the buffer buffer is eventually overwritten. The condition under which overwriting occurs is when the following expression is not satisfied. Therefore, in a state where the following equation is satisfied, the read control circuit 10 detects the state of FIG. 7, sets BUSY to a high level, and waits for data output on the data transmission side to suppress overwriting.

A.times. (Strobe clock width) .gtoreq.B.times. (Chip clock width) -C + D Here, A is the number of buffer buffers per transaction, and in this embodiment, 4 is the number of synchronization stages, and B is the number of synchronization stages. In this embodiment, two stages of flip-flops 8 and 9 are provided.
C is the difference between the strobe clock and the chip clock, which is 1 at the maximum, and D is the delay of the read start from the chip clock.

According to this embodiment, in the above equation, A = 4,
Since B = 2 and the maximum of C is 1, overwriting occurs when the value of D becomes 3. The timing of FIG. 7 appears when the value of D is 2. At this time, since overwriting has not yet occurred, overwriting can be suppressed by detecting this, setting BUSY to a high level, and waiting for data output on the data transmission side.

Next, the details of the above operation will be described in detail by disclosing details of the read control circuit 10. FIG.
FIG. 3 is a detailed block diagram of the read control circuit 10, which includes a count storage counter 20, a read address counter 21, a bit counter 22, a decoder 23, and a busy signal generation circuit 24.
And an OR gate 25. FIG. 4 is a time chart showing the operation of each circuit in FIG.

The count storage counter 20 is a counter for storing the number of RDY synchronization pulses, that is, the number of input transactions, and is incremented by the RDY synchronization pulse and decremented by the end notification from the decoder 23.

The OR gate 25 outputs the logical sum of the value of the count storage counter 20 and the RDY synchronization pulse as the count EN. The read address counter 21 counts EN
Is incremented cyclically between 1 and 6, while the count EN stops at "0". The output of the read address counter 21 is supplied to the selector 12 as a read address.

The count EN is also counted by a 2-bit counter 22, and its output is supplied to a decoder 23 and a busy signal generating circuit 24. When the count value of the 2-bit counter 23 becomes 3, the decoder 23 outputs an end signal to the number-of-times storage counter 20. In addition, the busy signal generation circuit 24 determines that the above-mentioned condition, that is, the number-of-times storage counter 20 stores “1” in FIG. 4 and that the 2-bit counter 22 stores “2” or “3” ( BUSY is generated at the time of (3).

Next, another embodiment of the present invention will be described. However, this embodiment differs from the embodiment in which the BUSY generation logic has been described in detail above and is shown in FIG.

In this example, in addition to the input data, a start bit indicating the first word of the transaction and an end bit indicating the last word are provided in the buffer buffer. These are attached to each of the buffer buffers 1, 2, 3, 4, 5, and 6 in the first embodiment. When writing to the buffer buffers 1, 2, 3, 4, 5 and 6, if the first word of the transaction, the start bit is set to the high level. If it is the last word of the transaction, the end bit is set to high level. These bits are read out simultaneously with the data when reading out from the buffer buffer.

Here, when the start bit or the end bit is not at the high level and the RDY synchronizing pulse is at the high level, overwriting may occur. Waits for data output to suppress overwriting. The case where the start bit or the end bit is not at the high level means that the busy signal generation circuit 24 shown in FIG.
Is equivalent to setting the time when the 2-bit count value of the 2-bit counter 22 (see FIG. 4) is “1” or “2” as the condition for generating BUSY.

In structure, the function of outputting BUSY is excluded from the read control circuit 10 in FIG. Instead, looking at the read data output from the selector 12, the start bit or the end bit is set to "1".
And a circuit that outputs BUSY when the number-of-times storage counter 20 outputs “1” is provided. The number storage circuit 20 uses one of the read control circuits.

In this embodiment, overwriting can be predicted in advance, so that the same effect as in the first embodiment can be obtained. Moreover, even if the number of words in one transaction is variable, the system performance can be improved since the number of words can be dealt with.

[0040]

According to the present invention, the data transmission side is notified by recognizing the state immediately before overwriting even when the writing speed to the buffer buffer is faster than the reading speed. By waiting for the data transfer, it is possible to prevent the data in the buffer buffer from being lost, and to obtain the first effect that the reliability of the device can be improved.

Further, since a state immediately before overwriting can be predicted without using a large-scale counter or the like, there is also a second effect that a circuit / device configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a read control circuit 10 in FIG. 1;

FIG. 3 is a time chart of the asynchronous data transfer control device shown in FIG. 1;

FIG. 4 is a time chart of the read control circuit 10 shown in FIG. 2;

FIG. 5 is a conceptual diagram showing data delay.

FIG. 6 is a diagram for explaining a signal shift due to synchronization.

FIG. 7 is a diagram showing a timing for detecting overwriting to a buffer buffer;

FIG. 8 is a block diagram showing features of another embodiment of the present invention.

FIG. 9 is a block diagram showing an example of a conventional asynchronous transfer control circuit.

[Explanation of symbols]

 1-6 buffer buffer 7-9 flip-flop 10 read control circuit 11 write control circuit 12 selector 13 inverter 14 AND gate 20 count counter 21 read address register 22 2-bit counter 23 decoder 24 busy signal generation circuit 25 OR gate

Claims (6)

[Claims] 1. An asynchronous data transfer control device for converting an input data rate to an output data rate, means for detecting in advance an overwrite to a buffer buffer for performing the rate conversion, and detecting the overwrite of the input data. An asynchronous data transfer control device comprising: means for transmitting an input to a side; and suppressing overwriting to the buffer buffer. 2. An asynchronous data transfer control device for converting the speed of input data and outputting the data asynchronously and sequentially, comprising: a buffer buffer for storing the input data; and a buffer for storing the input data in synchronization with a write clock. A write control circuit for sequentially writing to the buffer buffer; a synchronization circuit for generating a read synchronization pulse from a read preparation pulse synchronized with the write clock; and a read clock asynchronous with the write clock; and the read synchronization signal. In response to the above, a read address for reading the input data stored in the buffer buffer is generated, and an overwrite to the buffer buffer is detected in advance, and the detection is performed by the input of the input data. An asynchronous data transfer device, comprising: 3. An asynchronous data transfer control device for controlling data transfer in transaction units, wherein the read control circuit is incremented by the read synchronization pulse,
A count storage counter that is decremented by the end notification; an OR gate that outputs a logical sum of the count value of the count storage counter and the read preparation pulse as a count EN; and a buffer of the buffer buffer while the count EN is “1”. The number of stages is cyclically incremented, and the increment of the count EN to "0" is stopped. The output is the read address counter which is the read address and the number of data in the transaction in response to the count EN. A bit counter that counts cyclically, a bit counter that outputs an end signal to the number-of-times storage counter when the count value of the bit counter 23 reaches a final value, the number-of-times storage counter stores “1”, and ,
3. The asynchronous data transfer device according to claim 2, further comprising: a busy signal generation circuit that generates the BUSY when the count value of the bit counter is immediately before the final value. 4. An asynchronous data transfer control device for converting the speed of input data to output asynchronously and sequentially, wherein said input data and a start bit indicating whether said input data is a first word or a last word. A buffer buffer for storing an end bit, a write control circuit for sequentially writing the input data together with the start bit or end bit to the buffer buffer in synchronization with a write clock, and a read preparation pulse synchronized with the write clock. A synchronization circuit that generates a read synchronization pulse from the write clock and an asynchronous read clock; and a read address for reading input data stored in the buffer buffer in response to the read synchronization signal. A read control circuit for generating A BUSY notification circuit for detecting in advance the overwriting to the buffer buffer based on the start bit or the end bit at the time of reading, and transmitting the detection to the input data input side. Data transfer device. 5. An asynchronous data transfer control method for converting the speed of input data and outputting the data asynchronously and sequentially, comprising: a step of sequentially writing the input data to a buffer buffer in synchronization with a write clock; Generating a read synchronization pulse from a read preparation pulse synchronized with the read clock and a read clock asynchronous with the write clock; reading input data stored in the buffer buffer in response to the read synchronization signal Generating a read address for the buffer buffer, detecting in advance overwriting to the buffer buffer, and transmitting the detection to the input data input side. 6. An asynchronous data transfer control method for converting the speed of input data to output asynchronously and sequentially, wherein the input data and the input data are a first word or a last word in synchronization with a write clock. A step of sequentially writing a start bit or an end bit indicating whether to the buffer buffer; a step of generating a read synchronization pulse from a read preparation pulse synchronized with the write clock; and a read clock asynchronous with the write clock; Generating a read address for reading the input data stored in the buffer buffer in response to the read synchronization signal; and reading the buffer buffer based on the start bit or end bit when reading the buffer buffer. To detect overwriting in advance, and Asynchronous data transfer method, wherein the asynchronous data transfer input of the input data is equal to or a procedure to tell the side.