JP2001184256A - System lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To freely set the address of a built-in register. SOLUTION: This system LSI is provided with a CPU with a built-in register and a peripheral circuit with the built-in register. This system LSI is also provided with decoders 51-56 for receiving the address data of an address bus, and for instructing the pertinent registers of registers A1-A6 to be made accessible, a data converting circuit 41 for receiving addresses 51-56 to be set in the registers from the outside part, and a data transferring circuit 42 for setting the correspondence of the addresses received by the data converting circuit 41 to the registers A1-A6 in the decoders 51-56.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system LSI having a CPU having a built-in register and a peripheral circuit having a built-in register, wherein the address of each register can be variably set.

[0002]

2. Description of the Related Art Conventionally, in a system LSI of this kind, whether a register address is fixedly set,
The base address can be variably set for the entire register space.

In a system LSI having a fixed register address, since the register addresses are different in different system LSIs, the same software resource cannot be used, and the software must be changed.

Therefore, in order to improve the performance of the system LSI and to use it without changing the software, it is necessary to replace the registers of the system LSI with the improved performance with the registers provided in the old system LSI. It was necessary to take over the address, and software had to be considered at the stage of designing and manufacturing the system LSI.

On the other hand, even in a system LSI in which the base address can be variably set, the register space can only be changed as a whole, and the relative address between the registers cannot be freely changed. It cannot solve the above-mentioned problems.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional system LSI, and its object is to allow the address of a built-in register to be freely set. Accordingly, it is an object of the present invention to provide a system LSI which can eliminate the need to change software resources.

[0007]

[0007] A system L according to the present invention.
In a system LSI including a CPU having a built-in register and a peripheral circuit having a built-in register, a control means for receiving address data of an address bus and instructing the corresponding register in the register to be accessible; An address fetching unit for fetching an address to be set in each of the registers; and a register address setting unit for setting the correspondence between the address fetched by the address fetching unit and the register in the control unit. . According to the above configuration, the contents of the control for instructing the register can be changed to change the address of the register.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A system LSI according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a system LSI-A according to an embodiment of the present invention. This system LSI includes registers A1, A2, and A3,
A PU 11 and a serial IO 12, a memory control unit 13, and a parallel IO 14 are provided as peripheral circuits. The serial IO 12 has a register A4, and the memory control unit 13 has a register A4.
5, and the parallel IO 14 is provided with a register A6.

In this system LSI-A, addresses as shown in FIG. 2 are currently set in the registers A1 to A6. On the other hand, in order to execute the software 10, the register IDs shown in the table of FIG. 6 correspond to the columns A1 to A6 and the address values described in the data column in the ROM correspond to the registers A1 to A6. A
Must be set to 6.

A system LSI-B according to a second embodiment shown in FIG. 3 includes a CPU 21 having registers B1 to B4 built therein and a serial IO2 as a peripheral circuit.
2, a memory control unit 23 and a DMAC (direct memory controller) 24 are provided. The serial IO 22 includes registers B5 and B6, the memory control unit 13 includes a register B7, and the DMAC 24 includes a register B8.

In this system LSI-B, addresses as shown in FIG. 4 are currently set in the registers B1 to B8. On the other hand, in order to execute the software 10, the register IDs shown in the table of FIG. 6 correspond to the columns B1 to B6, and the address values described in the data column in the ROM correspond to the registers B1 to B6. B
Must be set to 6.

The above system LSI-A and system LS
The IBs are system LSIs having the same architecture but differing in some functions. These system LSIs
-A and the system LSI-B, the register A1 and the register B1 are registers having the same function, the register A2 and the register B2 are registers having the same function, and the register A3 and the register B3 are the same. And a register A
5 and the register B7 are registers having the same function. The registers B4, B6, and B8 are stored in the system LS.
This is an LSI newly added to IB.

The above system LSI-A and system LS
The IB is provided with a configuration for variably setting the address of each register, as shown in FIG. The configuration example in FIG. 5 shows the system LSI-A, and the same configuration is also applied to the system LSI-B to the register B1.
To B8.

As shown in FIG. 5, a system LSI-
A includes a data conversion circuit 4 for connecting the ROM 40 to the outside.
The data conversion circuit 41 is connected to a data transfer circuit 42. On the other hand, the registers A1 to A6 in the system LSI-A shown in FIG. 1 are provided with decoders 51 to 56, respectively.

The decoders 51 to 56 decode the addresses arriving from the address bus 5 and detect whether or not the corresponding addresses of the registers A1 to A6 are connected to each other. Is accessible. The decoders 51 to 56 receive the address transferred from the data transfer circuit 42 and receive the setting as the address of the register to which they are connected.

Registers A1-A are stored in the ROM 40 so that the system LSI-A can execute the software A.
In order to set an address for the A6, A1 to A6, which are "register IDs of the system LSI-A" in the table of FIG.
The address to be set is stored as ROM data. For example, an address “0X100” is stored as ROM data corresponding to the ROM address A1,
"0X104" is ROM corresponding to ROM address A2
Stored as data, hereinafter referred to as ROM address A6.
Address values as shown in the figure are stored as ROM data.

The system LSI-A having the above configuration is shown in FIG.
The ROM 40 is incorporated in a system such as a computer with the ROM 40 connected as shown in FIG. 7, and when power is turned on, initialization is performed in accordance with the sequence shown in FIG. That is, when the power is turned on (Power on), the system LSI-A
The data conversion circuit 41 includes register IDs A1 to A1
With 6 as the address of the ROM 40, the data stored corresponding to the address is read (S1). For example, first,
The data “0” stored in the address A1 of the ROM 40
X100 "is read out and sent to the data transfer circuit 42.

The data transfer circuit 42 sets the received data "0X100" to the decoder 51 corresponding to the register A1. Next, the data conversion circuit 41 converts the data “0X104” stored at the address A2 into RO data.
The data is read from M40 and sent to the data transfer circuit 42. The data transfer circuit 42 receives the data “0X1
04 "is set in the decoder 52 corresponding to the register A2. Hereinafter, similarly, the address A6 of the ROM 40
The same operation as described above is performed until the data is sequentially read out and set in the decoder 56 corresponding to the register A6.

When the above operation is completed, for example, the data transfer circuit 41 sends an END signal to the power-on reset circuit for the CPU 11 (S2). The power-on reset circuit that has received this resets the CPU 11 (S3), and the CPU 11 starts operating in response to this (S4).

By the time the CPU 11 starts operating, the registers A1 to A1 of the system LSI-A are
6, the respective addresses shown in the data in the ROM corresponding to the register IDs A1 to A6 in FIG. 6 are set, and the register addresses for executing the software 10 are set. Has been completed.

The above software 1 is installed in the system LSI-B.
0, the register IDs B1 to B
A ROM is prepared in which 8 is a ROM address and the data of the ROM is an address corresponding to register IDs B1 to B8. That is, in the above ROM, B1 to B8, which are the "register IDs of the system LSI-B" in the table of FIG. 6, are used as ROM addresses, and correspondingly, "0X100", "0X104", "0X10"
8 "," 0X10C "..." 0XC00 "are used as ROMs. This ROM is connected to the data conversion circuit 41 of the system LSI-B, and when the power is turned on, the operation as described for the system LSI-A with reference to FIG. 7 is performed.

As described above, the common software 10 can be used in the system LSI-A and the system LSI-B, and there is no need to change the software regardless of the change in the system LSI. In some software, even if the address allocation to the register having the same function is different, the address can be set by connecting the ROM corresponding to the above address allocation to the system LSI in this embodiment, and the software can be changed. It becomes unnecessary. In addition, by unifying address assignment for some functions of the system LSI, it is possible to share a unified internal address map during software development, and to respond to diversion and modification of software assets. It will be easier.

In the above embodiment, the number of decoders corresponding to registers is provided. However, a decoder common to all registers is provided, and this decoder decodes an address on an address bus to enable access to the corresponding register. May be adopted.

[0024]

As described above, according to the system LSI of the present invention, the contents of the decoder designating the register can be changed to make the register address variable. Has the advantage that the setting can be changed by changing the register address.

[Brief description of the drawings]

FIG. 1 shows a system LS according to a first embodiment of the present invention.
FIG.

FIG. 2 is a system LS according to the first embodiment of the present invention.
The figure which shows the address value set when it exists in the register of IA.

FIG. 3 shows a system LS according to a second embodiment of the present invention.
FIG.

FIG. 4 shows a system LS according to a second embodiment of the present invention.
The figure which shows the address value set when it exists in the register of IB.

FIG. 5 is a system LS according to the first embodiment of the present invention.
FIG.

FIG. 6 shows a system LS according to the first embodiment of the present invention.
IA and system LS according to second embodiment of the present invention
FIG. 9 is a diagram showing register address values for enabling IB to execute common software A;

FIG. 7 shows a system LS according to the first embodiment of the present invention.
5 is a timing chart when an address is set to a register in I.

[Explanation of symbols]

 11, 21 CPU 12, 22 Serial IO 13, 23 Memory control unit 14 Parallel IO 24 DMAC 40 ROM 41 Data conversion circuit 42 Data transfer circuit 51-56 Decoder

Claims (3)

[Claims] In a system LSI including a CPU having a built-in register and a peripheral circuit having a built-in register, control means for receiving address data of an address bus and instructing the corresponding register in the register to be accessible; Address acquisition means for taking in an address to be set in each of the registers from outside, and register address setting means for setting the correspondence between the address taken in by the address taking means and the register in the control means. System LS
I. 2. The system LSI according to claim 1, wherein said address fetching means fetches data stored in an externally connected ROM as an address. 3. The system LSI according to claim 1, wherein the address receiving circuit fetches an address when the power of the system is turned on.