KR101352140B1 - Data communication system - Google Patents

Abstract

A data communication system is disclosed. According to an embodiment of the present invention, at least one subprocessor or at least one main processor and at least one subprocessor connected to the main processor through a SPI (Serial Peripheral Interface) scheme and performing an operation corresponding to an instruction transmitted from the main processor And a peripheral device, wherein the connection via the SPI method is performed by one or more bus lines, wherein the one or more bus lines include a master in slave out (MISO) and a master out slave for data transmission. A slave select line (SS) for signal transmission for selecting one of an in-line (MOSI; Master Out Slave In), the subprocessor, or the peripheral device into an operable state, and branching from the select line, A signal transmitted through the selection line to the selected subprocessor or peripheral device; The data communication system is provided, including; (SPI Clock SCK) interrupt line (Intr), and a clock transmission line for transmitting a state machine (State Machine) initialization signal.

Description

DATA COMMUNICATION SYSTEM}

The present invention relates to a data communication system, and more particularly, to a data communication system that enables multiple processors to be connected without additional hardware.

In recent years, efforts to construct high-performance sensor nodes to support increasingly complex applications of wireless sensor networks have been increasing. In general, most sensor nodes use a single processor method. Since low power is a priority requirement, an 8-bit or 16-bit processor (eg, ATMega128, MSP430F1611, etc.) is mainly used. In some high-performance sensor nodes, a single chip of high-speed 16-bit or 32-bit (eg XYZ's OKI ML67Q5002) was also used.

On the other hand, in the sensor node that requires a high level of performance, a design method using multiple processors has been used. For example, in the case of a leaf node (LEAP) type sensor node, a 16-bit processor, the MSP430 and a PXA270 processor, and a pasta (PASTA) type processor, the 8-bit processors are configured. In the leaf method, processors are simply connected, and the concept of the system bus does not exist. In the past method, some common interfaces are provided, but the system bus that can simultaneously connect the processor and peripheral devices is not provided. It was.

Currently, there is an inter-integrated circuit (I2C) as an interface to connect processors or devices as a multi-master serial bus structure and to guarantee scalability. However, since most peripheral devices used in recent sensor nodes only have a serial peripheral interface (SPI), it can be difficult to connect the processor and the peripheral device to the same interface. In addition, the internal integrated circuit interface supports a speed of 100 kbps in the standard mode, which is also 10 times slower than the SPI connection. On the other hand, there are disadvantages in terms of power consumption, and it is too much to be used as a system bus for low power and high performance sensor nodes.

The present invention is to solve the above-mentioned problems of the prior art, and provides a system bus for communication between the processor or the processor and the peripheral device for implementing a high-performance sensor node as a multi-processor, using the SPI method without any additional hardware The purpose is to enable connection in a master / slave manner.

Another object of the present invention is to enable low power high performance data communication by allowing the state machine to initialize and operate only when a defined instruction is received from the main processor when connected in a master / slave fashion.

According to an embodiment of the present invention for achieving the above object, is connected to the main processor and the main processor through a SPI (Serial Peripheral Interface) scheme, and performs an operation corresponding to the command transmitted from the main processor One or more subprocessors or one or more peripheral devices, wherein the connection via the SPI method is made by one or more bus lines, the one or more bus lines, Master In Slave Outline (MISO; Master In) for data transmission Slave Out (Slave Out) and Master Out Slave In (MOSI; Master Out Slave In), a slave select line (SS) for signal transmission to select one of the subprocessor or the peripheral device and put it into an operational state, The signal is branched from the selection line, and the signal transmitted through the selection line is selected. Interrupt line (Intr), and a clock transmission line for transmitting a probe processor or state machine peripherals (State Machine) initialization signal, a data communication system including a (SCK SPI Clock) is provided.

The at least one bus line may further include a data standby line (Data Ready) for signal transmission indicating that there is data to be transmitted from the subprocessor or the peripheral device to the main processor.

The command may be any one of a “read”, “write”, and “execute” command.

The "read" command is transmitted in the form of "read (SPIdevID, addr, len, value)", and when the command of this type is transmitted, the subprocessor or peripheral device corresponding to the address of "SPIdevID" is " perform an operation of reading a "value" value having a length of "len" present at an address of addr, and the "write" command is transmitted in the form of "write (SPIdevId, addr, len, value)" When the command of the above form is transmitted, the subprocessor or the peripheral device corresponding to the address of "SPIdevId" writes a "value" value having a length of "len" in the address of "addr", and the " "Exec (SPIdevId, command, paramlen, param)" is transmitted in the form of "exec (SPIdevId, command, paramlen, param)", and when the command of the above form is transmitted, the subprocessor or peripheral device corresponding to the address of "SPIdevId" is "paramlen". A service named "command" with reference to a parameter named "param" with a length of It may perform the operation to be performed.

The command may be transmitted in a data format including a length of data in which a variable necessary for performing the operation is recorded, an opcode in which the command is recorded, and the data.

The subprocessor or the peripheral device may transmit a data format including the length of the result value of the operation and the result value to the main processor.

According to the present invention, a high performance sensor node may be implemented through multiple processors, and a data communication system may be implemented in a master / slave manner using an SPI method without any additional hardware.

In addition, according to the present invention, when connected in a master / slave manner between processors, since the state machine is initialized and operated only when a command defined from the main processor is received, low power high performance data communication is possible.

1 is a view showing the configuration of a data communication system according to an embodiment of the present invention.
2 is a diagram illustrating a connection between a main processor and a subprocessor or a peripheral device according to an exemplary embodiment of the present invention.
3 is a diagram illustrating a data frame format of an instruction transmitted from a main processor according to an embodiment of the present invention.
4 is a diagram illustrating an example of a state machine that a subprocessor or a peripheral device has in accordance with an embodiment of the present invention.
5 is a diagram illustrating a data frame format transmitted from a subprocessor or a peripheral device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

[Preferred Embodiment of the Present Invention]

Data Communication System Configuration

1 is a view showing the configuration of a data communication system according to an embodiment of the present invention. The data communication system shown in FIG. 1 may be a data communication system used for a sensor node, but may be used for other network communication.

Referring to FIG. 1, the data communication system of the present invention may include a plurality of subprocessors 120 and a plurality of peripheral devices 130 connected to the main processor 110 and the main processor 110. Can be. In FIG. 1, one main processor 110, M subprocessors 120, and N peripheral devices 130 form a data communication system. In addition, although the main processor 110 and the sub-processor 120 are shown separately, this is for convenience of description only, and a processor having the same internal configuration may be used as the main processor 110 or the sub-processor 120. have.

The subprocessor 120 and the peripheral device 130 may be connected to the main processor 110 through serial communication. According to one embodiment of the present invention, such serial communication may be a serial communication method of the SPI (Serial Peripheral Interface) method.

Communication between the main processor 110 and the subprocessor 120 or between the main processor 110 and the peripheral device 130 is performed through a one-to-one communication method.

2 is a diagram illustrating a hardware communication method between the subprocessor 120 or the peripheral device 130 and the main processor 110 according to an exemplary embodiment of the present invention. Although FIG. 2 illustrates an example in which the main processor 110 and the subprocessor 120 are connected through the SPI communication method, the communication method between the main processor 110 and the peripheral device 130 may be similarly implemented. have.

Referring to FIG. 2, the SPI communication between the main processor 110 and the subprocessor 120 may be performed through one or more lines. In this case, the main processor 110 and the subprocessor 120 may be master / master. It may be connected in a slave communication manner.

The Master In Slave Out (MISO) and the Master Out Slave In (MOSI) are lines used for data transmission.

Meanwhile, the main processor 110 should select one or more subprocessors 120 and one or more peripheral devices 130, which are communication targets, or a peripheral device 130. The input is input to the selected subprocessor 120 or the peripheral device 130 through a slave select line (SS). For example, when a specific subprocessor 120 is selected as a communication target by the main processor 120, a selection signal is input to the corresponding subprocessor 120 through the slave selection line SS, and the corresponding subprocessor 120 is selected. ) May be operable.

According to an embodiment of the present invention, the signal input to the slave select line SS is branched to the interrupt line Intr, which is another line branched from the slave select line SS, to the subprocessor 120 through another port. Can be entered. The signal input to the interrupt line Intr serves to release the wakeup state when the subprocessor 120 is in the sleep state, and the internal state machine of the subprocessor 120 It can also play a role of initializing a state machine. That is, when the slave selection signal is input, the subprocessor 120 enters a wake-up state, and the state machine is initialized to an operable state.

The master in slave out line (MISO) and the master out slave in line (MOSI), which are referred to as data transfer buses, are connected between the main processor 110 and the subprocessor 120, and the slave selection, which is called an address allocation bus, is selected. When the line SS is connected, a clock signal is supplied to the subprocessor 120 through a clock transmission line SCK. This clock signal is a signal indicating the timing of data transmission from the main processor 110 to the subprocessor 120. At this time, if there is data to be transmitted from the subprocessor 120 to the main processor 110, an additional data waiting line for transmitting a signal indicating this state from the subprocessor 120 to the main processor 110 (Data) Ready) may be further provided. That is, when there is data to be transmitted to the main processor 110, the subprocessor 120 transmits a corresponding signal through a data standby line (Data Ready), and the main processor 110 continuously checks whether a signal is received. The signal may be received by a polling method, which is a software method, or an interrupt method, which is a hardware method of checking only a change of a received signal. The data ready line is not an essential component of the present invention.

As described above, the communication scheme described with reference to FIG. 2 may be equally implemented between the main processor 110 and the peripheral device 130 as well as the main processor 110 and the subprocessor 120.

Hereinafter, a method of transmitting data and instructions from the main processor 110 to the subprocessor 120 or the peripheral device 130 will be described in detail.

Send data and instructions

3 is a diagram illustrating a data frame format in which an instruction is transmitted from the main processor 110 to the subprocessor 120 or the peripheral device 130.

Referring to FIG. 3, it can be seen that the main processor 110 sequentially transmits a length of data to be transmitted, an operation code (opcode) as an instruction, and data.

The subprocessor 120 or the peripheral device 130 performs an operation corresponding to an instruction transmitted in an opcode format with respect to data transmitted from the main processor 110.

Table 1 below shows a command transmitted from the main processor 110 to the subprocessor 120 or the peripheral device 130 and a description thereof.

command parameter read (SPIdevId, addr, len, value) SPIdevId: device address within the SPI bus
addr: address in the SPIdevId device
len: the length of the data in addr
value: The variable whose data in addr is stored and returned write (SPIdevId, addr, len, value) SPIdevId: device address on the SPI bus
addr: address in SPIdevId device,
len: the length of the data in addr
value: variable containing the value to add to the addr exec (SPIdevId, command, paramlen, param) SPIdevId: device address on the SPI bus
command: The service name you want to run on the SPI device
paramlen: the length of the parameter
param: parameters required by command

"read", "write" and "exec" commands are commands to read, write and execute respectively.

Each such instruction corresponds to an opcode in FIG. 3. Each command causes the subprocessor 120 or the peripheral device 130 to perform an operation corresponding to the command on the data transmitted after the opcode.

When the subprocessor 120 or the peripheral device 130 receives a command “read”, the subprocessor 120 or the peripheral device 130 reads data. For example, upon receiving the command read (SPIdevId, addr, len, value), the subprocessor 120 or the peripheral device 130 corresponding to the address of “SPIdevID” exists at the address of “addr” within the device. Reads a "value" value having a length of "len".

In addition, when the command "write" is received, the data write operation is performed. For example, upon receiving the command write (SPIdevId, addr, len, value), the subprocessor 120 or the peripheral device 130 corresponding to the address of “SPIdevId” is assigned to the address of “addr” within the device. Write the value "value" with length len ".

On the other hand, upon receiving the command "exec" it performs an operation of executing a predetermined service. For example, when the command exec (SPIdevId, command, paramlen, param) is received, the subprocessor 120 or the peripheral device 130 corresponding to the address of "SPIdevId" is called "param" having a length of "paramlen". Runs a service named "command" by referring to its parameters.

For example, the command transmitted from the main processor 110 to the subprocessor 120 or the peripheral device 130 may be in the following data frame format.

Master → Slave

if opcode == READ

data: addr

else if opcode == WRITE

data: addr.value

else if opcode == EXEC

data: command.param

In other words, when the opcode is "read", the "addr" parameter is recorded and transmitted in the subsequent data, and in the case of "write", the "addr" and "valie" parameters are recorded in the data. In the case of "exec", "command" and "param" parameters may be recorded and transmitted in subsequent data.

However, this is only an example, and the data frame format of the instruction transmitted from the main processor 110 may be different. For example, all of the "addr", "len", and "value" parameters may be recorded and transmitted in data transmitted after an opcode of "read".

Hereinafter, when the specific subprocessor 120 or the peripheral device 130 is selected by the main processor 110 and a command is transmitted, a method of operating in the subprocessor 120 or the peripheral device 130 will be described. Shall be.

State machine

When the main processor 110 and the subprocessor 120 or the peripheral device 130 are connected, the main processor 110 and the subprocessor 120 or the main processor 110 and the peripheral device 130 are software / client. It works in a way.

As described above, the main processor 110 may select one of the plurality of subprocessors 120 or the peripheral device 130. This selection may be performed by applying a selection signal to the specific subprocessor 120 or the peripheral device 130 through the slave selection line SS. The subprocessor 120 or the peripheral device 130 to which the selection signal is applied is in an operable state. As described above, the select signal transmitted through the slave select line SS may be branched and applied to the interrupt line Intr, which may be used to interrupt the state machine of the subprocessor 120 or the peripheral device 130. Can be initialized. Initialization may occur at a point before the first valid byte is transmitted from the main processor 110. Initialization through the selection signal may be performed at the time when the slave selection starts and when the slave selection ends.

After the subprocessor 120 or the peripheral device 130 is selected, the command is transmitted from the main processor 110 in the form shown in FIG. 3. The subprocessor 120 or the peripheral device 130 receiving the command checks whether the transmitted data is a valid frame using its own state machine and moves to the state corresponding to the received command to perform the corresponding routine. The result is returned to the main processor 110 in accordance with the state machine.

4 is a diagram illustrating an example of a state machine that the subprocessor 120 or the peripheral device 130 has.

Referring to FIG. 4, when the selection signal is transmitted through the slave selection line SS, the state machine is initialized (S400). The length of the data transmitted from the main processor 110 may be a fixed length or a variable length. In the case of a variable, the length of the data is received after the information about the length of the data is received and determined. Move to (S410). Thereafter, when the command "exec" is transmitted according to the command transmitted from the main processor 110, the command state ("cmd") moves to the command "param" transmitted with the command with reference to " command is executed (S420). As mentioned above, the parameters "command" and "param" may be transmitted together with "exec", more specifically as data following an opcode of "exec". When the service execution result value is generated, the length of the corresponding result value is returned to the main processor 110 and moved to the return state ("ret") (S430), and subsequently the generated result value is returned and subsequently initialized again. Move to (S400). On the other hand, if the command transmitted from the main processor 110 is "read" or "write", it moves from the length state ("length") to the address state ("addr") (S440). Thereafter, the mobile station moves to the reception state ("rx") to read a variable at a corresponding address or write a variable at a corresponding address (S450). The variable to be read or written may be transmitted together with an instruction from the main processor 110. After performing the operation may be reset again (S400).

Meanwhile, the subprocessor 120 or the peripheral device 130 may notify that the command is normally received by returning the command transmitted from the main processor 110. In detail, when the "exec" command is received, the command state ("cmd") is moved to the transmission state ("tx") for returning the command received (S460), the data returned, that is, the main processor 110 After returning the length of the command transmitted from the main processor 110 to the return state ("ret") (S430), the corresponding data can be returned subsequently. At this time, it may move back to the initialization state (S400). In addition, even when "read" and "write" commands are received, the controller moves to the transmission state ("tx") (S460), returns the length of the command transmitted from the main processor 110 to the main processor 110, and returns. After moving to the state "ret" (S430), the corresponding data is subsequently returned.

Meanwhile, according to an embodiment of the present invention, a data waiting line (see FIG. 2) may be connected between the main processor 110 and the subprocessor 120 or the peripheral device 130. In this case, The subprocessor 120 or the peripheral device 130 may transmit a data wait signal to the main processor 110 through a data wait line (Data Ready) to inform that there is data to be transmitted. The signal transmitted through the data waiting line (Data Ready) is reset after data is transmitted to the main processor 110. At the same time as the reset, the subprocessor 120 or the peripheral device 130 checks whether there is additional data to be transmitted. If there is additional data to be transmitted, the subprocessor 120 or the peripheral device 130 may prepare the data in a state in which data can be transmitted and then transmit the corresponding signal through a data standby line. On the contrary, the main processor 110 may check whether there is data to be transmitted from the subprocessor 120 or the peripheral device 130 through the change of the signal transmitted through the data standby line.

The subprocessor 120 or the peripheral device 130 may transmit data to the main processor 110 in a predetermined form. In FIG. 5, the subprocessor 120 or the peripheral device 130 may transmit data to the main processor 110. A diagram illustrating a data frame format for transmitting data to the main processor 110.

Referring to FIG. 5, the subprocessor 120 or the peripheral device 130 may sequentially transmit a length and a result value of data to be transmitted. The length of the data to be transmitted is the length of the result value, and the result value means the result value of performing the corresponding routine according to the command transmitted from the main processor 110. That is, the main processor 110 first reads the length of the result value to be transmitted by the subprocessor 120 or the peripheral device 130, and then reads data as much as the length. If no signal is transmitted from the data ready line, the main processor 110 is sufficient to prepare a result value for the subprocessor 120 or the peripheral device 130 to return to the main processor 110. After waiting for time, data transmitted in the data frame format shown in FIG. 5 can be read.

After the main processor 110 reads all the result values transmitted from the subprocessor 120 or the peripheral device 130, the communication may be completed by resetting the selection signal transmitted through the slave selection line SS.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Therefore, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, I will say.

110: main processor
120: subprocessor
130: peripheral device

Claims (6)

Main processor; And
Is connected to the main processor through a SPI (Serial Peripheral Interface) scheme, and includes one or more subprocessors or one or more peripheral devices for performing an operation corresponding to the instructions transmitted from the main processor,
The connection through the SPI scheme is made by one or more bus lines, and the one or more bus lines
Master In Slave Out (MISO) and Master Out Slave In (MOSI) for data transmission;
Slave Select (SS) for signal transmission to select one of the sub-processor or the peripheral device to switch to an operable state;
An interrupt line branched from the slave select line and transmitting a signal transmitted through the select line as a state machine initialization signal of the selected subprocessor or a peripheral device; And
A data communication system comprising a clock transmission line (SCK; SPI Clock). The method of claim 1,
The at least one bus line further includes a data standby line (Data Ready) for signal transmission indicating that there is data to be transmitted from the subprocessor or the peripheral device to the main processor. The method of claim 1,
The command is any one of a "read", "write", "execute" command. The method of claim 3,
The "read" command is transmitted in the form of "read (SPIdevID, addr, len, value)", and when the command of this type is transmitted, the subprocessor or peripheral device corresponding to the address of "SPIdevID" is " perform an operation of reading a "value" value having a length of "len" present at an address of addr ",
The "write" command is transmitted in the form of "write (SPIdevId, addr, len, value)", and when the command of this type is transmitted, the subprocessor or peripheral device corresponding to the address of "SPIdevId" is " write the value "value" with the length "len" into the address of addr ",
The "execute" command is transmitted in the form of "exec (SPIdevId, command, paramlen, param)", and when the command of this type is transmitted, the subprocessor or peripheral device corresponding to the address of "SPIdevId" is " A data communication system that performs an operation of executing a service called "command" with reference to a parameter called "param" having a length of paramlen ". The method of claim 1,
And the command is transmitted in a data format including a length of data in which a variable necessary for performing the operation is recorded, an opcode in which the command is recorded, and the data. In accordance with claim 1,
The subprocessor or the peripheral device transmits a data format including the length of the result value of the operation and the result value to the main processor.

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