JP2001177591A - Communication equipment with efficiently controlled power supply, control method and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital portable telephone system which stops the supply of power to multiple circuits as much as possible in a prescribed period when data are not transmitted/received and which can supply a symbol clock signal by the same phase as a previous one. SOLUTION: The supply of power to a radio part 102, a reference oscillator 108 and a demodulation part 103 is stopped in the prescribed period when data are not transmitted/received. The most part of the period is measured by a clock signal 134 whose frequency is low and the remaining short period is highly precisely measured by using the demodulation clock signal 133 of the high frequency. When the period terminates, power is supplied to the circuits, to which power supply have been stopped, with a spare time. Since the phase of a symbol clock signal 136 when power supply has been stopped is kept in a counter 143, the symbol clock signal 136 is resumed by the same phase by using the counter 143 when a period elapses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital demodulation circuit including a delay detection circuit, and more particularly to a symbol timing holding circuit for saving power consumption in the demodulation circuit.

[0002]

2. Description of the Related Art In a conventional digital portable telephone device or the like, first, a signal is received by an antenna, and only a signal of a required frequency is selected from the received signals.
Further, the selected signal is demodulated. The demodulated signal is converted into an audio signal, and finally output as audio from a receiver such as a mobile phone.

In a conventional digital portable telephone system, π / 4 shift DQPSK is generally used as a modulation method. A delay detection method may be used as a method for demodulating a signal generated by such a modulation method.

A receiver using the conventional differential detection system is
It comprises a phase detection circuit, a phase difference detection circuit, and a clock recovery circuit. The phase detection circuit detects the phase of the selected signal from the selected signal and the (symbol) clock signal recovered by the clock recovery circuit, and generates a phase signal. The phase difference detection circuit holds the phase signal at a certain timing of the symbol clock signal,
The next phase signal is fetched at the timing of the next symbol clock signal, and the difference between the two phase signals is output as a phase error signal. The clock recovery circuit recovers the symbol clock signal from the phase signal and supplies the symbol clock signal to the phase detection circuit and the phase difference detection circuit as described above.

The selected signal has a phase change of ± π / 4 or ± 3π / 4 at each symbol point, and a digital value is demodulated from the change.

A demodulator having a similar configuration is disclosed in Japanese Patent Laid-Open No. 6-6 / 1994.
398 "and" JP-A-6-261850 ".

[0007]

However, in order to accurately demodulate a signal, the symbol clock signal output from the clock recovery circuit needs to match the symbol timing of the selected signal. .

Therefore, when the power supply to the circuit is stopped during a period other than the required timing when data is received by the intermittent reception method or the like, when the power supply is started thereafter, the timing of the symbol clock signal is set to This will deviate from the symbol timing of the selected signal. In such a case, the selected signal can be received until the clock recovery circuit reacquires the timing (adjusts the timing of the symbol clock signal to the symbol timing of the selected signal). Absent.

For this reason, in such a digital portable telephone, it is necessary to keep only the clock recovery circuit operating even while the power supply to the main circuit is stopped. Further, since the symbol clock signal is generated based on a demodulation clock signal having a higher frequency, it is necessary to operate this demodulation clock signal. Further, since the demodulation clock signal is generated based on a higher reference frequency, it is necessary to operate an oscillation circuit of this reference frequency.

[0010] Leaving many circuits in operation in this way leads to an increase in current consumption. Since the current consumption of the oscillation circuit increases as the frequency increases (in a conventional circuit, the reference frequency is usually 14.4 MHz and the demodulation clock signal is 2.688 MHz).
Operating the oscillation circuit for the demodulation clock signal and the reference frequency signal, in particular, increases current consumption.

Since portable data communication devices such as mobile phones are required to be portable for a long time due to their properties, it is important to reduce current consumption and extend battery life. Problem.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a portable telephone device which can be carried for a long time without replacing a battery while reducing current consumption.

It is a further object of the present invention to provide a portable telephone device capable of reducing current consumption during standby by stopping power supply to a circuit except at the timing of receiving a call signal.

Still another object of the present invention is to provide a portable telephone device capable of reducing power consumption during non-calling and capable of quickly generating an optimum symbol clock signal when calling is resumed.

It is another object of the present invention to provide a symbol timing holding circuit used in a digital portable telephone device and capable of generating a symbol clock signal accurately and quickly when a call is resumed.

Still another object of the present invention is to reduce the time consumed for intermittent reception of radio signals in a communication device such as a digital portable telephone device by using low and high frequencies to reduce current consumption. It is an object of the present invention to provide a time measuring means that can be precisely obtained.

[0017]

According to one embodiment of the present invention, in a communication device for receiving digital data wirelessly, a first oscillator for generating a first oscillation frequency signal having a first frequency is provided. And a second oscillator that generates a second oscillation frequency signal having a second frequency based on the first oscillation frequency signal, and uses the second oscillation frequency signal to generate a symbol clock signal. The generated symbol clock circuit, and when not receiving the digital data, suspends the supply of the second oscillation frequency signal to the symbol clock circuit for a predetermined period to stop generating the symbol clock signal. And controlling the power supply of the first oscillator and the second oscillator to be stopped over a shorter predetermined period within the predetermined period. Having the control unit, when not receiving the digital data, for a predetermined period of time, when not receiving the digital data, control to stop power supply to unnecessary circuits, A symbol clock circuit having a first counter for holding a phase value of the symbol clock signal when the supply of the second oscillation frequency signal is interrupted, and a second oscillation frequency to the symbol clock circuit; When the supply of the signal is restarted, the symbol clock circuit restarts the generation of the symbol clock signal without causing a phase shift by using the phase value held in the first counter. Be composed.

According to the above configuration, the power of unnecessary circuits is cut off during a non-communication, so that the current consumption in the communication device can be reduced. It resumes quickly when needed without causing a phase shift.

According to yet another embodiment of the present invention, the communication device further comprises: a third oscillator for generating a third oscillation frequency signal having a third frequency lower than the second frequency; It is configured to include a timer unit that counts the predetermined period by counting the number of repetitions of the second oscillation frequency signal and the number of repetitions of the third oscillation frequency signal.

With the above configuration, the time until the generation of the symbol clock signal is restarted can be accurately measured with a small current consumption.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The symbol timing holding circuit according to the present invention can be used for holding the timing of a symbol clock signal used for demodulating a digital signal as in a digital portable telephone device, for example. In consideration of this, here, the digital mobile phone device will be described first.

The digital portable telephone device shown in FIG.
Antenna 101, radio unit 102, demodulation unit 103, AFC
Unit 104, clock unit 105, audio processing unit 106, reference oscillator 108, control unit 109, operation unit 110, display unit 1
11, a microphone 112, and a receiver 113.

The digital cellular phone device shown in FIG. 1 first provides a radio signal 102 with a reception signal received via antenna 101. Next, radio section 102 selects a frequency to be received from the received signal, performs frequency conversion, amplifies the result, generates an IF signal, and outputs the IF signal to demodulation section 103. Demodulation section 103 demodulates the IF signal and outputs received data to control section 109.

In a digital portable telephone system, a π / 4 shift DQPSK is used as a modulation method, and a delay detection method and a synchronous detection method are often used as a demodulation method. The demodulation unit 103 includes a delay detection type demodulation circuit. A demodulation circuit using a general delay detection method is described in Japanese Patent Application No. 9-265607.

Next, the control unit 109 processes the received data from the demodulation unit 103 and outputs an audio signal to the audio processing unit 106. The audio processing unit 106 converts the audio signal into an analog signal and transmits the analog signal to the receiver 113. Upon receiving the analog signal, the receiver 113 outputs a sound corresponding to the analog signal.

On the other hand, the sound input from the microphone 112 is converted into a digital signal by the sound processing unit 106, passes through the control unit 109, is modulated by the radio unit 102, and uses a carrier having a predetermined frequency. Transmitted from the antenna 101. Since the transmission processing is not directly related to the present invention, further description is omitted.

The operation unit 110 controls a user interface, and sends user's instructions such as a telephone number to the control unit 109. The display unit 111 performs various displays such as an incoming telephone number.

The clock section 105 normally generates a clock signal for time display or the like. This signal is also used to control the power supply timing of each component for intermittent reception in the present invention.

The reference oscillator 108 generates an accurate frequency used as a reference frequency in the radio unit 102, the control unit 109, the demodulation unit 103, and the clock unit. Since the oscillator 108 is a TCXO (temperature controlled XATL oscillator), the generated frequency is extremely accurate.

The AFC (Automatic Frequency Control) unit 104 controls the reference oscillator 108 so as to match the received frequency of the base station.

Next, referring to FIG.
Will be described in detail.

The phase detector 12 provided in the demodulator 103
1 is IF signal 127, reference frequency (14.4 MHz)
128 and the symbol clock signal 136, and the IF signal 127 at the timing of the symbol clock signal 136.
Is output to the data reproducing unit 122, the phase correcting unit 123, and the clock reproducing unit 124. IF
The signal 127 is transmitted from the radio unit 102 in FIG.
28 is supplied from the reference frequency 108 in FIG. 1, and the symbol clock signal 136 is supplied from the clock recovery unit 124.

The data reproducing section 122 is provided with the phase detecting section 1.
The phase data 129 obtained in step 21 is input, reception data 137 is created, and output to the control unit 109 in FIG.

The phase correction unit 123 performs phase correction on the input phase data 129 and outputs the result as a correction output 130 to the AFC unit 104 in FIG.

The demodulation clock section 125 has a PLL circuit configuration, and has a reference frequency 128 from the reference oscillator 108 shown in FIG.
, The demodulation clock signal 133 (2.688 MHz)
z) is output to the clock reproducing unit 124 and the timer unit 126.

The clock reproducing section 124 divides the frequency of the demodulation clock signal 133 by 128 to generate the symbol clock signal 1
36 (21 kHz) and supplies it to the phase detector 121. The clock recovery unit 124 further performs a data clock signal 1 by dividing the demodulation clock signal 133 by 64.
31 (42 kHz) is output.

The clock reproducing unit 124 adjusts the phase timings of the symbol clock signal 136 and the data clock signal 131 based on the difference between the phase shift amounts of the first half and the second half of the symbol section of the phase data 129, and adjusts these timings. Match the symbol timing of the IF signal 127.

The timer 126 has a clock signal 134.
The clock signal 133 for demodulation is counted, and the control signal 132 is output at intervals corresponding to the count specified by the control unit signal 135 to control the input of the clock signal to the counter in the clock reproducing unit 124.

Comparing the demodulation section 103 of FIG. 2 with the conventional demodulation section 203 shown in FIG. 9, the demodulation section 103 shown in FIG. There is a great difference in that the control signal 132 is output to the unit 124.

Next, the clock reproducing unit 124 shown in FIG. 2 will be described with reference to FIG.

The lag / advance detector 141 is a phase detector 1
21 and the value of the phase data 129 from the clock recovery unit 1
24, the data clock signal 131 generated by the adder 144 is input, and the difference in the amount of phase shift is calculated at the timing of the data clock signal 131 for the first / second half of the symbol section indicated by the symbol clock signal 136. As an advance / delay signal 146 to the UP / DOWN counter 142.

The switch (SW) 145 receives the demodulation clock signal 133 from the demodulation clock unit 125 and the control signal 132 from the timer unit 126 and receives the control signal 1
According to the value of 32, U of the demodulation clock signal 133
The transmission to the P / DOWN counter 142 and the counter 143 is controlled.

The counter 143 is a 7-bit counter that counts a demodulation clock signal (2.688 MHz). The UP / DOWN counter 142 is a counter that is added or subtracted at the timing of the demodulation clock signal according to the instruction of the advance / delay signal 146.

The adder 144 includes a counter 143 and an UP /
The outputs of the DOWN counter 142 are added, and a 7-bit value is output. The seventh bit is the symbol clock signal 13
As 6, it is supplied to the phase detector 121. The sixth bit is output as the data clock signal 131 and is returned to the delay / advance detecting section 141 in the clock reproducing section 124 again, and is supplied to the control section 109 at the same time.

When comparing the clock recovery unit 124 of FIG. 3 with the conventional clock recovery unit 224 shown in FIG. 10, the clock recovery unit 124 generates the demodulated clock signal 133 and
A switch (S) newly controlled by the control signal 132 is provided between the counter 143 and the UP / DOWN counter 142.
W) 145.

Next, a detailed configuration of the timer section 126 shown in FIG. 2 will be described with reference to FIG.

The counter 151 is a counter using the clock signal 134 from the clock unit 105 shown in FIG. 1 as a clock signal. Another counter 153 is a counter that uses the demodulation clock signal 133 from the demodulation clock unit 125 as a clock signal.

The counter 151 is started by a control unit signal 135 from the control unit 109.

Predetermined values are set in advance in the comparator 152 and the comparator 154 via the control signal 135 from the control unit 109.

When the comparator 152 detects that the value set by the control unit 109 and the value of the output 155 of the counter 151 match, the comparator 152 outputs a reset signal 157 to the counter 151 and sets the value of the counter 151 to 0. And the counter 151 is stopped. Further, the comparator 152 outputs a start signal 156 to the counter 153, and starts the counter 153.

When the comparator 154 detects that the value set by the control unit 109 and the value of the output 157 of the counter 153 match, the comparator 154 outputs a reset signal 158 to the counter 153 and sets the value of the counter 153 to 0. And the counter 153 is stopped. Further, the comparator 154 outputs the control signal 132 to the clock reproducing unit 124. As described with reference to FIG.
32 is provided to the switch 145 of the clock recovery unit 124 to control the input of the demodulation clock signal to the counter 143.

The values set in the two counters by the control unit 109 will be described later in detail.

Next, the configuration of the clock unit 105 will be described in detail with reference to FIG.

The oscillator 161 is an oscillation circuit using a crystal oscillator, and is a clock signal 13 having a frequency of 32.768 kHz.
4 is output.

The counter 162 sends an output 165 to another counter 163 every time it counts 2752 clocks using the clock signal 134 as a clock signal.

The counter 163 corresponds to the reference oscillator 10 shown in FIG.
Input reference frequency 128 (14.4 MHz) from 8
It is counted for the interval section of the output 165, and the count result is set as a correction value 164, and the control unit 109
Output to

The reference frequency 128 is very accurate as described above. Although detailed description is omitted here,
Since the AFC unit 104 brings the reference frequency 128 of the reference oscillator 108 closer to the base station frequency based on the correction output supplied from the demodulation unit 103, it is more accurate.

Therefore, when there is a deviation in the frequency of the oscillator 161, the deviation can be grasped by the value of the correction value 164.

Here, the overall operation of the digital portable telephone device according to one embodiment of the present invention will be described with reference to FIG.

First, in step S10, when performing data reception, the control unit 109 starts up power supplies of all necessary circuit blocks such as the radio unit 102, the reference oscillator 108, and the demodulation clock unit 125.

Next, in step S11, data reception is started, and the clock recovery section 124 of the demodulation section 103 adjusts the timing of the symbol clock signal 136 so as to match the symbol timing of the received signal.

Next, at step S12, the control unit 109
Are the comparators 152 and 154 in the timer unit 126.
Is calculated, and each value is calculated by the comparator 15.
2 and the comparator 154. Each value of these comparators is used as a stopper for the count of the clock signal 134 with respect to the comparator 152 as described above.
With respect to, it functions as a stopper for counting the demodulation clock signal 133, and functions as a timer for notifying that a certain time has elapsed as a whole. The clock signal 134 has a very low frequency as compared with the demodulation clock signal 133.
Most of the predetermined time is counted, and the remaining short time that is equal to or less than one cycle of the clock signal 134 is accurately counted by the demodulation clock signal 133.

This is effective in reducing current consumption because a clock signal with low current consumption and a low frequency operates for a long time and a clock signal with high current consumption and a high frequency operate only slightly. How to determine each value will be described later in detail.

Next, at step S13, the control unit 109
However, the switch 145 is turned off by the control signal 132 by controlling the comparator 154. Next, the time until the operation of the clock reproducing unit 124 is restarted is set to 710 m, for example.
s. This period is set by subtracting a margin time from a period (713.3 ms) in which one communication device does not need to receive data in a three-slot TDMA of a digital cellular phone system (PDC) described later with reference to FIG. Period.

Since the demodulation clock signal 133 is not input to the counter 143, the value of the counter at this time is held as it is. The value of the counter 143 is a positive integer and usually changes periodically from 1 to 128. 1
To 128 correspond to one cycle of the symbol clock signal. By holding the value at the time when the switch 145 is turned off, the symbol clock signal can be restarted at the same phase.

Next, at step S14, the control unit 109
Stops the power supply of the radio unit 102, the reference oscillator 108, and the demodulation clock unit 125. Here, in order to simplify the flow, the stopping of the power supply to each device is performed in step S
14, the wireless unit 102 and other devices are
Strictly different processing is performed. Radio unit 102
Is unnecessary at the same time as the switch 145 is turned off, that is, at the same time when the data reception is completed. Therefore, the power supply is stopped at this timing. On the other hand, the power supplies of the reference oscillator 108 and the demodulation clock unit 125 are stopped later than the wireless unit 102 (there is a possibility after step S15 described below). This is because the reference frequency signal from the reference oscillator 108 is used for rearranging and decrypting the data after receiving the data. This is because it is used for timing control of another device after receiving data.

Thereafter, in step S15, control section 109 starts counting clock signal 134 by counter 151. Although steps S13 to S15 are shown to be performed sequentially for convenience of description, it should be noted that these processes can be performed almost simultaneously.

In step S16, it is determined whether the value of the counter 151 is equal to the value -α set in the comparator 152. α is used to activate the reference oscillator 108 and the demodulation clock unit 125 in advance so that when the counter 151 reaches the value set in the comparator 152, the counter 153 that operates next can function immediately. It is time to spare. In other words, this time is the time from when the power is turned on to when the reference oscillator 108 and the demodulation clock unit 125 operate stably, and is usually about 3 ms.

In step S16, the counter 151
Is equal to the value −α of the comparator 152,
Proceeding to 22, the power supply of the reference oscillator 108 and the demodulation clock unit 125 is resumed as described above.

If the determination in step S16 is NO,
In step S17, the counter 151 sets the comparator 15
It is determined whether the value is equal to the value −β set to 2.
β is a margin time for activating the radio unit 102 in advance so that the received data can be demodulated immediately when the counter 151 reaches the value set in the comparator 152. The wireless unit 102 actually needs to be activated in advance so that it operates normally when the counter 153 becomes equal to the comparator 154 in step S20 to be described later. This is to be determined in the second loop (a loop consisting of step S19 and step S20). However, as described later, the time counted by the counter 153 is 2.6 μs.
On the other hand, the time from when the power is turned on until the wireless unit 102 operates stably is about 100 μs.
It is. Accordingly, here, the restart of the power supply of the wireless unit 102 is determined in the first loop (the loop including steps S15 to S18) illustrated in FIG.

The point at which such a restart of the power supply is determined may fluctuate in the future depending on the performance of the radio unit 102 and the like, and is strictly limited to the flowchart shown in FIG. is not.

If the value of the counter 151 is equal to the value of the comparator 152 at step S17, the process proceeds to step S23, and the power supply to the radio unit 102 is restarted as described above.

If the determination in step S17 is NO,
In step S18, it is further determined whether the value of the counter 151 is equal to the value of the comparator 152.

If it is determined in step S18 that the values are not equal (NO), the process returns to step S15, and the clock signal 1
The count of 34 is repeated.

If it is determined in step S18 that they are equal (YES), the process proceeds to step S19, in which the counter 153 is activated to count the demodulation clock signal 133.

Then, the process proceeds to a step S20, wherein the counter 1
It is determined whether the value of 53 is equal to the value of comparator 154.

If not equal, the flow returns to step S19.
The count of the demodulation clock signal 133 is repeated. If they are equal, the process proceeds to step S21, and the switch 145 is turned on.
Then, the counter 143 restarts counting the demodulation clock signal 133. The counter 143 is, as described above,
Since the value 710 ms before the switch 145 was turned off is held, counting is performed continuously from that value,
The symbol clock signal 136 can be output with the same phase as before.

Next, with reference to FIG. 7, a description will be given of a time slot used in the communication apparatus according to the embodiment of the present invention. The communication device is intended for use in a digital mobile phone system (PDS) in Japan. This system employs 3-slot TDMA. This has groups 1 to 36 in successive superframes (per mobile number) as shown in FIG. 7, each of which has 3 slots. Here, the length of one slot is 20/3 ms (hereinafter abbreviated as 6.7 ms). Therefore, one group has three slots, ie, 20 /
3 × 3 = 20 ms in length, and one superframe is 36 groups, ie, 20 × 36 = 720 ms in length.

The period of this one slot is allocated to the reception of a call signal of a certain communication device, and therefore, the reception slot of the call signal allocated to the one communication device is repeated at intervals of 720 ms.
Time other than this slot (720−6.7 = 713.3)
In ms), the communication device is not called, so that the power of the device related to reception can be turned off.

In the present specification, the embodiment of the present invention has been described by taking as an example the application to three-slot TDMA. However, as described above, transmission and reception of signals to and from a communication device at fixed or regular intervals are guaranteed. The present invention can be applied to other communication methods as long as the intermittent reception method is used.

Next, the timing of the entire flow described in FIG. 6 will be described with reference to FIG.

FIG. 8 shows the radio section 102 and the reference oscillator 10
8 and the power on / off of the demodulation clock unit 125, the presence / absence of operation of the counters 151 and 153, and the on / off of the switch 145 of the clock recovery unit 124 in a time series. In this example, the data reception timing is shown for the first A and the B immediately after it, and the period is 6.7 ms in each case. The interval at the start of the two data reception timings A and B is 720 m
s.

As described with reference to FIG. 7, the communication apparatus according to the embodiment of the present invention uses the data reception timing A,
B, during a period in which no data is received (71
3.3 ms), the power of unnecessary circuits is stopped as much as possible.

The timing chart of FIG. 8 will be described corresponding to each step of FIG. Step S13 in FIG.
Corresponds to the first fall for switch 145. Steps S10 to S12 in FIG. 6 have been performed before that, and at this time, the first data reception timing A
Also ends.

Step S14 in FIG. 6 is based on
This corresponds to the first fall of each of the radio unit 102, the reference oscillator 108, and the demodulation clock unit 125. FIG.
Shortly after the power of the radio unit 102 is stopped, the reference oscillator 108 and the demodulation clock unit 12
5 is stopped.

In step S15, the counter 151
Is activated, which, with respect to FIG.
51 is the first rising point. From here, the counting of the clock signal 134 is started.

The time at which the counter 153 starts counting in step S19 in FIG.
This is the second rising of No. 3. At this time, it can be seen that the operation of the counter 151 is stopped at the same time. It can also be seen that the power of the reference oscillator 108, the demodulation clock unit 125, and the radio unit 102 has been turned on before this point in steps S22 and S23 in FIG.

At step S21 in FIG. 6, the preparation for demodulation of the received data is performed by the counter 153 in FIG.
At the time of the second fall. At this time, it can be seen that the switch 145 is turned on at the same time.

In this example, the interruption time during which data can be received again from the end of data reception timing A is 710
In this case, there is actually a margin time of 720-710-6.7 = 3.3 ms from the time when reception becomes possible to the start of the data reception timing B in this case. The extra time is based on the fluctuation of the starting operation time of each component, but if these problems are solved, the extra time can be made closer to 0 ms. However, even in this case, the condition is that the interruption time is an integer multiple of the symbol timing frequency (21 kHz).

Next, the processing contents of step S12 in FIG.
That is, a procedure for obtaining values set in the comparators 152 and 154 in the timer unit 126 will be described in detail.

First, the control unit 109 controls the clock unit 10
5 and the correction value 164 is read. If the clock signal 134 has the correct frequency, ie, 32.768 kHz, the number of the correction value 164 is 2,752 × 14,400,000 / 32,768 = 1,209,
It becomes 375. Here, the value of the read correction value 164 is H
And

Next, the deviation of the clock signal 134 is calculated. From the principle of outputting the correction value 164 of the clock unit 105 (the principle of the clock correction circuit), the deviation X (ppm) = − 1
× (H-1,209,375) × (100/120). Therefore,
Frequency F1 (kHz) of clock signal 134 = 32.768 ×
(1 + X / 1,000,000). Usually, a 32.768 kHz clock signal has a relatively large deviation, and taking such a deviation into account is a very important factor.

In order to stop the symbol clock signal 136 at an arbitrary phase θ and restore the same phase after a certain time, the value of the counter at the time of the phase θ (the counter 143 of the clock reproducing unit 124) is held, and Then, at a timing after n cycles, the counter 143 must be operated again. Therefore, the operation holding time of the clock reproducing unit 124 is equal to the frequency (21 kHz) of the symbol clock 136.
Needs to be exactly n times. In this case, the operation holding time is set to 710 ms, which is nd = 710 ms /
(1/21 kHz) = 14,910, divisible, n = 14,9
10, T = 710 ms.

Next, the time T is defined as n1 periods (= T1) of the clock signal 134 of 32.768 kHz, and 2.688.
MHz demodulation clock signal 133 for n2 periods (= T
Consider expressing in 2). That is, T = T1 + T2.

The count value of the clock signal 134 of 32.768 kHz is n1d = 710 ms / (1 / F1).
Here, assuming that H = 1,209,365, X = −1 ×
(1,209,365-1,209,375) x (100/120) = 8.333333p
pm.

F1 = 32.768 × (1 + 8.333333 / 1,000,00
0) = 32.76772693 kHz, n1d = 710 ms /
(1 / F1) = 710ms × F1 = 710 × 32.78772693 = 23,
265.08612.

Truncation of the decimal places of n1d results in n1 =
Assuming 23,265, T1 = n1x (1 / 32.76772693) = 7
09.9973718 ms.

The remaining time is T2 = 710−709.9973718 = 0.
0026282 ms. From this, the count value of the 2.688 MHz demodulation clock signal 133 is n2d = 0.002628.
2 ms / (1/2688 kHz) = 7.06. The fractional part of n2d is rounded down, so that n2 = 7.

From the above calculations, T1 and T2 are obtained. Since T is configured using two types of clock signals, T1 + T2 may not be an accurate value of T. However, 3/128 of one cycle of the symbol clock signal, that is, (1/21 kHz) × (3/12
8) If the design is made so that the symbol point time error is within the allowable range of the symbol point time error for data demodulation up to 1.1 μs, the error does not matter. Because the 2.688 MHz demodulation clock signal 133 is used to represent T, the error is 1 / 2.6888.
This is because MHz = 0.37 μs or less.

Finally, the set value of the comparator 152 is 232,
365, the set value of the comparator 154 is determined to be 7.

[0101]

According to the present invention, the power supply to the radio unit 102, the reference oscillator 108, and the demodulation unit 103 can be stopped at times other than the timing at which necessary data is received, thereby reducing current consumption. it can.

Further, according to the present invention, it is possible to adopt a structure in which only the clock signal having the lowest frequency is operated when the power supply is stopped, so that the current consumption can be further reduced.

Further, according to the present invention, when power is supplied again, a plurality of counters are provided so that the phase of the symbol clock signal does not shift, and an optimum symbol clock signal can be reproduced.

Further, according to the present invention, the time used for intermittent reception of a radio signal can be precisely obtained while reducing current consumption by using a low frequency and a high frequency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital mobile phone according to the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration of a demodulation unit 103 illustrated in FIG.

FIG. 3 is a block diagram illustrating a detailed configuration of a clock recovery unit 124 illustrated in FIG.

FIG. 4 is a block diagram illustrating a detailed configuration of a timer unit 126 illustrated in FIG.

FIG. 5 is a block diagram illustrating a detailed configuration of a clock unit 105 illustrated in FIG.

FIG. 6 is a flowchart showing the overall operation of the digital mobile phone device according to one embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a slot used in the three-slot TDMA.

FIG. 8 is a chart showing an operation timing of a part of the digital mobile phone device according to one embodiment of the present invention.

FIG. 9 is a block diagram illustrating a detailed configuration of a conventional demodulation unit 203.

FIG. 10 is a block diagram illustrating a detailed configuration of a conventional clock recovery unit 224.

[Explanation of symbols]

 Reference Signs List 101 antenna 102 radio unit 103 demodulation unit 104 AFC unit 105 clock unit 106 audio processing unit 108 reference oscillator 109 control unit 110 operation unit 111 display unit 112 microphone 113 receiver 121 phase detection unit 122 data reproduction unit 123 phase correction unit 124 clock reproduction unit 125 Demodulation clock section 126 Timer section

Claims (13)

[Claims] 1. A communication device for receiving digital data wirelessly, comprising: a first oscillator that generates a first oscillation frequency signal having a first frequency; and a first oscillator that generates a first oscillation frequency signal based on the first oscillation frequency signal. A second oscillator that generates a second oscillation frequency signal having a second frequency, a symbol clock circuit that generates a symbol clock signal using the second oscillation frequency signal, and receives the digital data. If not, the supply of the second oscillating frequency signal to the symbol clock circuit is interrupted for a predetermined period to stop the generation of the symbol clock signal, and a shorter predetermined period within the predetermined period is set. Over a period of time, the control unit controls to stop the power supply of the first oscillator and the second oscillator, a third frequency lower than the second frequency A third oscillator that generates a third oscillation frequency signal, and a timer that measures the predetermined period by counting the number of repetitions of the second oscillation frequency signal and the number of repetitions of the third oscillation frequency signal. The symbol clock circuit has a first counter that holds the value of the phase of the symbol clock signal when the supply of the second oscillation frequency signal is interrupted. When the supply of the second oscillation frequency signal is resumed, the symbol clock circuit uses the phase value held in the first counter to generate the symbol clock signal without causing a phase shift. A communication device for restarting occurrence of the communication. 2. The method according to claim 1, wherein the timer unit compares a second counter that counts the number of repetitions of the second oscillation frequency signal with a value of the second counter and a first comparison value. A first comparator, a third counter that counts the number of repetitions of the third oscillation frequency signal, and a second comparator that compares the value of the third counter with a second comparison value. A communication device comprising: 3. The method according to claim 2, wherein the first and second comparison values are obtained by multiplying a time of one cycle of the second oscillation frequency signal by the first comparison value, and The sum of the time of one cycle of the third oscillation frequency signal multiplied by the second comparison value is determined to be equal to the predetermined period or to be approximated within the predetermined period. The first and second comparators are respectively set, and at the start of the predetermined period, the third counter starts counting the number of repetitions of the third oscillation frequency signal. When the value of the second comparison value becomes equal to the second comparison value, the second counter starts counting the number of repetitions of the second oscillation frequency signal, and the value of the second counter becomes the first comparison value. Judge when it is equal to With the end of the period, the communication apparatus characterized by performing the measurement of the predetermined period. 4. The communication device according to claim 3, wherein the communication device further comprises: a fourth counter for counting the number of repetitions of the third oscillation frequency signal by a predetermined number; and a number of repetitions of the first oscillation frequency signal. And a fifth counter that counts until the value of the second counter reaches the predetermined number. The control unit calculates the frequency of the third oscillator from the value of the fifth counter. A communication device for calculating a deviation. 5. The method according to claim 3, wherein a frequency of the third oscillation frequency signal having high accuracy is obtained from a frequency deviation of the third oscillator, and the first and second comparison values are obtained. A communication device using the high-precision frequency for three oscillation frequency signals. 6. The communication device according to claim 3, wherein when calculating the first and second comparison values, the calculation is performed such that the second comparison value increases. 7. The power supply of the first and second oscillators according to claim 6, wherein in the measurement of the predetermined period, before the counting of the number of repetitions of the second oscillation frequency signal is started. Characteristic communication device. 8. The power supply of a circuit according to claim 6, wherein in the measurement of the predetermined period, before counting of the number of repetitions of the second oscillation frequency signal is completed, the circuit is unnecessary unless the digital data is received. A communication device for supplying. 9. The communication device according to claim 1, wherein the first oscillator is under automatic frequency control. 10. The communication device according to claim 1, wherein the communication device is a mobile phone device. 11. A first oscillator that receives digital data wirelessly and generates a first oscillation frequency signal having a first frequency, and a second frequency based on the first oscillation frequency signal. A method for controlling power supply of a circuit in a communication device having a second oscillator for generating a second oscillation frequency signal having: and a symbol clock circuit for generating a symbol clock signal using the second frequency A step of interrupting the generation of the symbol clock signal by interrupting the supply of the second oscillation frequency signal to the symbol clock circuit for a predetermined period; and a shorter predetermined period within the predetermined period. Interrupting the power supply of the first and second oscillators over a period of time, the symbol clock circuit of the second oscillation frequency signal Holding the value of the phase of the symbol clock signal when the supply to the symbol clock circuit is interrupted; and restarting the supply of the second oscillation frequency signal to the symbol clock circuit when the predetermined period has elapsed. Restarting the supply of the symbol clock signal without causing a phase shift by using the held value of the phase of the symbol clock signal when restarting the supply; The combination of the repetition of the third oscillation frequency signal having a frequency lower than the frequency of the second oscillation frequency signal and the combination of the repetition of the second oscillation frequency signal are similar to the predetermined period or approximated within a range not exceeding the predetermined period. A determination step of determining a first number of repetitions for the third oscillation frequency signal and a second number of repetitions for the second oscillation frequency signal, A measuring step of measuring the predetermined period by repeating the third oscillation frequency signal by the first repetition number and further repeating the second oscillation frequency signal by the second repetition number. . 12. A first oscillator that receives digital data wirelessly and generates a first oscillation frequency signal having a first frequency, and a second frequency based on the first oscillation frequency signal. A method for controlling power supply of a circuit in a communication device having a second oscillator for generating a second oscillation frequency signal having: and a symbol clock circuit for generating a symbol clock signal using the second frequency A computer-readable recording medium that records a symbol clock signal by interrupting the supply of the second oscillation frequency signal to the symbol clock circuit for a predetermined period. Interrupting the occurrence of the first and second oscillations over a shorter predetermined period within the predetermined period. Interrupting the power supply of the second clock signal; and, when the supply of the second oscillation frequency signal to the symbol clock circuit is interrupted, holding the value of the phase of the symbol clock signal. Restarting the supply of the second oscillating frequency signal to the symbol clock circuit; and, when restarting the supply, using the held value of the phase of the symbol clock signal, Restarting the generation of the symbol clock signal without causing a shift. 13. A first oscillator for receiving digital data wirelessly to generate a first oscillation frequency signal having a first frequency, and a second oscillator based on the first oscillation frequency signal. A method for controlling power supply of a circuit in a communication device having a second oscillator for generating a second oscillation frequency signal having: and a symbol clock circuit for generating a symbol clock signal using the second frequency A computer-readable recording medium that records a symbol clock signal by interrupting the supply of the second oscillation frequency signal to the symbol clock circuit for a predetermined period. Interrupting the occurrence of the first and second oscillations over a shorter predetermined period within the predetermined period. Interrupting the power supply of the second clock signal; and, when the supply of the second oscillation frequency signal to the symbol clock circuit is interrupted, holding the phase value of the symbol clock signal. Restarting the supply of the second oscillating frequency signal to the symbol clock circuit; and, when restarting the supply, using the held value of the phase of the symbol clock signal, Restarting the generation of the symbol clock signal without causing a shift, a combination of a repetition of a third oscillation frequency signal having a frequency lower than the second frequency, and a combination of the repetition of the second oscillation frequency signal The first repetition of the third oscillation frequency signal so as to be in agreement with the predetermined period or within a range not exceeding the predetermined period. A determining step of determining a number of times and a second number of repetitions for the second oscillation frequency signal; and repeating the third oscillation frequency signal by the first number of iterations. A computer readable recording medium, comprising: a measuring step of measuring the predetermined time period by repeating the second number of times.