JP2001177058A - Circuit board with asic mounted thereon - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board with ASICs mounted thereon which is reutilizable, without remounting the ASICs, if a circuit block in the ASIC fails or a circuit changes. SOLUTION: Circuit boards 10, 10a mounting ASICs 12, 14 have interfaces allowing the input/output operation between connection parts of a plurality of circuit blocks in the ASICs 12, 14 and the externals of the ASICs 12, 14. Through the interface, an FPGA 82 is connected to allow a specified circuit block in the ASICs 12, 14 to be replaced with the FPGA 82.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ASIC-mounted circuit board on which an ASIC is mounted, and more particularly to a configuration for reusing the circuit board.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 21A, there is a case where a circuit board 200 on which ASICs 210 and 220 which are a kind of logic LSI are mounted is reused. In this case, the ASIC 210.220 is used. It is necessary to check for defects.

In this case, as shown in FIG. 21B, for example, the circuit blocks 310, 320,
Even if part 320 of 330 and 340 is defective,
It was necessary to remove the ASIC 300 from the substrate and replace it with a good ASIC. In addition, when a circuit needs to be changed in an installed ASIC at the time of reuse, it is necessary to newly create the entire ASIC even if it is a part of an internal circuit block.
Further, in any case, the circuit board may be discarded after giving up reuse.

[0004]

In the above-mentioned ASIC replacement work, if the surface of the circuit board to be reused is oxidized or the ASIC has a large number of pins, the ASIC replacement is performed. It was difficult and costly. Further, even when a circuit change is required for only one block in the ASIC, the entire ASIC has to be rebuilt, resulting in a cost.

Therefore, a technical problem to be solved by the present invention is that even if there is a defect in a circuit block in an ASIC or a circuit is changed, a circuit board can be mounted without replacing the ASIC. AS that can be reused
An object of the present invention is to provide an IC mounting circuit board.

[0006]

Means for Solving the Problems and Actions / Effects The present invention solves the above technical problem by providing an A
An SIC mounted circuit board is provided.

A circuit board on which an ASIC is mounted is an ASIC.
It has an interface unit that allows input / output between a connection portion of a plurality of circuit blocks inside and the outside of the ASIC. By connecting an FPGA via the interface unit,
A specific circuit block in the ASIC can be replaced with an internal circuit of the FPGA.

In the above configuration, the FPGA is an ASIC.
May be mounted on the same board as the circuit board on which is mounted, or may be mounted on another board. Alternatively, the FPGA may be always connected to the interface section of the circuit board, or may be connected only when the circuit block needs to be replaced.

According to the above configuration, the FPGA is connected to the interface section of the circuit board, and a specific circuit block in the ASIC (for example, a defective circuit block or a circuit block requiring a circuit change) is constituted by the FPGA. By replacing the circuit, the circuit board can be reused without replacing the ASIC.

The present invention further provides an A
Provided is a circuit board on which an SIC is mounted.

That is, a circuit board on which an ASIC is mounted is connected to a connection portion between a plurality of circuit blocks in the ASIC and the AS board.
An interface unit capable of inputting and outputting to the outside of the IC;
A self-diagnosis function unit for testing a plurality of circuit blocks in the SIC. When the self-diagnosis function unit determines that a specific circuit block of the ASIC has a defect, the specific circuit block in which the defect has been determined can be replaced with an internal circuit of the FPGA by connecting an FPGA to the interface unit. Configuration.

[0012] In the above configuration, the FPGA also uses the ASI
It may be mounted on the same board as the circuit board on which C is mounted, or may be mounted on another board. Alternatively, the FPGA may be always connected to the interface section of the circuit board, or may be connected only when the circuit block needs to be replaced. Further, the self-diagnosis function unit may be provided directly on the circuit board on which the ASIC is mounted, but preferably, if it is provided in the ASIC mounted on the circuit board, the component configuration is simplified.

According to the above configuration, the self-diagnosis function unit makes it easy to detect a defective circuit block in the ASIC. In addition, when detecting a defective circuit block or when a circuit change is required, the FP is connected to the interface section of the circuit board.
Connect a GA and FP a specific circuit block in the ASIC
By replacing the circuit with GA, ASI
The circuit board can be reused without replacing C.

Preferably, an internal circuit of the FPGA that replaces a specific circuit block in the ASIC is configured by reading circuit data stored in a ROM.

According to the above configuration, by replacing the ROM,
Specific circuit blocks in the ASIC can be easily replaced.

More preferably, the ROM includes an AS
Circuit data corresponding to each of a plurality of circuit blocks in the IC is stored.

According to the above configuration, by selecting data stored in the ROM, a plurality of circuit blocks in the ASIC can be appropriately selected and replaced.
There is no need to replace the ROM for each circuit block in the ASIC, and the replacement of circuit blocks becomes easier.

More preferably, when a defect is detected in a specific circuit block in the ASIC by the self-diagnosis function unit, the circuit data corresponding to the specific circuit block is transmitted to the FP.
The GA further includes circuit block replacement control means for automatically reading from the ROM to form an internal circuit and controlling the internal circuit to replace the specific circuit block.

More specifically, for example, the CPU is configured to control the replacement of the circuit block by the FPGA,
When the self-diagnosis function unit detects a defect in a circuit block in the ASIC, the CPU controls data reading from the ROM to rewrite the internal circuit of the FPGA, and replaces the defective circuit block with the internal circuit.

An ASIC is provided by self-diagnosis and automatic rewriting.
This eliminates the need for inspection and replacement of the FPGA ROM, thereby reducing the cost of reusing the circuit board.

Preferably, a specific circuit block in the ASIC to be replaced with an internal circuit of the FPGA is selected by inputting an input / output select signal from the FPGA to the interface section of the ASIC.

According to the above configuration, the interface unit is separately provided for each circuit block in the ASIC,
Since the number of terminals is reduced as compared with the case where the circuit is replaced with a circuit, the configuration of the interface unit is simplified. In addition, circuit replacement work is also facilitated.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an ASIC-mounted circuit board according to each embodiment of the present invention will be described with reference to the drawings.

First, a first embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 1A, two ASICs 12 and 14 and an FP
GA82 is mounted. ASIC to be mounted
May be one or three or more. Also,
A separate FPGA may be used for each ASIC.

As shown in FIG. 1B, the FPGA 82
It is mounted on an FPGA board 80 different from the main circuit board 10a on which the SICs 12 and 14 are mounted, and if necessary,
A form that can be connected to the main circuit board 10a by a connector or the like may be used.

The FPGA 82 is a device that allows the user to determine the function at hand, so that, for example, when reusing the circuit boards 10, 10a, the ASICs 12, 1
In the case where a specific circuit block in 4 is defective or a circuit change is required, the circuit block is replaced with the FPGA 82 so that the ASICs 12 and 14 do not need to be replaced.

Schematically, as shown in FIG.
14 and connection portions of input / output 14a, 14b of ASIC 14 and AS
The configuration is such that the FPGA 82 outside the ASIC and the ASIC 1
ASIC by appropriately connecting the above-mentioned connection parts in the ASIC.
14 can be replaced by the FPGA 84.

That is, when it is desired to replace the specific circuit block 22 in the ASIC 14 with a circuit in the FPGA 82,
The input / output selector 25 is operated by the input / output selector signal 82a from the FPGA 82, and the signal group to be input to the specific circuit block 22 is indicated by the FPG
A82, and is output from the FPGA 82 instead of the specific circuit block 22 at the output position from the specific circuit block 22, as indicated by the arrow 25b. Thus, the specific circuit block 22 is replaced with the FPGA 82.

Next, the connection configuration between the ASIC 30 and the FPGA 82 will be described in more detail.

As shown in FIG. 3, the ASIC 30 receives an ASIC input group signal as indicated by an arrow 30a.
This is processed by an internal circuit block, and an ASIC output group signal is output as indicated by an arrow 30b. Also, ASI
From the FPGA output unit 32 of C30, an FPGA output signal group is output to the FPGA 82 as indicated by an arrow 32a. An FPGA input signal group is output from the FPGA 82, and as indicated by an arrow 34a, the FPGA
The data is input to the input unit 34. Also, from the FPGA 82,
The input / output select signal 82a is output and input to the ASIC 30.

The FPGA 82 is connected to a ROM 84,
As indicated by arrow 84a, data in ROM 84 is read. The FPGA 82 is a gate array capable of freely creating an internal circuit, and its circuit data is stored in a ROM 84. The circuit of the block to be replaced is stored in the ROM 84
, A specific circuit block in the ASIC 30 can be replaced.

That is, a specific circuit block to be replaced by the FPGA 82 is selected from the circuit blocks in the ASIC 30 by the input / output select signal from the FPGA 82. The ASIC 30 outputs a signal group to be input to the specific circuit block selected by the input / output select signal to the FPG.
A82, the signal group from the FPGA 82 is returned to the output portion of the specific circuit block, and the circuit is bypassed to the FPGA 82 side.

Next, the internal configuration of the ASIC 30 will be described.

As shown in FIG. 4, the ASIC 30 includes circuit blocks 41, 42, 43, 44 and selectors 51, 5
2, 53, 54 are connected alternately. Each selector 5
1, 52, 53, and 54 respectively have output signal groups Aout, Aout,
Bout, Cout, and Dout and an input signal group FPGAin from the FPGA 82 are input, and one of them is output. The output selector 55 receives the signal groups Ain, Aout, Bout, and Cout that should be input to the circuit blocks 41, 42, 43, and 44. It is supposed to be.

The input selector section 50 has three control signals from the FPGA 82, namely, signals input_sel1 and input_s for selecting an input position to the ASIC 30.
el2 and ON / OFF signal of replacement in FPGA82
/ not_sel ("0" when not replacing) is input. The input selector unit 50 includes a decoder 50a.
And an AND gate 50b, and outputs selection signals i_sel1, i_sel2, i_sel3, and i_sel4 for selecting an input position to the ASIC 30 according to the logic table of FIG.

Each of the selectors 51, 52, 53, 54 has a selection signal i_sel1, i_sel2, i_sel3,
i_sel4 is input. Then, according to the logic tables of FIGS. 6 to 9, one of the output signal groups Aout, Bout, Cout, Dout of the circuit blocks 41, 42, 43, 44 or the input signal group FPGAin from the FPGA is output.

The output selector 55 has two of the input / output select signals from the FPGA 82, namely, the ASI
A signal output_se for selecting an output position from C30
Based on l1 and output_sel2, one of the signal groups Ain, Aout, Bout, and Cout that should be originally input to the circuit blocks 41, 42, 43, and 44 is selected according to the logic table of FIG. FPGA
Output as out.

For example, the second-stage circuit block 42 is
To replace with PGA, output_sel1 = 0 output_sel2 = 1 input_sel1 = 0 input_sel2 = 1 / not_sel = 1.

When it is desired to replace the third and fourth circuit blocks 43 and 44 with the FPGA 82, output_sel1 = 1 output_sel2 = 0 input_sel1 = 1 input_sel2 = 1 / not_sel = 1.

Next, a second embodiment of the present invention will be described with reference to FIGS.

As shown in the block diagram of FIG.
The ASIC 130 is configured in the same manner as the first embodiment. The ASIC 130 receives an ASIC input group signal as shown by an arrow 130a, processes it by an internal circuit block, and
The ASIC output group signal is output as shown by. Also,
From the FPGA output unit 132 of the ASIC 130, an arrow 1
As shown by 32a, an FPGA output signal group is output to the FPGA 182. An FPGA input signal group is output from the FPGA 182, and as indicated by an arrow 134a, the ASI
It is input to the FPGA input unit 134 of C130. Also,
An input / output select signal 182a is output from the FPGA 182 and input to the ASIC.

On the other hand, the RAM 1 which is not the first embodiment
60 and the CPU 100.

The RAM 160 is provided in the ASIC 130. The CPU 100 is connected to the ASIC 130,
As shown by the arrow 100a, the ASIC test signal is transmitted and received. Further, the CPU 100 is also connected to the FPGA 182, and as shown by the arrow 100b, the clock signal CLK.
And the data signal data, and receive the status signal status as indicated by the arrow 100c. Furthermore, CPU1
00 is connected to the ROM 184 and can read self-diagnosis data, expected value data, and FPGA circuit data stored in the ROM 184, as indicated by an arrow 184a.

That is, the CPU 100 controls the ASIC 13
The test data for self-diagnosis is written to the area 1 of the RAM 160 in the area “0”. The self-diagnosis is performed when the ASIC 130
The test is performed by inputting the test data from the area 1 of 60 to the head circuit block and writing the output result of the circuit block selected by the CPU 100 to the area 2 of the RAM 160. The CPU 100 reads the data in the area 2 of the RAM 160 and detects a defective circuit block based on whether or not the read data matches the expected value stored in the ROM. If there is a defective circuit block, the circuit data of the circuit block is stored in the ROM 184.
From the FPGA 1 and transferred to the FPGA 182.
The circuit of 82 is changed. In the ROM 184, the FPGA 1
In addition to the circuit data of 82, self-diagnosis data (program), expected value data, and the like are stored.

Further, the internal configuration of the ASIC 130 will be described.

As shown in FIG. 12, the ASIC 130
Generally, the configuration is the same as that of the first embodiment. That is, A
The SIC 130 includes circuit blocks 141, 142, 14
3,144 and selectors 151,152,153,154
Are alternately connected to each other, and have an input selector unit 150 and an output selector unit 155 for performing input / output with the FPGA 182. Input selector section 150, selector 1
51, 152, 153, 154, output selector 155
Selects an output signal according to the logic tables of FIGS.

On the other hand, unlike the first embodiment, the ASIC 1
A test block for performing self-diagnosis is added to 30. The test block includes a RAM 160, a diagnostic data generator 164, a diagnostic data writer 166, a test selector 162, and a test input selector (not shown).

The RAM 160 is a dual port.
The first port is connected to the CPU 100, and inputs and outputs an ASIC test signal. The second port of the RAM is connected to a diagnostic data generator and a diagnostic data writer, and inputs and outputs data.

More specifically, most of the ASIC test signals from the CPU 100 are input to the RAM 160. That is, an address signal address for designating an address when data is read / written to / from the RAM 160,
A data signal data for transmitting / receiving data to be written to or read from the RAM 160, a select signal / cs for enabling the RAM 160, a read / write control signal / RD / WR for instructing writing to the RAM 160 or reading from the RAM 160, and access by the second port A busy signal busy indicating that the test is in progress, and a test instruction signal test for instructing execution of the self-diagnosis are input and output to and from the RAM 160.

RAM 160 includes an area 1 for temporarily storing data from CPU 100 and an area 2 for temporarily storing data to be output to CPU 100.

The diagnostic data generator 164 generates a simulation signal for self-diagnosis. The simulation signal is output from the test selector 16
2 is input. The test selector 162 includes an ASIC
The input group signal IN to 130 is also input. Based on the test instruction signal test, the test selector 162 outputs a simulation signal from the diagnostic data generator 164 during self-diagnosis, and an input group signal IN to the ASIC 130 at other times,
The input signal group Ain is output to the first-stage circuit block 141.

The test input selector not shown is an ASIC
Block select signals test_sel1 and test_s for selecting a circuit block for performing self-diagnosis from test signals
According to el2, a signal group test_in to be input to the diagnostic data writing unit 166 is selected according to the logic table of FIG. The diagnostic data writing unit 166 converts the input data into RA data.
Transfer to area 2 of M160.

Next, the operation at the time of self-diagnosis will be described.

As shown in the flowchart of FIG.
The PU 100 reads the diagnostic data from the ROM 184 and writes the diagnostic data to the area 1 of the dual port RAM 160 (# 10). Next, the diagnostic data generator 164 of the ASIC 130 reads out the diagnostic data from the area 1 of the RAM 160 and generates a simulation signal. The simulation signal is sent to the first-stage circuit block 141 via the test selector 162.
It is input as an input signal group Ain (# 12).

Next, according to the combination of the block selection signals test_1 and test_2 for selecting the circuit block for performing the self-diagnosis (# 20 to # 26), the test selector (not shown) sets each of the circuit blocks 141, 142, 14
One of the 3,144 output signal groups Aout, Bout, Cout, Dout is selected as a test signal group test_in and input to the diagnostic data writing unit 166 (# 30 to # 36).

That is, test_1 = 0 and test_2 = 0
, The output signal group Aout of the circuit block 141 is input to the diagnostic data writing unit 166 (# 20, # 3
0). When test_1 = 0 and test_2 = 1, the output signal group Bout of the circuit block 142 is input to the diagnostic data writing unit 166 (# 22, # 32). test_1 =
When 1 and test_2 = 0, the output signal group Cout of the circuit block 143 is input to the diagnostic data writing unit 166 (# 24, # 34). test_1 = 1 and test_2 =
When it is 1, the output signal group Dout of the circuit block 144
Is input to the diagnostic data writing unit 166 (# 26, #
36).

The diagnostic data writing section 166 writes the diagnostic result data based on the test signal group test_in into the area 2 of the RAM 160 (# 40). The CPU 100 reads the diagnostic result data from the area 2 of the RAM 160,
This is compared with the expected value data stored in the OM 184. If the diagnosis result data and the expected value data match within a predetermined range, the selected circuit block is determined to be good, and if not, it is determined to be defective.

As described above, the circuit block in the ASIC can be replaced with the circuit formed in the FPGA. Therefore, when the circuit block in the ASIC is defective or the circuit is changed. Even ASIC
ASIC mounted circuit board can be reused without replacement

The present invention is not limited to the above embodiment, but can be embodied in various other modes. For example, circuit blocks in the ASIC may be connected in parallel.

[Brief description of the drawings]

FIG. 1 is a plan view of an ASIC-mounted circuit board according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of FIG.

FIG. 3 is a connection configuration diagram between the ASIC and the FPGA in FIG. 1;

FIG. 4 is an internal configuration diagram of the ASIC of FIG. 1;

FIG. 5 is a logic table of the input selector unit of FIG. 4;

FIG. 6 is a logic table of a Bin output unit in FIG. 4;

FIG. 7 is a logic table of a Cin output unit in FIG. 4;

FIG. 8 is a logic table of a Din output unit in FIG. 4;

FIG. 9 is a logic table of an OUT output unit in FIG. 4;

FIG. 10 is a logic table of the output selector unit of FIG. 4;

FIG. 11 is a connection configuration diagram of an ASIC-mounted circuit board according to a second embodiment of the present invention.

FIG. 12 is an internal configuration diagram of the ASIC of FIG. 11;

FIG. 13 is a logic table of data input to the self-diagnosis unit of FIG. 12;

FIG. 14 is a logic table of the input selector unit of FIG. 12;

FIG. 15 is a logic table of a Bin output unit in FIG. 12;

FIG. 16 is a logic table of a Cin output unit in FIG. 12;

17 is a logic table of a Din output unit in FIG.

FIG. 18 is a logic table of an OUT output unit in FIG. 12;

FIG. 19 is a logic table of the output selector unit in FIG. 12;

FIG. 20 is a flowchart of an operation at the time of self-diagnosis.

FIG. 21 is an explanatory view of a conventional ASIC mounting board.

[Explanation of symbols]

10, 10a ASIC mounted circuit 12, 14, 30 ASIC 32 FPGA output section (interface section) 34 FPGA input section (interface section) 41, 42, 43, 44 Circuit block 50 input selector section 51, 52, 53, 54 selector ( 55) Output selector unit 82 FPGA circuit 84 ROM 100 CPU (self-diagnosis function unit) 130 ASIC 132 FPGA output unit (interface unit) 134 FPGA input unit (interface unit) 141, 142, 143, 144 Circuit block 150 Input selector Unit 151, 152, 153, 154 Selector (connection part) 155 Output selector unit 160 RAM (self-diagnosis function unit) 162 Test selector (self-diagnosis function unit) 164 Diagnostic data generation unit (self-diagnosis function unit) 66 diagnostic data writing unit (self-diagnosis function portion) 184 ROM (self-diagnosis function portion)

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hideaki Mizuno 2-3-1-13 Azuchicho, Chuo-ku, Osaka-shi, Osaka F-term in Osaka International Building Minolta Co., Ltd. 5F038 DF01 DT08 DT18 EZ20

Claims (6)

[Claims] 1. A circuit board on which an ASIC is mounted, comprising: an interface section through which a connection between a plurality of circuit blocks in the ASIC and the outside of the ASIC can be input / output; and an FPGA connected via the interface section. By doing so, a specific circuit block in the ASIC is
A circuit board on which an ASIC is mounted, wherein the circuit board can be replaced by an internal circuit of a GA. 2. A circuit board on which an ASIC is mounted, wherein an interface for inputting / outputting a connection portion between a plurality of circuit blocks in the ASIC and the outside of the ASIC; and inspecting a plurality of circuit blocks in the ASIC. A self-diagnosis function unit for performing the operation. When the self-diagnosis function unit determines that the specific circuit block of the ASIC has a defect, an FPGA is connected to the interface unit so that the specific circuit block can be connected to the ASIC. A circuit board on which an ASIC is mounted, wherein the circuit board can be replaced by an internal circuit of the FPGA. 3. The internal circuit of the FPGA is a ROM.
A circuit board mounted with the ASIC according to claim 1 or 2, wherein the circuit board is configured by reading circuit data stored in the ASIC. 4. The ASIC according to claim 3, wherein said ROM stores circuit data corresponding to each of a plurality of circuit blocks in said ASIC.
A circuit board equipped with 5. A specific circuit block in the ASIC which is to be replaced by the internal circuit of the FPGA by inputting an input / output select signal from the FPGA to the interface unit of the ASIC. A circuit board on which the ASIC according to claim 1 is mounted. 6. The ASIC according to the self-diagnosis function unit.
When a failure is detected in a specific circuit block in the FPGA, the FPGA automatically reads out circuit data corresponding to the specific circuit block from the ROM to form the internal circuit, and the internal circuit configures the specific circuit. 5. The circuit board having the ASIC according to claim 4, further comprising a circuit block replacement control unit that controls to replace the block.