JP2017027212A - Data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make possible reconfiguration of fixed-type circuitry for data processing for data in at least stage of processing.SOLUTION: Data processors 10 with which a data processing device 100 is equipped perform data processing of processible data. The data processors 10 include a fixed-type data processor 20 and a reconfigurable data processor 30. The fixed-type circuitry with which the fixed-type data processor 20 is equipped can perform stepwise data processing on object data. The reconfigurable data processor 30 can reconfigure a circuit configuration for auxiliary processing of data in at least stage of processing out of multiple processing stages by the fixed-type data processor 20.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a data processing apparatus.

  Reconfigurable circuits (also called programmable logic circuits) such as PLDs (Programmable Logic Devices) and FPGAs (Field Programmable Gate Arrays) capable of reconfiguring (changing) internal logic circuit configurations have become widespread. PLDs and FPGAs generally set an internal logic circuit configuration at the time of circuit startup, but those capable of changing the logic circuit configuration while the circuit is operating have been developed. In addition, the use of dynamically reconfigurable processors (DRPs) that can dynamically reconfigure internal logic circuit configurations is advancing.

  On the other hand, a non-programmable fixed circuit configuration is also necessary in designing the apparatus, and devices such as an ASIC (Application Specific Integrated Circuit) that realizes the fixed circuit configuration are still used in many apparatuses.

  For example, Patent Document 1 and Patent Document 2 describe a circuit configuration in which an ASIC that is a typical example of a fixed circuit configuration and an FPGA that is a typical example of a reconfigurable circuit configuration are combined.

JP 2001-177058 A Japanese Patent Laid-Open No. 2003-078408

  An object of the present invention is to make it possible to reconfigure a data processing circuit configuration for data in at least one processing stage in a fixed circuit configuration.

  The invention according to claim 1 includes a fixed processing unit having a fixed circuit configuration capable of executing stepwise data processing, and at least one processing step among a plurality of processing steps in the stepwise data processing. A data processing apparatus comprising: a reconfigurable processing unit capable of reconfiguring a circuit configuration of auxiliary data processing for certain data.

  According to a second aspect of the present invention, in the data processing device according to the first aspect, the data subjected to the auxiliary data processing by the reconfigurable processing unit is sent to the fixed-type processing unit, and the plurality of processes The data processing apparatus is characterized in that the stepwise data processing is performed on the data from any of the steps.

  The invention according to claim 3 is the data processing device according to claim 1 or 2, wherein the stepwise data processing includes a plurality of unit processes, and the auxiliary data processing includes the plurality of units. An alternative process that is an alternative to the change target process, which is at least one of the processes, is included, and the change target process is executed when the plurality of unit processes are sequentially executed in the stepwise data processing by the fixed processing unit. In this processing order, the reconfigurable processing unit is caused to execute the substitution process instead of the change target process.

  The invention according to claim 4 is the data processing device according to any one of claims 1 to 3, wherein the auxiliary data processing includes an additional process added to the stepwise data processing, The data processing apparatus is characterized in that the fixed type processing unit executes the stepwise data processing and the reconfigurable processing unit executes the additional processing.

  According to the first aspect of the present invention, it is possible to reconfigure a data processing circuit configuration for data in at least one processing stage in a fixed circuit configuration.

  According to the second aspect of the present invention, data processing is executed from an arbitrary processing stage in a fixed circuit configuration.

  According to the third aspect of the invention, an alternative process is realized in place of the process to be changed in the fixed circuit configuration.

  According to the fourth aspect of the present invention, the additional processing added to the data processing in the fixed circuit configuration is realized.

It is a figure which shows the specific example of a data processing apparatus suitable as embodiment of this invention. It is a figure which shows the suitable specific example 1 of a data processing part. It is a figure which shows the suitable specific example 2 of a data processing part. It is a figure which shows the circuit configuration example 1 and the timing chart of a data processing. It is a figure which shows the circuit configuration example 2 and the timing chart of a data processing. It is a figure which shows the circuit configuration example 3 and the timing chart of a data processing.

  FIG. 1 is a diagram showing a specific example of a data processing apparatus 100 suitable as a mode for carrying out the present invention. The data processing apparatus 100 in FIG. 1 includes a data processing unit 10 that performs data processing on target data (data to be processed). A suitable specific example of the target data is image data (including data of only characters, numbers, and symbols), and the like. For example, image data is sent to the data processing apparatus 100 from an external device such as a computer.

  1 is incorporated in an image processing apparatus having an image reading function (scanning function) or the like, and image data obtained from a medium such as paper via the image reading function is the target data. May be. Furthermore, an image corresponding to the image data processed by the data processing apparatus 100 may be printed on paper or the like, or the processed image data may be provided to an external apparatus. Note that suitable specific examples of the image processing apparatus include a copying machine, a printing machine, and a facsimile (FAX). Further, a multifunction machine having a plurality of functions among a copying machine, a printing machine, and a facsimile is also a preferable specific example of the image processing apparatus.

  The data processing unit 10 includes a fixed data processing unit 20 and a reconfigurable data processing unit 30. The fixed data processing unit 20 performs data processing on target data with a fixed (for example, not programmable) circuit configuration. Non-programmable circuit configurations include, for example, hard wired logic. The hard wired logic is, for example, a circuit in which the arrangement and wiring of arithmetic elements are fixed.

  On the other hand, the reconfigurable data processing unit 30 performs data processing on target data with a reconfigurable (programmable) circuit configuration. The reconfigurable circuit configuration can be realized by, for example, a dynamic reconfigurable processor (DRP). Of course, a reconfigurable circuit configuration may be realized by a programmable logic circuit such as PLD (Programmable Logic Device) or FPGA (Field Programmable Gate Array).

  The fixed type circuit configuration provided in the fixed type data processing unit 20 can execute stepwise data processing on target data. The reconfigurable data processing unit 30 is a circuit configuration of auxiliary data processing for processing data in at least one processing stage among a plurality of processing stages in the staged data processing by the fixed data processing unit 20 Can be reconfigured.

  The plurality of processing stages in the fixed data processing unit 20 include a stage before staged data processing (stage before data processing), a stage during staged data processing (stage during data processing), and staged data. A post-processing stage (post-data processing stage) is included. Further, the auxiliary data processing by the reconfigurable data processing unit 30 includes an alternative process that replaces at least a part of the stepwise data processing by the fixed data processing unit 20, and a fixed data processing unit 20. This includes additional processing that is added to the step-by-step data processing.

  FIG. 2 is a diagram illustrating a preferred specific example 1 of the data processing unit 10. The hard wired logic 22 is a preferable specific example of the fixed data processing unit 20 (FIG. 1), and the reconfigurable circuit 32 is a preferable specific example of the reconfigurable data processing unit 30 (FIG. 1).

  The hard wired logic 22 has a fixed circuit configuration capable of executing stepwise data processing. That is, a circuit configuration corresponding to N (N is a natural number) unit processing of data processing (1), data processing (2), data processing (3),..., Data processing (N) is provided. As specific examples of each unit process (each stage or each function of stepwise data processing), image processing such as shading correction, color space conversion, and resolution conversion is suitable. However, each unit process is limited to these specific examples. Not.

  The reconfigurable circuit 32 includes a programmable circuit configuration unit that can reconfigure the circuit configuration, and a circuit for executing data processing is configured in the circuit configuration unit. A specific example of data processing in the reconfigurable circuit 32 is data compression processing or the like. For example, by making it possible to reconfigure the data compression processing circuit, it is possible to flexibly cope with a change in a desired compression ratio or the like as compared with the case of a fixed circuit configuration. Further, as the data processing in the reconfigurable circuit 32, an alternative processing that replaces at least a part of the data processing in the hard wired logic 22 may be realized. Thereby, for example, it is possible to flexibly cope with an upgrade of data processing in the hard wired logic 22.

  The hard wired logic 22 includes a plurality of multiplexers (in addition to a circuit configuration corresponding to each unit process of data processing (1), data processing (2), data processing (3),..., Data processing (N)). MUX) and a plurality of demultiplexers (DEM).

  The DEM (1) outputs the target data processed by the data processing (1) to the data processing (2) or the output selection multiplexer (MUX). The DEM (2) outputs the target data processed by the data processing (2) to the data processing (3) or the output selection MUX, and the DEM (3) is the target data processed by the data processing (3). Is output to the subsequent data processing or output selection MUX.

  The output selection multiplexer (MUX) selects target data obtained from any of the plurality of demultiplexers (DEM) included in the hard wired logic 22 and outputs the target data to the reconfigurable circuit 32. When the input buffer of the reconfigurable circuit 32 includes a plurality of buffer areas, the target data is input from the output selection MUX to any buffer area. The target data output from the output selection MUX is subjected to data processing in the reconfigurable circuit 32.

  The target data processed in the reconfigurable circuit 32 is output to an input selection demultiplexer (DEM). When the output buffer of the reconfigurable circuit 32 includes a plurality of buffer areas, the input selection DEM acquires target data from any of the buffer areas. For example, the target data is acquired from the buffer area (number) of the output buffer corresponding to the buffer area (number) of the input buffer selected by the output selection MUX.

  Then, the input selection DEM outputs the target data to any one of a plurality of multiplexers (MUX) included in the hard wired logic 22.

  The MUX (1) selects either target data obtained from the input selection DEM or target data processed by the data processing (1) and outputs the selected data to the data processing (2). The MUX (2) selects either the target data obtained from the input selection DEM or the target data processed by the data processing (2) and outputs the selected data to the data processing (3). The MUX (3) Either target data obtained from the input selection DEM or target data processed by the data processing (3) is selected and output to the subsequent data processing.

  The plurality of multiplexers (MUX), the plurality of demultiplexers (DEM), the output selection multiplexer (MUX), and the input selection demultiplexer (DEM) select the target data or output the target data according to the control by the data control unit 40. Select. For example, the data control unit 40 can set target data in a desired order by register settings for a plurality of multiplexers (MUX), a plurality of demultiplexers (DEM), an output selection multiplexer (MUX), and an input selection demultiplexer (DEM). The control to perform the data processing is realized.

  Note that at least some of the plurality of multiplexers (MUX), the plurality of demultiplexers (DEM), the output selection multiplexer (MUX), and the input selection demultiplexer (DEM) may be omitted, or at least some functions. May be realized by other alternative configurations.

  In addition, a multiplexer (MUX) and a demultiplexer (DEM) are provided before the data processing (1) of the hard-wired logic 22, and the target data before being subjected to the data processing (1) is processed by the reconfigurable circuit 32. Alternatively, the target data processed by the reconfigurable circuit 32 may be processed by the data processing (1).

  FIG. 3 is a diagram illustrating a preferred specific example 2 of the data processing unit 10. The hard wired logic 22 is a preferable specific example of the fixed data processing unit 20 (FIG. 1), and the reconfigurable circuit 32 is a preferable specific example of the reconfigurable data processing unit 30 (FIG. 1).

  The hard wired logic 22 has a fixed circuit configuration capable of executing stepwise data processing. That is, a circuit configuration corresponding to N (N is a natural number) unit processing of data processing (1), data processing (2), data processing (3),..., Data processing (N) is provided. Each unit process is the same as, for example, the specific example 1 in FIG. Also, the reconfigurable circuit 32 of FIG. 3 is the same as the specific example 1 of FIG. 2 and includes a programmable circuit configuration unit that can reconfigure the circuit configuration, and a data processing circuit is included in the circuit configuration unit. Is configured.

  In specific example 2 of FIG. 3, target data is transferred via a data bus by a plurality of bus interfaces (bus IFs). Transfer of the target data using the data bus is controlled by the arbitrator.

  The hard wired logic 22 includes a plurality of multiplexers (in addition to a circuit configuration corresponding to each unit process of data processing (1), data processing (2), data processing (3),..., Data processing (N)). MUX) and a plurality of demultiplexers (DEM).

  The DEM (1) outputs the target data processed by the data processing (1) to the data processing (2) or the bus IF (1). The DEM (2) outputs the target data processed by the data processing (2) to the data processing (3) or the bus IF (2), and the DEM (3) is processed by the data processing (3). The target data is output to the subsequent data processing or bus IF (3).

  The target data obtained from any of a plurality of demultiplexers (DEM) included in the hard wired logic 22 is transferred to the bus IF (P) via the data bus, and is sent from the bus IF (P) to the reconfigurable circuit 32. It is done. When the input buffer of the reconfigurable circuit 32 includes a plurality of buffer areas, the target data is input from the bus IF (P) to any buffer area. The target data output from the bus IF (P) is processed in the reconfigurable circuit 32.

  The target data processed in the reconfigurable circuit 32 is sent from the bus IF (P) to the data bus. If the output buffer of the reconfigurable circuit 32 includes a plurality of buffer areas, the bus IF (P) acquires target data from any of the buffer areas. For example, the target data is acquired from the buffer area (number) of the output buffer corresponding to the buffer area (number) of the input buffer to which the target data is input.

  The target data sent from the bus IF (P) to the data bus is output to one of a plurality of multiplexers (MUX) included in the hard wired logic 22 via the bus IFs (1) to (3).

  The MUX (1) selects either the target data obtained from the bus IF (1) or the target data processed by the data processing (1) and outputs it to the data processing (2). The MUX (2) selects either the target data obtained from the bus IF (2) or the target data processed by the data processing (2) and outputs the selected data to the data processing (3). ) Selects either the target data obtained from the bus IF (3) or the target data processed by the data processing (3) and outputs it to the subsequent data processing.

  The plurality of multiplexers (MUX), the plurality of demultiplexers (DEM), and the plurality of bus interfaces (bus IF) select the target data or select the output destination of the target data according to the control by the data control unit 40. The data control unit 40 realizes control such that the target data is subjected to desired data processing in a desired order by, for example, register setting for each multiplexer (MUX) and each demultiplexer (DEM).

  Note that at least some of the plurality of multiplexers (MUX), the plurality of demultiplexers (DEM), and the plurality of bus interfaces (bus IFs) may be omitted, or at least some of the functions may be based on other alternative configurations. It may be realized.

  Also, a multiplexer (MUX) and a demultiplexer (DEM) are provided in the previous stage of the data processing (1) of the hard wired logic 22, and a bus interface (bus IF) is provided to these multiplexers (MUX) and demultiplexer (DEM). By connecting, the target data before being subjected to data processing (1) may be processed by the reconfigurable circuit 32, or the target data processed by the reconfigurable circuit 32 is processed by data processing (1 ) May be processed.

  2 and 3, the target data after processing in the hard-wired logic 22 is temporarily stored (buffered) in a memory or the like, sent to the reconfigurable circuit 32 after time adjustment. Alternatively, the target data after processing in the reconfigurable circuit 32 may be temporarily stored (buffered) in a memory or the like and sent to the hardwired logic 22 after time adjustment.

  2 and 3 may be realized as package parts, for example. For example, the data processing unit 10 of FIG. 2 or FIG. 3 may be embodied by one package (one chip) ASIC (Application Specific Integrated Circuit) in which the hard wired logic 22 and the reconfigurable circuit 32 are mounted together. Of course, the data processing unit 10 may be realized by combining a plurality of package parts (a plurality of chips), for example, an ASIC, FPGA, DRP, or the like.

  4 to 6 show a circuit configuration example of the reconfigurable circuit 32 and a timing chart of data processing. 4 to 6, a specific example of data processing (P) is data compression processing and the like. Specific examples of unit processing of data processing (1), data processing (2), and data processing (3) are shading correction. Color space conversion, resolution conversion, and the like. Further, the data processing is executed for each structural unit constituting the target data, for example. 4 to 6, the target data is composed of a plurality of lines, and data processing is executed for each line in order from the first line 1.

  FIG. 4 is a diagram illustrating a circuit configuration example 1 of the reconfigurable circuit 32 and a timing chart of data processing. In the circuit configuration example 1 in FIG. 4, the data processing (P) circuit is reconfigured in the reconfigurable circuit 32 (FIGS. 2 and 3). Further, the hard wired logic 22 (FIGS. 2 and 3) has a circuit configuration corresponding to each unit process of data processing (1), data processing (2), and data processing (3).

  In the specific example of FIG. 4, first, the line 1 of the target data is pipeline processed by the hardwired logic 22 in the order of data processing (1), data processing (2), and data processing (3). For example, the line 1 is composed of a plurality of data, and each data is subjected to the data processing (2) immediately after the data processing (1) is performed, without waiting for the processing of other data thereafter. Δt shown in FIG. 4 is a pipeline delay and corresponds to the processing time from the input of each data to the output of the data processing (1), data processing (2), and data processing (3). doing.

  When the data processing (3) is executed by the hardwired logic 22, the target data line 1 is sent from the hardwired logic 22 to the reconfigurable circuit 32, and the data processing (P) is executed by the reconfigurable circuit 32. Is done. Thus, the target data line 1 is pipeline processed in the order of data processing (1), data processing (2), data processing (3), and data processing (P).

  Each line following the target data line 1 is also pipelined in the same manner as the line 1. For example, the first data of the line 2 of the target data is input to the data processing (1) following the final data of the line 1 of the target data, and the pipeline processing for the line 2 is started. Similarly, pipeline processing is sequentially performed on the lines 3 and 4 after the line 2.

  According to the specific example shown in FIG. 4, the data processing by the reconfigurable circuit 32 as an additional processing added to the data processing (1), the data processing (2) and the data processing (3) executed by the hard wired logic 22. (P) is executed.

  FIG. 5 is a diagram illustrating a circuit configuration example 2 of the reconfigurable circuit 32 and a timing chart of data processing. In the circuit configuration example 2 in FIG. 5, the data processing (P) circuit and the data processing (2 ′) circuit are reconfigured in the reconfigurable circuit 32 (FIGS. 2 and 3). The data process (2 ′) is an alternative process executed in place of the data process (2). Further, the hard wired logic 22 (FIGS. 2 and 3) has a circuit configuration corresponding to each unit process of data processing (1), data processing (2), and data processing (3). However, in the specific example of FIG. 5, the data processing (2) is not executed in the hard wired logic 22.

  In the specific example of FIG. 5, first, when the data processing (1) is executed by the hardwired logic 22, the line 1 of the target data is sent from the hardwired logic 22 to the reconfigurable circuit 32, and the reconfigurable circuit The data processing (2 ') is executed by 32. When the data processing (2 ′) is executed, the line 1 of the target data is returned from the reconfigurable circuit 32 to the hard wired logic 22, and the data processing (3) is executed by the hard wired logic 22. Further, when the data processing (3) is executed, the target data line 1 is sent from the hardwired logic 22 to the reconfigurable circuit 32, and the reconfigurable circuit 32 executes the data processing (P). Thus, the target data line 1 is pipeline processed in the order of data processing (1), data processing (2 '), data processing (3), and data processing (P).

  Note that Δt in FIG. 5 is also a pipeline delay, and corresponds to the processing time from the input of each data to the output of each data processing.

  Each line following the target data line 1 is also pipelined in the same manner as the line 1. For example, the first data of the line 2 of the target data is input to the data processing (1) following the final data of the line 1 of the target data, and the pipeline processing for the line 2 is started. Similarly, pipeline processing is sequentially performed on the lines 3 and 4 after the line 2.

  According to the specific example shown in FIG. 5, the data processing by the reconfigurable circuit 32 as an additional processing added to the data processing (1), the data processing (2), and the data processing (3) executed by the hard wired logic 22. (P) is executed, and the data processing (1), the data processing (2), and the data processing (3), which is a part of the data processing (3), are executed by the hard-wired logic 22. As a result, the data processing (2 ′) is executed by the reconfigurable circuit 32.

  The specific example shown in FIG. 5 is suitable, for example, when the data processing (2) is upgraded to the data processing (2 ′). For example, according to the specific example shown in FIG. 5, the data processing (2) is preferably performed without changing the hardware resources while maintaining the hardware resources of the hard-wired logic 22 and the reconfigurable circuit 32 as much as possible. The version is upgraded to (2 ′).

  FIG. 6 is a diagram illustrating a circuit configuration example 3 of the reconfigurable circuit 32 and a timing chart of data processing.

  In the circuit configuration example 3 in FIG. 6, the data processing (P) circuit, the data processing (2 ′) circuit, and the data processing (3 ′) circuit are reconfigured in the reconfigurable circuit 32 (FIGS. 2 and 3). Composed. The data process (2 ′) is an alternative process executed instead of the data process (2), and the data process (3 ′) is an alternative process executed instead of the data process (3).

  Further, the hard wired logic 22 (FIGS. 2 and 3) has a circuit configuration corresponding to each unit process of data processing (1), data processing (2), and data processing (3). However, in the specific example of FIG. 6, the data processing (2) and the data processing (3) are not executed in the hard wired logic 22.

  In the specific example of FIG. 6, first, when data processing (1) is executed by the hardwired logic 22, the line 1 of the target data is sent from the hardwired logic 22 to the reconfigurable circuit 32, and the reconfigurable circuit The data processing (2 ') is executed by 32.

  In the specific example of FIG. 6, the processing speed of each data processing in the reconfigurable circuit 32 is twice the processing speed of each data processing in the hard wired logic 22. Therefore, the data processing (2 ′) for each line by the reconfigurable circuit 32 is started after waiting for a delay time T / 2 that is half the processing time T of each data processing for each line in the hardwired logic 22. . For example, it is desirable that the target data after processing in the hard-wired logic 22 is temporarily stored (buffered) in a memory or the like and time-adjusted before being sent to the reconfigurable circuit 32.

  When the data processing (2 ′) is executed, the target data line 1 continues to reconfigure the reconfigurable circuit 32 and is pipelined in the order of data processing (3 ′) and data processing (P). .

  Each line following the target data line 1 is also pipelined in the same manner as the line 1. For example, the first data of the line 2 of the target data is input to the data processing (1) following the final data of the line 1 of the target data, and the pipeline processing for the line 2 is started. Similarly, pipeline processing is sequentially performed on the lines 3 and 4 after the line 2.

  In the specific example of FIG. 6, as shown in the timing chart, in the period A1, the data process (2 ′) for the line 2 is executed in parallel with the data process (P) for the line 1, and in the period A2, the data process for the line 2 is performed. In parallel with the data processing (P), the data processing (2 ′) for the line 3 is executed. That is, in the period A (A0, A1, A2,...), The data processing (P) circuit and the data processing (2 ′) circuit are required in the reconfigurable circuit 32.

  In the period B1, the data process (3 ′) for the line 1 is executed, and in the period B2, the data process (3 ′) for the line 2 is executed. That is, a data processing (3 ′) circuit is required in the reconfigurable circuit 32 in the period B (B1, B2, B3,...).

  Therefore, in the specific example of FIG. 6, a circuit configuration corresponding to two processes (two functions) of data processing (P) and data processing (2 ′) in the period A in the reconfigurable circuit 32 (two functions and one configuration type). ) Is reconfigured, and in the period B, the circuit configuration (1 function 1 configuration type) corresponding to 1 process (1 function) of the data process (3 ′) is reconfigured.

  Since the period A and the period B occur alternately during the data processing for the target data composed of a plurality of lines, the circuit configuration in the reconfigurable circuit 32 is dynamically reconfigured during the data processing. . A specific example suitable for an existing device that realizes dynamic reconfiguration is a dynamic reconfigurable processor (DRP). For example, the reconfigurable circuit 32 can be realized by DRP. Of course, the reconfigurable circuit 32 may be realized by using a dynamically reconfigurable device (such as a processor) other than DRP that will appear in the future.

  According to the specific example shown in FIG. 6, the data processing by the reconfigurable circuit 32 as an additional processing added to the data processing (1), the data processing (2), and the data processing (3) executed by the hard wired logic 22. (P) is executed, and further, data processing (2) and data processing (part of data processing (1), data processing (2), and data processing (3) executed by the hard-wired logic 22) As an alternative process in place of 3), the reconfigurable circuit 32 executes data processing (2 ′) and data processing (3 ′).

  The specific example shown in FIG. 6 is suitable, for example, when data processing (2) and data processing (3) are upgraded to data processing (2 ′) and data processing (3 ′), respectively. For example, according to the specific example shown in FIG. 6, the data processing (2) is preferably performed without changing the hardware resources while maintaining the hardware resources of the hard-wired logic 22 and the reconfigurable circuit 32 as much as possible. 2 ′), and data processing (3) is upgraded to data processing (3 ′).

  In the specific example shown in FIG. 6, the circuit configuration of the data processing (2 ′), the data processing (3 ′), and the data processing (P) is reconfigured at once in the reconfigurable circuit 32 (three functions and one configuration). If it is not possible, it will be one of the most effective solutions.

  As mentioned above, although preferred embodiment of this invention was described, embodiment mentioned above is only a mere illustration in all the points, and does not limit the scope of the present invention. The present invention includes various modifications without departing from the essence thereof.

  10 data processing units, 20 fixed data processing units, 22 hard-wired logic, 30 reconfigurable data processing units, 32 reconfigurable circuits, 100 data processing devices.

Claims (4)

A fixed processing unit having a fixed circuit configuration capable of performing stepwise data processing;
A reconfigurable processing unit capable of reconfiguring an auxiliary data processing circuit configuration for data in at least one of the plurality of processing steps in the stepwise data processing;
Having
A data processing apparatus. The data processing apparatus according to claim 1,
The data subjected to the auxiliary data processing by the reconfigurable processing unit is sent to the fixed type processing unit, and the stepwise data processing is performed on the data from any processing step among the plurality of processing steps. Apply,
A data processing apparatus. The data processing device according to claim 1 or 2,
The stepwise data processing is composed of a plurality of unit processes,
The auxiliary data processing includes an alternative process as an alternative to the change target process that is at least one of the plurality of unit processes.
In performing the plurality of unit processes in order in the stepwise data processing by the fixed-type processing unit, the replacement process is performed in the reconfigurable processing unit instead of the change target process in the processing order of the change target process. To execute,
A data processing apparatus. The data processing apparatus according to any one of claims 1 to 3,
The auxiliary data processing includes additional processing added to the stepwise data processing,
Causing the fixed type processing unit to execute the stepwise data processing and causing the reconfigurable processing unit to execute the additional processing;
A data processing apparatus.

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