JP2008181361A - Data processing device, image processing apparatus and data processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To implement speed up of data processing using a reconfigurable arithmetic circuit. <P>SOLUTION: At first, the reconfigurable circuit 22 contains an X processing part 80 for image processing X and an A processing part 82 for image processing A using intermediate data Dx output from the X processing part 80. When a condition of reconfiguration is satisfied, the reconfigurable circuit 22 is completely reconfigured to contain an X processing part 84 and a B processing part 86. The X processing part 84 has the same logic circuit as the X processing part 80 and retains the intermediate data Dx retained in the X processing part 80. The B processing part 86 can thus use the intermediate data Dx to perform immediate image processing B. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data processing device, an image processing device, or a data processing program.

  A technique for performing arithmetic processing using a circuit that can be logically reconfigured is known.

  Patent Document 1 below discloses a technique for switching a plurality of processes at high speed in a reconfiguration circuit that takes a relatively long time for reconfiguration. Specifically, a circuit that is common to all the processes and a circuit that is not common to any of the processes are configured in advance, and the remaining necessary circuits are reconfigured according to the process to be performed.

  Patent Document 2 below discloses a technique for reconfiguring, on a dynamic reconfiguration circuit, image processing in which which is to be performed is clear in advance, such as image compression processing and decompression processing. In this technique, a reconfigurable circuit is completely replaced to form a compression circuit or expansion circuit, and compression processing or expansion processing is performed on image data to be processed.

JP 2001-51826 A JP 2006-50571 A

  By the way, an arithmetic unit is generally used as a basic element constituting a circuit that can be logically reconfigured. When performing a large-scale arithmetic process, the logical reconfiguration of the arithmetic unit is repeated, which increases the processing load.

  The present invention relates to a data processing device that speeds up data processing in a reconfigurable arithmetic circuit by utilizing data held before reconfiguration after reconfiguration to suppress or prevent an increase in data processing amount, image It is an object to provide a processing device or a data processing program.

  In one aspect of the data processing apparatus of the present invention, a logical reconfiguration is possible, and the stored data is arranged in an arithmetic circuit that can maintain the stored data before and after the reconfiguration, and the stored data is referred to. And a data processing unit that performs a plurality of data processing associated with updating, a determination unit that determines whether or not to change a certain data process in the plurality of data processes to another data process, and a determination by the determination unit Relocation means for reconfiguring the arithmetic circuit based on the result and rearranging the data processing unit, wherein the relocation means changes the certain data processing to the other data processing. The data processing unit is rearranged so that at least a part of the data processing that is not changed is performed at a location corresponding to that before the rearrangement, and the data processing unit is After placement, with reference to the data held before relocating the portion corresponding to the previous said arrangement implementing the specific data processing.

  In one aspect of the data processing apparatus of the present invention, the location corresponding to the pre-relocation is the same location as the pre-relocation on the arithmetic circuit.

  In one aspect of the data processing apparatus of the present invention, when the relocation means changes the certain data processing to the other data processing, the different data is processed at the place where the certain data processing is performed. The data processing unit is arranged so that the processing is performed.

  In one aspect of the data processing apparatus of the present invention, when the rearrangement unit changes the certain data processing to the other data processing, the other data processing to be rearranged is the certain data processing. When the data processing unit is rearranged so as not to update the data that has been referenced or updated by the above, and then re-changed to the certain data processing again, the certain data processing is performed at a location corresponding to the previous one. The data processing unit is rearranged as described above.

  In one aspect of the data processing apparatus of the present invention, the part corresponding to the previous part is the same part as before.

  In one aspect of the data processing apparatus of the present invention, the certain data processing is performed in a time-sequential manner by processing a plurality of data in a synchronized manner in a plurality of stages in which processing is sequentially transferred from upstream to downstream. The data processing unit includes an adjustment mechanism that adjusts an arrangement order of data output from the certain data processing and data output from the other data processing.

  In one aspect of the data processing apparatus of the present invention, the different data processing is performed in a synchronized manner in a plurality of stages in which the processing is sequentially transferred from upstream to downstream, thereby adding a time difference to processing of the plurality of data. The plurality of stages in the other data processing is shorter than the plurality of stages in the certain data processing, and the data from the other data processing is earlier than the certain data processing. Is output.

  In one aspect of the data processing apparatus of the present invention, an input unit for sequentially inputting data is provided, and the data processing unit performs the plurality of associated data processing on each input data.

  In one aspect of the data processing apparatus of the present invention, the determination means determines whether to change the certain data processing to the other data processing for each input data.

  In one aspect of the data processing apparatus of the present invention, the plurality of data processing performed by the data processing unit is data processing on image data.

  In one aspect of the data processing apparatus of the present invention, the certain data processing and the different data processing are different in the width of the pixel range of the data to be referred to, and the location corresponding to before the rearrangement depends on the arrangement of the rearrangement unit. The at least part of the data processing set to be executed includes an array holding process in which the data is arranged and held in an arrangement order in which both the one data processing and the other data processing can be referred to in common. Is included.

  One aspect of the image processing apparatus of the present invention includes a generating unit that generates the image data or a printing unit that performs printing based on the image data.

  In one aspect of the data processing program of the present invention, an arithmetic circuit that can be logically reconstructed and that can maintain the retained data before and after the reconfiguration, and the arithmetic circuit that is arranged and retained A data processing unit that performs a plurality of data processing associated with the data being referred to and updated, and a determination unit that determines whether to change one data processing in the plurality of data processing to another data processing, Relocation means for reconfiguring the arithmetic circuit based on a determination result of the determination means and relocating the data processing unit, wherein the data processing is performed on the relocation means with respect to the different data processing. The data processing unit is reconfigured so that at least a part of the data processing that is not changed is performed at a location corresponding to that before the rearrangement. Is location, to said data processing unit, wherein after rearrangement by rearrangement means, with reference to the data held before relocating the portion corresponding to the previous the arrangement, thereby carrying out said further data processing.

  According to the first aspect of the present invention, since it is possible to utilize the data held before the reconfiguration as compared with the case where the present configuration is not provided, an increase in the amount of data processing due to re-operation Can be suppressed or prevented, and the data processing speed can be increased.

  According to the present invention of claim 2, even an arithmetic circuit that cannot be partially reconfigured can be substantially partially reconfigured.

  According to the present invention of claim 3, it is possible to save the space of the arithmetic circuit as compared with the case where the present configuration is not provided.

  According to the present invention of claim 4, when the certain data processing is performed again, it is possible to utilize the data retained from the previous execution, so when this configuration is not provided Compared to the above, it is possible to reduce or prevent the waste of redoing the calculation.

  According to the present invention of claim 5, since the change due to the reconfiguration is reduced, the design of the reconfiguration is facilitated as compared with the case where the present configuration is not provided.

  According to the present invention of claim 6, the arrangement order of data can be adjusted.

  According to the present invention of claim 7, when data processing having a short processing stage is performed, data is output earlier than data processing having a long processing stage. The data processing can be speeded up as compared with the configuration synchronized with the data processing having.

  According to the eighth aspect of the present invention, it is possible to speed up the execution of different types of data processing on sequentially input data as compared with the case where the present configuration is not provided.

  According to the present invention of claim 9, different types of data processing can be performed on each input data.

  According to the tenth aspect of the present invention, it is possible to increase the speed of image processing as compared with the case where the present configuration is not provided.

  According to the eleventh aspect of the present invention, since a circuit for providing data to be referred to is shared, a space for the arithmetic circuit can be saved as compared with the case where the present configuration is not provided.

  According to the present invention of claim 12, there is provided an image processing apparatus capable of speeding up image processing as compared with a case where the present configuration is not provided.

  According to the thirteenth aspect of the present invention, there is provided a program for utilizing the data held before the reconfiguration and increasing the data processing speed as compared with the case where the present configuration is not provided.

  Embodiments of the present invention are illustrated below.

  FIG. 1 is a block diagram illustrating an outline of a hardware configuration of an image processing apparatus 10 according to the present embodiment. The image processing apparatus 10 is a data processing apparatus that processes image data such as still images and moving images. For example, the image processing apparatus 10 is constructed using a general-purpose computer such as a PC (personal computer), or has a built-in printer or scanner. It can be constructed using a computer that mainly performs image processing.

  The image processing apparatus 10 includes a reconstruction device 20. The reconfigurable device 20 is an apparatus that may be called a programmable device or a reconfigurable device. The reconstruction device 20 includes a reconstruction circuit 22, a control circuit 32, a memory 34, and the like, which are typically installed on a substrate. The reconfiguration circuit 22 is an arithmetic circuit capable of logical reconfiguration, and includes a plurality of PEs (processor elements) 23, 24,. . . Is included. PE (processor elements) 23, 24,. . . Is a basic unit for logical reconfiguration. The illustrated PE 30 is provided for instructing the control circuit 32 to perform reconfiguration.

  Here, PE will be described with reference to FIG. FIG. 2 is a diagram conceptually illustrating the hardware configuration of the PE. The PE includes a register 70 that holds (stores) input data in1 and a register 72 that holds input data in2. The register 70 and the register 72 are connected to an ALU (arithmetic logic unit) 74. The ALU (arithmetic logic operation unit) 74 refers to (reads) the input data in1 and in2, performs various operations such as addition, subtraction, multiplication, and passage, and outputs the operation result to the register 76 as output data out. (The data in the register 76 is updated). What calculation the ALU 74 performs is controlled by a control signal 78. Then, by operating the control signal 78, the logical operation function of the ALU 74 is reconfigured. In this reconfiguration, the data held in the registers 70, 72, 76 is preserved unless the data is explicitly erased or updated. That is, after the reconfiguration, the ALU 74 and the PE can continue using the data held before the reconfiguration.

  The PE can be configured in various ways other than those described here. Specifically, a mode in which the reconfiguration is realized by switching the flow of the data signal flowing between the PEs, and a mode in which a plurality of ALUs are built in the PE to perform complex arithmetic control can be exemplified.

  Returning to FIG. 1 again, the description of the image processing apparatus 10 will be continued. The control circuit 32 in the reconfiguration device 20 is a circuit that reconfigures the reconfiguration circuit 22 based on a command from the PE 30. The control circuit 32 performs reconfiguration according to a program stored in the memory 34. The storage of the program in the memory 34 may be performed when the reconfigurable device 20 is manufactured, or may be performed after manufacturing. In the image processing apparatus 10, a data processing program for image data is typically stored in the memory 34, and the reconstruction device 20 is used as a high-speed image processing apparatus that conforms to dedicated image processing hardware.

  In addition to the above hardware, the reconfigurable device 20 can be provided with, for example, an arithmetic circuit that cannot be logically reconfigured, an SRAM (memory), an input / output switch, and the like. In addition, arithmetic circuits, SRAM, input / output switches, and the like that cannot be reconfigured can be mixed in the reconfiguration circuit 22.

  The reconfiguration device 20 is connected to the internal bus 40. The internal bus 40 is a communication path in the image processing apparatus 10, and various data, control signals, and the like are flown through it. Connected to the internal bus 40 are a CPU (central control unit) 42, a memory 44, a printer 46, a scanner 48, a UI (user interface) 50, a CDD (compact disk drive) 52, a network IF (interface) 54, and the like. .

  The CPU 42 is a device that performs various controls and image processing in the image processing apparatus 10. The CPU 42 operates based on a program stored in the memory 44. The CPU 42 can also control to separate the image processing to be performed by the reconstruction device 20 and the image processing to be performed by itself. The memory 44 is a storage device configured using a semiconductor memory or a magnetic disk.

  The printer 46 is a device that performs printing on paper based on image data. The scanner 48 is a device that reads paper and generates image data. The UI 50 is a device for the user to operate the image processing apparatus 10. The UI 50 includes an input device such as a keyboard and a touch panel for a user to input instructions, and a display device such as a liquid crystal display for visually presenting images and other data to the user.

  The CDD 52 is a device for inputting / outputting data to / from a CD (compact disc) as a storage medium. It is also possible to store a program for controlling the control circuit 32 or the CPU 42 in a CD and perform installation through the CDD 52. The network IF 54 is an interface for performing communication through an external network 60 such as the Internet. Thereby, the image processing apparatus 10 can transmit / receive image data to / from an external apparatus connected to the network 60, or can receive a data signal of a program for controlling the control circuit 32 or the CPU. It becomes like this.

  The hardware in the image processing apparatus 10 is controlled by a program for controlling the control circuit 32 or the CPU 42, and functions organically as an apparatus for performing image processing. Based on user instructions input from the UI 50, various image processing such as printing using the printer 46, image data generation using the scanner 48, and image data processing using the CPU 42 and the reconstruction device 20 are performed. To do. In particular, in the reconstruction device 20, image processing functions such as image data expansion / compression, filtering, and rotation are constructed by reconstruction, and high-speed hardware processing is performed.

  Next, the reconstruction device 20 will be described in detail. In the image processing apparatus 10, the reconstruction device 20 can be reconfigured at a predetermined timing (for example, when image data compression is instructed or new image data is input), or dynamically reconfigured. It is also possible to do. Here, the dynamic reconfiguration refers to reconfiguration at a fluid timing, that is, a timing that is not determined in advance.

  FIG. 3 is a flowchart showing a procedure for dynamic reconfiguration. This flowchart is based on the premise that processing for certain image data is continued, and the reconstruction condition is evaluated at an appropriate timing (for example, every pixel or every line) (S10). That is, it is evaluated what processing should be performed on the image data and whether the current image processing configuration can be implemented (S12). The determination of what processing should be performed can be made in various ways. For example, the processing may be performed based on the condition for the input image data or the corresponding intermediate data (for example, the condition for the absolute value of luminance). However, it may be performed using conditions (for example, luminance contrast with the surroundings) for data input in the vicinity of these data. It is also possible to evaluate in consideration of the tendency of data processing performed before the data. As a result of the evaluation (S12), when it is determined that the current image processing configuration can be used, the processing is continued (S14). When it is determined that the current image processing configuration cannot be used, input of image data is temporarily performed. (S16), and after the reconfiguration is performed (S18), the process is executed (S14). By repeating this sequentially, dynamic reconstruction is repeated in a series of image processing.

  FIG. 4 is a schematic view illustrating a configuration that can be switched by dynamic reconfiguration. Here, it is assumed that image processing X is always performed on image data, and then either image processing A or image processing B is performed. In the reconfiguration circuit 22, the configuration shown in FIG. 4A and the configuration shown in FIG. 4B are alternatively configured.

  In the mode shown in FIG. 4A, the reconstruction circuit 22 includes an X processing unit 80 in which a logic circuit Lx for performing image processing X is set and an A in which a logic circuit La for performing image processing A is constructed. A processing unit 82 is arranged. The X processing unit 80 refers to (inputs) the input image data and performs image processing X to generate intermediate data Dx. Then, the A processing unit 82 performs image processing A with reference to the intermediate data Dx, and outputs output data representing the final result. The next image data is input to the X processing unit 80 by the time when the A processing unit 82 refers to the intermediate data Dx at the latest. That is, on the reconstruction circuit 22, processing for a plurality of image data is performed in parallel with a time difference. Note that the X processing unit 80 and the A processing unit 82 may internally hold data other than the intermediate data Dx and perform data processing with reference to the data.

  Here, as a result of the evaluation of the reconstruction condition, it is assumed that image processing B should be performed on certain intermediate data Dx and it is determined that reconstruction is necessary. In this case, the reconfiguration circuit 22 is completely reconfigured, and the circuit shown in FIG. 4B is arranged. That is, the reconstruction circuit 22 includes an X processing unit 84 in which a logic circuit Lx ′ for performing image processing X is set and a B processing unit 86 in which a logic circuit Lb for performing image processing B is constructed. Yes. The logic circuit Lx ′ is the same circuit as the logic circuit Lx in FIG. 4A, but is re-configured, and therefore is denoted by the symbol “′”. The X processing unit 80 and the X processing unit 84 are arranged at the same location in the reconfiguration circuit 22. Here, the same location means a relationship in which each (two-dimensional) coordinate of the logic circuit Lx of the X processing unit 80 and each coordinate of the logic circuit Lx ′ of the X processing unit 84 are equal in the reconstruction circuit 22. For example, the upper left coordinates (X11, Y11) and the lower right coordinates (X12, Y12) of the X processing unit 80 are set, the upper left coordinates of the X processing unit 84 are (X21, Y21), and the lower right coordinates are (X22, Y12). If attention is paid to these coordinates as Y22), the conditional expressions X11 = X21, X12 = X22, Y11 = Y21, Y12 = Y22 are satisfied. In the X processing unit 84, the intermediate data Dx held in the X processing unit 80 before reconfiguration is maintained. That is, before reconfiguration and after reconfiguration, intermediate data having the same value is held at the same location in the reconfiguration circuit 22 (that is, the location where the coordinates in the reconfiguration circuit 22 are the same). On the other hand, the B processing unit 86 does not need to be disposed at the same location as the A processing unit 82. However, at least the B processing unit 86 is arranged at a location where the intermediate data Dx can be referred to.

  When the reconstruction is completed, the B processing unit 86 inputs the intermediate data Dx from the X processing unit 80 and performs the image processing B. The X processing unit 84 inputs new image data and performs image processing X. That is, in the configuration illustrated in FIG. 4, only the A processing unit 82 in the reconfiguration circuit 22 is apparently reconfigured as if it was changed to the B processing unit 86. In other words, in the example described with reference to FIG. 4, a circuit capable of partial reconfiguration is constructed in a pseudo manner. Thus, since the B processing unit 86 continues processing the intermediate data held in the reconfiguration circuit 22 using Dx, the intermediate data Dx is not recalculated, and the intermediate data Dx is stored in the memory. Is not saved or re-entered. Here, for reference, a mode in which the intermediate data Dx is saved in the memory and re-input after reconfiguration will be mentioned. For example, in the case of an A4 size document having an input resolution of 600 dpi, assuming that one pixel is processed in one clock, the processing time (32M clock) for a maximum of 32M pixels is taken to save and re-input intermediate data Dx. Will do.

  FIG. 5 is a diagram corresponding to FIG. 4 and is a schematic diagram illustrating another configuration that can be switched by dynamic reconfiguration. In this example, as in the example shown with reference to FIG. 4, image processing X is always performed on image data, and then either image processing A or image processing B is performed. Therefore, the reconstruction circuit 22 includes a configuration in which the X processing unit 80 and the A processing unit 90 shown in FIG. 5A are arranged, and an X processing unit 84 and a B processing unit 110 shown in FIG. The arranged configuration is appropriately constructed by reconfiguration. The X processing units 80 and 84 in FIGS. 5A and 5B perform the same image processing X as the X processing units 80 and 84 in FIGS. 4A and 4B, and the intermediate data Dx is obtained. The same applies to the point of generation. However, the A processing unit 90 and the B processing unit 110 in FIGS. 5A and 5B are different from the A processing unit 82 and the B processing unit 86 in FIGS. 4A and 4B.

  The A processing unit 90 performs image processing A by pipeline processing including four stages. Pipeline processing is processing that has a plurality of stages that sequentially transfer processing from upstream to downstream, and processes the plurality of input data in parallel with a time difference by synchronizing each stage. For this reason, the A processing unit 90 is provided with processing units of stages 92, 94, 96, and 98 each including logic circuits La1, La2, La3, and La4, and is set so that data flows in this order. Yes. That is, the stage 92 refers to the intermediate data Dx held by the X processing unit 80, performs image processing by the logic circuit La1, and generates intermediate data Da1. Then, the stage 94 refers to the intermediate data Da1, performs image processing by the logic circuit La2, and generates intermediate data Da2. Similarly, the stage 96 refers to the intermediate data Da2 and performs image processing by the logic circuit La3 to generate intermediate data Da3. The stage 98 refers to the intermediate data Da3 and performs image processing by the logic circuit La4. To generate output data Da4.

  The A processing unit 90 is also provided with two stages 100 and 102 for performing the image processing B by pipeline processing. The stage 100 includes a logic circuit Lb1 and holds intermediate data Db1, and the stage 102 includes a logic circuit Lb2 and holds intermediate data Db2. However, the stages 100 and 102 are isolated from the surroundings so as not to input / output new data, and are set not to perform new image processing calculations.

  When the reconstruction conditions are evaluated and it is determined that the reconstruction is necessary, the entire reconstruction is performed, and the circuit shown in FIG. 5B is arranged. The arranged B processing unit 110 performs data processing different from that of the A processing unit 90, but is arranged at a place where the A processing unit 90 is arranged (a place where at least some of the coordinates overlap). ing. As an example, the upper left coordinate of the A processing unit 82 in the reconstruction circuit 22 is (X11, Y11), the lower right coordinate is (X12, Y12), and the upper left coordinate of the B processing unit 86 is (X21, Y21). If the lower right coordinates are (X22, Y22) and attention is paid to these two points, an arrangement that satisfies the conditional expressions X11 ≦ X21 <X22 ≦ X12 and Y11 ≦ Y21 <Y22 ≦ Y12 can be given. . The B processing unit 110 is similar in configuration to the A processing unit 90, and corresponds to the stages 92, 94, 96, and 98 included in the A processing unit 90, and the stages 112, 114, 116, 118. That is, the stages 112 to 118 are respectively provided with logic circuits La1 ′ to La4 ′ (these are the same as La1 to La4 but are marked with “′” to indicate that they have been reconfigured), and Intermediate data Da1 to Da4 are held. However, each of these stages 112 to 118 is isolated from the surroundings, and is set not to perform a new image processing calculation.

  The B processing unit 110 further includes stages 120 and 122 for performing image processing B corresponding to the stages 100 and 102 included in the A processing unit 90. That is, the stages 120 and 122 include logic circuits Lb1 ′ and Lb2 ′ (which are the same as Lb1 and Lb2, respectively, but are marked with “′” to indicate that they have been reconfigured), and Intermediate data Db1 and Db2 are held. The stages 120 and 122 are set so that the image processing B can be performed. Specifically, the stage 120 is set to update the intermediate data Db1 by referring to the intermediate data Dx held by the X processing unit 84 and performing an operation by the logic circuit Lb1 '. The stage 122 is set to update the output data Db2 by referring to the intermediate data Db1 held by the stage 120 and performing an operation by the logic circuit Lb2 '.

  The intermediate data Db1 and Db2 held by the stages 120 and 122 immediately after the reconfiguration are preserved since the B processing unit 110 was previously constructed. That is, the B processing unit 110 performs the interrupted image processing B using the intermediate data Db1 and Db2 held in the pipeline. In the B processing unit 110, as described above, the intermediate data Da1 to Da4 held by the stages 92 to 98 for the image processing A are maintained, and when the A processing unit 90 is configured, these are performed. The processing is continued using the intermediate data Da1 to Da4.

  In the embodiment shown in FIG. 5, logic circuits that are not actually used are also formally arranged. However, when not used, the logic circuit is not provided (the logic circuit is actively deleted), the retained data is simply left, and the logic circuit is rearranged again at the stage of adoption. You may make it do. In other words, if it is desired to reuse the intermediate data updated and held by a certain logic circuit in the future, the area where the intermediate data is held is the same at the time of reconfiguration unless this logic circuit is required again. It can be set as an “arrangement prohibition area” in which another logic circuit should not be provided.

  Here, as a reference mode, FIG. 6 shows a mode in which the image processes A and B are switched without performing reconstruction. In the configuration shown in FIG. 6, as in FIG. 5A, stages 92 to 98 and stages 100 and 102 are provided, and these are connected together to pipeline the image processing A and the pipeline of the image processing B. Is forming. Further, delay circuits 134 and 136 made of flip-flops are provided behind the stages 100 and 102, and the number of stages of the image processing B is formally set to be the same as the number of stages of the image processing A, and data is input. The output order is maintained. In addition, a determination unit 130 is provided in parallel with both pipelines, and a selection circuit 132 is provided downstream of both pipelines.

  In this configuration, the image data is input to both pipelines and the determination unit 130. Then, in addition to executing both image processing A and image processing B, the determination unit 130 determines which processing result is adopted. The selection circuit 132 selects one of the outputs based on the determination result of the determination unit 130.

  In the configuration shown in FIG. 6, unlike the configuration shown in FIG. 5, no reconfiguration is performed. Instead, even when the result of the image processing B having a short pipeline is adopted, the output is performed after waiting for the result of the image processing A having a long pipeline. On the other hand, in the reconstruction shown in FIG. 5, when the delay circuits 134 and 136 shown in FIG. 6 are not adopted and a short pipeline (image processing B) is performed, a long pipeline (image processing) is used. A waiting time to synchronize with A) becomes unnecessary. In the mode shown in FIG. 5, there is a possibility that the data arrangement order may be changed due to the difference in the length of the pipeline. In order to avoid this, the data arrangement order may be adjusted as described below.

  Next, a specific example in which two image processing units that perform pipeline processing are sequentially reconfigured will be described with reference to FIGS. 7 and 8. In this example, either 5 × 5 pixel filter processing or 3 × 3 pixel filter processing is performed on image data.

  FIGS. 7A and 7B are block diagrams showing two configurations switched in this filter processing. The figure includes an input switch 150, a reconstruction circuit 22, an SRAM 178, and a pixel counter 180. The input switch 150, the SRAM 178, and the pixel counter 180 are configured using, for example, an input / output switch or an SRAM on the reconstruction device 20. The reconstruction circuit 22 includes a TI (text / image) separation processing unit 152, a reconstruction condition evaluation unit 154, a reconstruction event generator 156, a FIFO 158, an image processing unit 160, a pixel counter 170, and a FIFO-A 172. , And FIFO-B174 have been constructed.

  The input switch 150 sequentially inputs image data in units of one pixel to the TI separation processing unit 152. Sequential input means that data elements are input one after another over a certain long period. Input may be performed continuously or at intervals. The input interval may be irregular. The image data may be 1-bit data, but typically consists of a plurality of bits.

  The TI separation processing unit 152 determines whether the input pixel is located in a text area representing characters, numbers, symbols, or the like, or an image area representing a photograph, a figure, or the like, and Tag data representing the discrimination result Is added to the input image data and output to the reconstruction condition evaluation unit 154. The text region is subjected to filter processing of a 3 × 3 image having a small window size in order to emphasize edges, and the image region is subjected to filter processing of 5 × 5 pixels having a large window size for smoothing. Will be given.

  The reconstruction condition evaluation unit 154 evaluates the value of Tag data based on a preset condition. Specifically, when the value of the Tag data does not change, it is evaluated that the reconfiguration of the reconfiguration circuit 22 is unnecessary, and the evaluation result is output to the reconfiguration event generator 156 and the FIFO 158. On the other hand, when the value of Tag data changes, that is, when the text area changes to the image area, or when the image area changes to the text area, it is evaluated that the reconstruction should be performed. Output to the reconfiguration event generator 156 and the FIFO 158. Further, the reconstruction condition evaluation unit 154 outputs image data to the FIFO 158 when the writable signal (WE) is given from the FIFO 158.

  The reconfiguration event generator 156 is a device constructed using the PE 30 shown in FIG. 1, and when the evaluation result indicating that reconfiguration is to be performed is received from the reconfiguration condition evaluation unit 154, the reconfiguration event generator 156 is shown in FIG. A signal to that effect is transmitted to the control circuit 32. The FIFO 158 is a first-in first-out data storage unit that absorbs a difference in processing speed between the TI separation processing unit 152 and two types of filters (a 5 × 5 filter processing unit 164 and a 3 × 3 filter processing unit 168 described later). It is provided to buffer image data for the clock time required for reconstruction. A write enable signal (WE) is transmitted from the FIFO 158 to the reconstruction condition evaluation unit 154, and the data input timing is controlled. The FIFO 158 transmits a readable signal (RE) to the image processing unit 160. The image processing unit 160 reads image data from the FIFO 158 based on this signal.

  In the configuration of FIG. 7A, the image processing unit 160 is provided with a common circuit 162 and a 5 × 5 filter processing unit (corresponding to the A processing unit in the example of FIG. 5) 164, and 3 × 3 The filter processing unit (also corresponding to the B processing unit) 168 is formally arranged. That is, the common circuit 162 receives image data and performs preprocessing, and the 5 × 5 filter processing unit 164 performs filter processing subsequently. The 3 × 3 filter processing unit 168 does not perform any particular processing.

  The pixel counter 170 counts input of image data from the FIFO 158 to the image processing unit 160. The counting is performed based on a signal from the FIFO 158. Then, the pixel counter 170 generates an address of image data corresponding to each count and stores it in the FIFO-A 172.

  When image data is output from the image processing unit 160, a read signal (RE) is sent to the FIFO-A 172, and an address where output data is to be stored in the SRAM 178 is transmitted from the FIFO-A 172. The output data output from the 5 × 5 filter processing unit 164 of the image processing unit 160 is stored at this address. As a result, the output data is stored in the SRAM 178 in the order corresponding to the original image data. Output data is output from the SRAM 178 at an appropriate timing, and the pixel counter 180 counts the number.

  When a reconfiguration instruction is issued from the reconfiguration event generator 156, the reconfiguration circuit 22 is completely reconfigured to reconfigure the circuit arrangement shown in FIG. 7B. However, the arrangement after the reconstruction is the same in many parts as before the reconstruction, the FIFO-B 174 is used instead of the FIFO-A 172, and the 5 × 5 filter processing unit 164 in the image processing unit 160. The only difference is that a 3 × 3 filter processing unit 168 is used instead. That is, the image processing unit 160 performs 3 × 3 pixel filter processing, and the output data is stored in the SRAM 178 according to the address from the FIFO-B 174.

  FIG. 8 is a diagram for explaining in detail the configuration of the image processing unit 160 shown in FIG. The common circuit 162 includes FIFOs 190, 192, 194, and 196 that store five data therein, and a tap unit 200 provided with 5 × 5 taps. That is, the input image data includes taps 202, 204,. . . As described above, first, the data is sequentially flowed to the uppermost tap and is stored in the FIFO 190. When the image data sent to the uppermost tap disappears, the image data is sequentially sent from the FIFO 190 to the second tap and stored in the FIFO 192. In this way, the image data is sequentially passed through the taps from the top to the bottom. Focusing on the entire tap unit 200, the oldest input image data is stored in the lower right tap of the tap unit 200, and the latest input image data is stored in the upper left tap 202. Become.

  In the configuration shown in FIG. 8A, the input logic of the connection is set so that data is input from all the taps of the tap unit 200 to the 5 × 5 filter processing unit 164. Then, the 5 × 5 filter processing unit 164 performs filter processing on the pixels of the central tap 210 in the tap unit 200 based on the entire image data of 5 × 5 pixels. In the calculation of the filter processing, for example, a product-sum operation with a filter coefficient corresponding to Laplacian is performed.

  On the other hand, in the configuration shown in FIG. 8B, the tap unit 200 has image data arranged on all 5 × 5 taps. However, the input logic is set in the 3 × 3 filter processing unit 168 so that only 3 × 3 pixel image data near the center of the tap unit 200 is input. Filter processing is performed based on the image data of × 3 pixels. In this way, the tap unit 200 is set so that necessary image data can be output to any size filter processing unit before and after reconstruction, and is therefore independent of both filter processing units. The common circuit 162 is provided. Note that the 5 × 5 filter processing unit 164 and the 3 × 3 filter processing unit 168 are arranged at the same location (as in the example shown in FIG. 4, the other is arranged after reconfiguration at the location where one was arranged. It is also possible to In this case, the intermediate data in the filter is not held, so that the reconstruction may be waited until the intermediate data flows through these filters. When the common circuit 162 is provided and the data processing unique to each filter is reduced as in the illustrated example, the time for the intermediate data to flow through the filter is relatively short (for example, about several tens of clocks).

  In the above description, data processing for image data has been described in mind. However, this embodiment can also be applied to data processing of various data other than image data (for example, audio data, observation data, simulation data, etc.). In the above description, examples of processing units that are common before and after reconfiguration have been described as being arranged at the same location. However, although not the same location, it is possible to utilize data held before reconfiguration. It is also possible to arrange at corresponding locations. For example, when a register or memory value can be referred to from a plurality of PEs, there is a possibility that a processing unit can be arranged for any PE.

It is a figure which shows the hardware structural example of the image processing apparatus concerning this Embodiment. It is a figure which shows the outline of the structural example of PE. It is a flowchart which shows the example of the procedure of a reconstruction. It is a block diagram which shows the example of a reconstruction. It is a block diagram which shows another reconstruction example. FIG. 6 is a reference diagram related to the example of FIG. 5. It is a block diagram which shows the specific example of a reconstruction. It is a figure which shows a part of structure of FIG. 7 in detail.

Explanation of symbols

  10 image processing apparatus, 20 reconstruction device, 22 reconstruction circuit, 23, 24, 30 PE, 32 control circuit, 34 memory, 40 internal bus, 42 CPU, 44 memory, 46 printer, 48 scanner, 50 UI, 52 CDD , 54 network IF, 60 network, 70, 72, 76 register, 74 ALU, 78 control signal, 80, 84 X processing unit, 82, 90 A processing unit, 86, 110 B processing unit, 130 determination unit, 132 selection circuit , 150 input switch, 152 TI separation processing unit, 154 reconstruction condition evaluation unit, 156 reconstruction event generator, 158 FIFO, 160 image processing unit, 162 common circuit, 164 5 × 5 filter processing unit, 168 3 × 3 filter Processing unit, 170,180 pixel counter, 172 FIFO- , 174 FIFO-B, 178 SRAM, 200 tap part.

Claims (13)

Arrangement of multiple data processing that is arranged in an arithmetic circuit that can be logically reconstructed and that can maintain the retained data before and after the reconfiguration, while referring to and updating the retained data A data processing unit to implement;
Determining means for determining whether or not to change a data process in the plurality of data processes to another data process;
Relocation means for reconfiguring the arithmetic circuit based on the determination result of the determination means, and relocating the data processing unit;
With
The relocation means is configured to change the data processing so that the certain data processing is changed to the other data processing, and so that at least a part of the data processing that is not changed is performed at a location corresponding to that before the relocation. Rearrange the parts,
The data processing unit, after rearrangement by the rearrangement unit, refers to data held from before the rearrangement at a location corresponding to the pre-arrangement, and performs the other data processing. Data processing device. The data processing apparatus according to claim 1,
The location corresponding to before the rearrangement is the same location as before the rearrangement on the arithmetic circuit. The data processing apparatus according to claim 1,
In the case where the certain data processing is changed to the other data processing, the rearrangement unit sets the data processing unit so that the other data processing is performed at a place where the certain data processing is performed. A data processing device characterized by being arranged. The data processing apparatus according to claim 1,
When the rearrangement unit changes the certain data processing to the other data processing, the other data processing to be rearranged does not update the data referenced or updated by the certain data processing. When the data processing unit is rearranged and then re-changed to the certain data processing, the data processing unit is rearranged so that the certain data processing is performed at a location corresponding to the previous one. A data processing apparatus. The data processing apparatus according to claim 4, wherein
The data processing apparatus according to claim 1, wherein the part corresponding to the previous part is the same part as before. The data processing apparatus according to claim 4, wherein
The certain data processing is performed in parallel with a time difference by processing a plurality of data by performing processing in synchronization with a plurality of stages that sequentially pass processing from upstream to downstream,
The data processing device includes an adjustment mechanism that adjusts an arrangement order of data output from the certain data processing and data output from the other data processing. The data processing apparatus according to claim 6, wherein
The other data processing is performed in parallel with a time difference by processing a plurality of data by performing processing in synchronization with a plurality of stages that sequentially pass processing from upstream to downstream,
The plurality of stages in the other data processing is shorter than the plurality of stages in the certain data processing,
A data processing apparatus characterized in that data is output earlier from the other data processing than the certain data processing. The data processing apparatus according to claim 1,
It has an input unit to input data sequentially,
A data processing apparatus, wherein the data processing unit performs the plurality of associated data processing on each input data. The data processing apparatus according to claim 8, wherein
The data processing apparatus according to claim 1, wherein the determination unit determines whether to change the certain data processing to the other data processing for each input data. The data processing apparatus according to any one of claims 1 to 9,
The data processing apparatus, wherein the plurality of data processing performed by the data processing unit is data processing on image data. The data processing apparatus according to claim 10, wherein
The certain data processing and the other data processing are different in the width of the pixel range of the data to be referred to,
The at least some data processing set to be executed at a location corresponding to the location before the rearrangement by the placement of the rearrangement unit refers to both the one data processing and the other data processing in common. A data processing apparatus comprising: an array holding process for arranging and holding the data in an order of possible arrangement. A data processing device according to claim 10 or 11,
Generating means for generating the image data, or printing means for performing printing based on the image data;
An image processing apparatus comprising: An arithmetic circuit capable of logical reconfiguration and capable of preserving retained data before and after reconfiguration;
A data processing unit that is arranged in the arithmetic circuit and performs a plurality of associated data processing while referring to and updating stored data;
Determining means for determining whether or not to change a data process in the plurality of data processes to another data process;
Relocation means for reconfiguring the arithmetic circuit based on the determination result of the determination means, and relocating the data processing unit;
In a computer comprising:
The data so that the data processing is changed to the other data processing, and at least a part of the data processing that is not changed is performed at a location corresponding to that before the rearrangement. Rearrange the processing parts,
After the rearrangement by the rearrangement unit, the data processing unit is referred to the data held from before the rearrangement in the location corresponding to the pre-arrangement, and the other data processing is performed.
A data processing program characterized by that.

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