JP2001171184A - Image data-processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image data-processing apparatus which rotates image data with a small memory capacity at a high speed when a bit map development direction and a paper transfer direction are different from each other. SOLUTION: The apparatus has a page memory in which image data developed to a bit map are stored in units of pages, a bit array memory in which image data present at a predetermined block of the page memory is stored by reading out the data for every bit arrangement aligned in a predetermined line direction, a rotation process control means for taking out image data stored in the bit array memory for every line of a direction different from the bit arrangement direction, a line buffer memory for storing image data taken out by the rotation process control means in a predetermined order, and an image data output means for sequentially outputting image data stored in the line buffer memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing apparatus, and more particularly, to an apparatus which requires image processing such as a printing apparatus, which speeds up a predetermined conversion process of bitmap data expanded on a memory. Data processing apparatus for the same.

[0002]

2. Description of the Related Art In general,
The printing paper is determined to have a predetermined size such as A3, A4, or B4, but is a rectangle having different vertical and horizontal lengths.
When the printing paper is set in the printer device, the long side of the paper is aligned with the conveyance port so that the short side of the paper is in the conveyance direction of the paper (FIG. 13A). There is a case where the paper is aligned with the mouth so that the long side of the paper is in the transport direction of the paper (FIG. 13B).

In particular, in a printing apparatus capable of feeding up to A3 paper, A3 paper is generally set in a portrait direction (longitudinal direction) as shown in FIG. 13B, while A4 paper is set in FIG. As shown in (a), the image is set in a so-called landscape direction (horizontally long direction).

When executing a printing function on a personal computer or the like,
In general, an instruction for printing in a portrait or landscape orientation is input, and print data is created in accordance with the instruction and transferred to a printing device. For example, when a print instruction input of A3 portrait orientation is input, print data for transporting and printing paper in the portrait orientation is created as shown in FIG. 13B and transferred to the printing apparatus. At this time, if the paper is set in the printing apparatus as shown in FIG. 13B, the transferred print data and the transport direction of the paper coincide with each other. Should be expanded to

[0005] However, when the transferred print data is different from the paper transport direction, a special conversion process needs to be performed. For example, A4 paper is used in the printing device as shown in FIG.
When the print instruction is input in the A4 portrait direction when the printer is set to carry in the landscape direction and prints as shown in (2), the print data to be transferred is the data to transport and print the paper in the portrait direction. Therefore, it is necessary to perform a conversion process in order to print the print data in the landscape orientation.

The following is required for the conversion process. (1) The font once expanded to bitmap is 90 °
Rotate and write back as bitmap data. (2) Convert the coordinate system and develop the image.

In the case where the transferred print data and the paper conveyance direction are different, the print data in the portrait direction is once subjected to bitmap development as it is, and before the video transfer output, the program is processed in the portrait direction. Data 9
It is necessary to rotate the data by 0 ° and convert it into data in the horizontal direction on a page-by-page basis, and this process takes a considerable time.

At this time, since conversion is performed in page units, it is necessary to prepare separate page unit memories for print data before conversion and for print data after conversion, and a large memory capacity is required. Becomes It is also possible to perform this conversion process during the video transfer output process. However, if the video transfer rate is increased, the speed of the program processing for this conversion is slower than the video output speed. This causes a reduction in printing speed as performance.

As described above, in the conventional printing apparatus,
If the developing direction of the print data transferred to the printing device is different from the transport direction of the actually set paper,
Since it is necessary to perform the print data conversion process in units of pages, the printing speed as the basic performance of the printing apparatus is greatly reduced, and it is necessary to prepare at least two data development memories having a page unit capacity in advance. was there.

The present invention has been made in view of the above points, and by performing processing for converting print data for each block in a certain area, it is possible to save memory for expansion and to further reduce the paper size. The present invention is to provide an image data processing apparatus which does not cause a decrease in printing speed even when the transport direction of the image does not match the designated printing direction.

[0011]

According to the present invention, there is provided a page memory in which bitmap-deployed image data is stored in units of pages, and image data present in a predetermined block of the page memory arranged in a predetermined line direction. A bit array memory read and stored for each array, rotation processing control means for extracting image data for each line in a direction different from the bit array direction with respect to the image data stored in the bit array memory, and rotation processing control An image data processing apparatus comprising: a line buffer memory storing image data taken out by means in a predetermined order; and image data output means for sequentially reading out image data stored in the line buffer memory. Is what you do.

Further, the line buffer of the present invention comprises:
When the one line buffer is used to store the image data extracted by the rotation processing control means, the other line buffer is read by the image data output means. The two line buffers are used cyclically exclusively to each other. Here, a line buffer switching means for cyclically using the two line buffers may be further provided.

Further, each of the plurality of bit arrays stored in the bit array memory may have a unit word length. The unit word length is, for example, 8 bits,
They are 16 bits, 32 bits, and 64 bits.

When the image data stored in the page memory is data developed in the portrait direction, the block is constituted by a predetermined number of bit arrays on lines arranged in the portrait direction, The image data retrieved from the bit array memory by the rotation processing control means is a second bit array on a line arranged in a direction perpendicular to the portrait direction. That is, the bit arrangement constituting the block and the second bit arrangement are different in the 90 ° direction.

Further, the present invention comprises the above-described image data processing apparatus and a paper transport means, and a developing direction of the image data stored in the page memory, and a transport of the paper set in the paper transport means. If the direction is different, the rotation processing control means extracts the image data for each line in a direction different from the direction of the bit array of the image data stored in the bit array memory. Things.

The page memory is constituted by a rewritable memory, and for example, an SRAM, a DRAM or the like can be used. The data stored in the page memory is data created in one page, and the page memory has a capacity capable of storing all data of one unit printed by a page printer, for example.

The bit array memory is a rewritable memory having a smaller memory capacity than the page memory, and stores data contained in a predetermined block of the page memory. Here, the block is a matrix-shaped area, and refers to, for example, a planar storage space in which the vertical direction and the horizontal direction are each one word long. At this time, the number of lines corresponding to the length of one word is arranged in the vertical direction, and each line is composed of a bit array of the number of one word. However, the vertical and horizontal lengths of the block are not limited to this, and may be a plurality of words. One word varies depending on the processor and hardware that execute the image data processing of the present invention, but in the embodiment of the present invention described below, one word is 32 bits.

When the image data stored in the page memory is bitmap data expanded in a so-called portrait direction, the vertical direction of the block is the portrait direction and the horizontal direction of the block is the landscape direction. . That is, in the block, a plurality of lines are arranged in the portrait direction, and the direction of the bit array forming each line is the landscape direction.

On the other hand, the image data taken out by the rotation processing control means uses one unit of a bit array arranged on a line in a direction different from the direction in which the bit arrays are arranged. Here, the different direction means a direction in which this bit array is rotated by 90 °. For example, in the bitmap data expanded in the portrait direction, the direction of the bit array on the bit array memory is the landscape direction, but the direction of the image data taken out by the rotation processing control means is the portrait rotated by 90 °. Direction.

The line buffer is composed of a rewritable memory having a smaller capacity than the page memory. For example, an SRAM, a DRAM, or the like can be used. For example, if the bit array memory has a size of 1 word × 1 word and the page memory has a size of n lines in the portrait direction and m words in the landscape direction, the line buffer is It is sufficient to have a capacity of at least one word × n lines.

The order of storing the image data in the line buffer is, for example, assuming that the paper transport direction of the printing apparatus is the landscape direction, and the image data is sequentially stored at a position such that the printing direction of the image data is the landscape direction. I should go.

The rotation processing control means and the image data output means can be realized by a so-called processor (CPU). The image data processing device includes a processor, RAM, RO
M, timer, I / O controller, etc., ROM
The processing of each means is executed by the CPU executing the control program stored in the CPU or the like. Further, the line buffer switching means can be executed by a microprocessor, but is preferably implemented by hardware independent of the CPU in order to reduce the load on the CPU.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings. Note that the present invention is not limited to this. FIG. 1 is a schematic block diagram of a first embodiment of an image data processing apparatus in a printing apparatus according to the present invention. In FIG. 1, the printing apparatus includes an image data processing device 1 and a printer engine 12.

The host 11 is a sender of print data such as a so-called personal computer. The image data processing apparatus 1 includes a processor (CPU) 2, a ROM storing a program for printing processing, a RAM storing various setting data, a peripheral I / F for communicating with the host 11, font information such as print characters, and the like. ROM 7, a bitmap memory for developing the transferred print data in a bitmap format, a bit array 13 and a line buffer 14 used in the conversion process, which is a feature of the present invention, and a printer engine 12. A video output unit 8 that outputs image data converted to a format, a printer I / F unit 9 that controls the operation of the video output unit 8 and controls the exchange of commands and status between the printer engine 12 and the processor 2. It is composed of The printer engine 12 includes a so-called paper transport mechanism and an image forming mechanism using a semiconductor laser or the like.

Here, the bitmap memory 5 is a memory having a capacity enough to store bitmap data for one page. Normally, the bitmap memory 5 is obtained by directly expanding the print data transferred from the host 11 into a bitmap. Is stored.

The bit array 13 is a memory for extracting a part of the data developed in the bit map memory 5 and changing the direction of the data arrangement. The direction conversion refers to converting the arrangement of bits in the vertical direction (vertical bit array) to the arrangement of bits in the horizontal direction (horizontal bit array), or vice versa. A description will be given of a case where the bit array of (Late) is converted into a bit array of a landscape (landscape) direction. That is, a description will be given of conversion in a case where print data transferred as portrait data (portrait) and expanded in portrait direction is transported in the landscape direction (landscape) and printed. Hereinafter, this direction conversion is referred to as rotation processing.

The line buffer 14 is a bit array 1
3 is a memory for taking out data for each word from the data stored in No. 3 and storing it.

FIG. 2 is an explanatory diagram of one embodiment of the contents stored in the bit map memory. In FIG. 2, the host 11
4 shows a case where data in a vertically long direction (portrait direction) is transferred from the memory and is developed on the bit map memory 5. The bitmap memory 5 has a capacity capable of storing data for one page of paper. The long side in the vertical direction is composed of X lines, and the short side in the horizontal direction is m words. . Further, if 1 word = 32 bits, one line is composed of m words.
Consists of bits.

One word consists of bits named numbers 0 to 31. In FIG. 2A, 1
Assuming that the address of one word at the left end of the line is n, 1
The right end of the line is address n + m-1. Hereinafter, similarly, the address of one word at the left end of the second line is n + m,
The right end is represented by n + 2m-1, the address of the leftmost word on the bottom X line is n + (x-1) m, and the address of the rightmost word is n + xm-1. It is assumed that the processor 2 can handle one word, that is, data having a 32-bit width.

Here, the bit array 13 is a memory composed of a matrix area of 32 bits × 32 bits. Words in a partial area of the bitmap data are stored here as needed. For example, FIG.
(A) from address n + (x−32) m to address n +
Data of 32 words up to (x−1) m are stored in the bit array 13.

FIG. 3 is a block diagram showing an embodiment of the line buffer 14. As shown in FIG. The line buffer 14 has x / 32 in the horizontal direction.
It is composed of a memory having a length of a word and a size of 32 bits in the vertical direction. As will be described later, the line buffer 14 stores the data of the block read into the bit array 13 in an arrangement rotated by 90 °.

In FIG. 2A, the address n +
32 consisting of (x−32) m,..., N + (x−1) m
The block 1 corresponding to a word is a first processing unit of “rotation processing by a bit array” described later. The block of the first processing unit is sequentially processed in the X-line direction (vertical upward direction) in FIG. 2A, and data of one word and X lines (this is referred to as a second processing unit). Are first stored in the line buffer 14.

That is, addresses n, n + m,..., N
+ (X−32) m,..., N + (x−1) m data of block 2 is the second processing unit. This second
Is transferred to the bit output unit 8 in this unit as described later. Therefore, the capacity of the line buffer 14 is required for the second processing unit. In the case of FIG. 21A, the number of lines in the vertical direction, that is, the long side direction is “X”. A memory having a size corresponding to the number of lines corresponding to x / 32 words in the horizontal direction and one word (32) bits in the vertical direction, that is, 32 lines is required.

In the line buffer 14 shown in FIG. 3, if one word at the left end of the first line (line No. 31) in the horizontal direction is an address a, the address at the right end is a + (x / 32-1). ), And the left end of the second line (the line of number 30) is a + x / 32.
The leftmost address of the lowermost line (the line with the number 0) of the line buffer 14 is a + 31x / 32.

In this embodiment, the number of lines X in the long side direction is preferably a multiple of 32, but the number of lines X
Is not a multiple of 32, an all-white line is added so that the total number of lines is a multiple of 32. FIG. 2D shows a state in which the data of the block 1 is read and stored in the bit array 13. That is, the uppermost row 31 of the bit array 13 stores data of one word at the address n + (x−1) m, and the lowermost row 0 stores data of one word at the address n + (x−32) m. Have been.

FIG. 5 shows a configuration diagram of an embodiment of the bit array of the present invention. In this embodiment, the bit array 13
Is composed of 32 × 32 bit cells, and each cell can be composed of a combination of several logic elements and flip-flops. For example, the basic configuration 1 of the cell (reference numeral 13)
In a), the data input of the flip-flop 13-1 is selectively input by a multiplexer including AND-OR gates (13-2, 3, 4).

At the time of writing data to the bit array 13 (W
In the RITE signal = '1'), the X coordinate is the same,
The output (the signal of MTX (X, Y-1)) of the flip-flop of the cell whose Y coordinate is smaller by 1, that is, the cell immediately below is input to the flip-flop 13-1. When data is read from the bit array 13 (READ signal =
In “1”), the position where the Y coordinate is the same and the X coordinate is larger by 1, that is, the output (MTX (X + 1, Y) signal) of the flip-flop of the cell on the right is the flip-flop 1
Input to 3-1. The READ signal or the WRITE signal is supplied from the system bus, and is output from the NOR gate 13-5.
To the flip-flop 13-1.

When the bit array 13 is configured as described above, writing of data to the bit array 13 is performed by using 32-bit data obtained from the data bus (0 to 31 bits) with respect to cells in row units in the horizontal direction. Done. Then, when new data is written for each row, the 32-bit data of the k-th row is written to the row immediately above (k + 1 row). That is, 32-bit data is moved upward one row at a time.

On the other hand, the reading of data from the bit array 13 is performed on cells in the column unit of the bit array in the vertical direction, and is output to the data bus via the output buffer 13-6. When data is read out for each column, the 32-bit data in the i-th column is written in the next left row (i-1 column). That is, 32-bit data is moved leftward by one column.

By the way, the cells in the rightmost column of the bit array 13, that is, 32 cells arranged in the vertical direction where the X coordinate is X = 31, have no data input to these cells at the time of reading. A basic configuration as shown by reference numeral 13b in FIG. 5 may be used. In the basic configuration 13b, when a read signal (READ signal = '1') is input, the input data of the flip-flop 13-1 becomes 0, but at this time, it may be handled as invalid data.

In FIG. 5, the cell at the coordinate position of Y = 0 and X = 0 in the bit array is connected to bit 31 of the data bus of the system, and the cell at the coordinate position of Y = 0 and X = 31 is connected to the system. The 32-bit data (bits 0 to 31) output on the data bus of the system is written to 32 cells which are connected to bit 0 of the data bus and are arranged horizontally at the coordinate position of Y = 0. Will be.

The flip-flop outputs of 32 cells arranged in the vertical direction at the coordinate position of X = 0 are connected to the system bus via a three-state output buffer 13-6 controlled by a read signal (READ signal). And
The output of the cell at the position of X = 0 and Y = 0 is output to bit 0 of the data bus, and the output of the cell at the position of Y = 31 is output to bit 31 of the data bus.

With this configuration, all the cells of the bit array operate simultaneously by the clock input which is the inverted logical signal of the logical sum of the write signal and the read signal whose logic "1" is true. At the time of writing, data on the data bus is written to 32 cells at the coordinates of Y = 0, and the remaining 32 cells in the horizontal direction × 31 cells in the vertical direction (Y = 1 to 31) have the same X coordinate. Then, the data of the cell at the position where the Y coordinate is smaller by 1 is written. That is, the data of the cell at the coordinates of Y = 1 to 31 is shifted by one coordinate in the plus direction of the Y coordinate.

On the other hand, at the time of reading, invalid data is stored in 32 cells in the vertical direction where X = 31, and the remaining 31 cells in the horizontal direction (X = 0 to 30) × 32 cells in the vertical direction have
Data of cells having the same Y coordinate and one larger X coordinate is written. That is, the data of the cell at the coordinates of X = 0 to 30 is shifted by one coordinate in the minus direction of the X coordinate. The write signal WRITE and the read signal READ are signals that change in a pulse shape for each of the write and read operations of the processor.

FIG. 6 is an explanatory diagram of the timing of the read / write operation for the flip-flop of the bit array according to the present invention. FIG. 6A shows the write timing, and FIG. 6B shows the read timing. The data of the flip-flop in the cell changes at the timing of the falling edge of the write signal or the timing of the falling edge of the read signal. Since the write signal or the read signal is logically inverted by the NOR gate 13-5, the falling edge of the write signal or the read signal is the rising edge at the clock input of the flip-flop.

Next, a description will be given of a process for storing print data developed into a bitmap into a line buffer via a bit array. The following processing is performed by the processor 2
Is performed based on a control program stored in a ROM or the like.

When the print data (portrait image) in the portrait direction is changed to the print data (landscape image) in the landscape direction, all the data are rotated by 90 °, but the lower left of the portrait image is positioned at the upper left of the landscape image. Become. Therefore, first, the processing is started from the data at the lower left position in FIG. That is, in the block 2 that is the second processing unit in FIG. 2A, the address n + (x−1) m corresponding to the lower left word in the block 1 that is the first processing unit Read data and write to bit array.

At this time, 1 of address n + (x-1) m
The word data (32 bits) is output on the data bus, and when the write signal (WRITE) falls,
The data is written to 32 cells (referred to as a cell group of line 0) in the horizontal direction at the coordinate of Y = 0 in FIG. FIG. 2 (b)
The state of the bit array after writing (state 1) is shown. At this time, the data of each cell of the lines 31 to 1 of the bit array is shifted in the positive direction of the Y coordinate, but in FIG. 2B, all invalid data is stored as described above.

Next, the address n + (x−
2) 32-bit data in n is Y = 0 in the bit array
Is written to the bottom row (cell group on line 0) at the position of.
At this time, at the same time as the data at the address n + (x−2) m is written, the data written to the cell group at line 0 at the position Y = 0 is replaced with the cell group at line 1 at the position Y = 1. Is written to. That is, one line of 32-bit data (data of address n + (x-1) m) is shifted by one bit in the upward direction of the Y coordinate.

FIG. 2C shows the state of the bit array at this time. As described above, when the data of the block 1 in FIG. 2A is sequentially written to the bit array in word units, the latest 32-bit data is read from the data bus on the line 0 cell at the position of Y = 0. Data written to the group and already written to the bit array
The data is sequentially shifted upward by one line in the upward direction of the Y coordinate.

Therefore, the data of the block 1, that is, the address n + (x-1) m to the address n + (x-3)
2) After 32 words of data up to m have been written into the bit array, the state of the bit array is as shown in FIG. 2 (d). Top row of bit array (line 3
1 cell group) contains data for one word at address n + (x-1) m, and the bottom row (cell group for line 0) contains data for one word at address n + (x-32) m. enter. When the writing of data for one block is completed, data is read from the bit array and written to the line buffer.

FIG. 4 is an explanatory diagram of a process of reading data from a bit array according to the present invention. As described above, reading is performed on data in 32 cells in the vertical direction at X = 0 in FIG. 5 (referred to as a cell group in column 31). That is, 32-bit data rotated by 90 ° with respect to the written data is read. FIG. 4 (b)
2D shows the same state of the bit array as that of FIG. 2D. Here, the 32-bit data in the vertical direction at the position of X = 0, that is, a group of data of the cell group of the column 31 is represented by “a”. ". Hereinafter, 32 of the cell group of the column 30 on the right
A group of bit data is represented as "a + 1", and a group of 32-bit data of the cell group in the rightmost column 0 is represented as "a + 31".

When the processor performs a read operation on the bit array, while the read pulse is "1", the output buffer of the bit array is enabled, and the coordinate X = 0.
Is output on the data bus. At the end of the first read operation, that is, at the falling edge of the read signal, the data in the bit array becomes X
The coordinate is shifted by one coordinate in the minus direction, and X
= 0, the data of the cell group in the column 30 adjacent to the right is shifted to the 32 cells in the vertical direction (cell group in the column 31), and the 32 cells (columns in the vertical direction) of X = 31 are shifted. 0 cell group) becomes invalid data, and the bit array is shown in FIG.
State.

The data 'a' read from the bit array is written by the processor to the address A of the line buffer (see FIG. 4A). That is, since this is the first write, the data is written in the upper left one-word area of the line buffer (the area of bits 31 to 0 of the first line in the vertical direction).

Next, the second reading of the bit array is performed. At this time, the data 'a + 1' in the vertical direction at the coordinate of X = 1 has been shifted to the position of X = 0 at the time of the previous reading, so that at the time of the second reading, the data 'a + 1' is on the data bus. Is output. Then, the processor writes the data 'a + 1' to the address A + x / 32 of the line buffer.

FIG. 4D shows a state where the data “a + 31” of the cell group in the last column, that is, the data in the cell group in column 0 of the bit array in FIG. 2B is shifted to the left end. This data 'a + 31' is output on the data bus in the 32nd read, and is written by the processor at the position of the address A + 31x / 32 in the line buffer. As described above, when the reading process from the bit array is repeated 32 times, the data in the block 1 of the bit map shown in FIG. , A + x / 3
2,..., A + 31x / 32). The above is a series of rotation processing of the bitmap data in the first processing unit.

Next, the processing performed for the first processing unit as described above is repeated for the second processing unit. That is, in the block 2 in FIG. 2A, the above-described write processing to the line buffer via the bit array is performed for each of 32 words in the upward direction. When the rotation process for the entire block 2 is completed,
As shown in FIG. 4A, a landscape image (rotated bitmap data) for 32 lines is stored in the line buffer.

The landscape image stored in the line buffer is stored in the address A, A by the processor.
+1, A + 2,..., A + x / 32-1, A + x / 3
Are read out in the order of 2,... And output to the video output unit 8. The video output unit 8 converts the parallel 32-bit data for each address into serial data and outputs the serial data to the printer engine 12, whereby
Printing in the paper transport direction as shown in FIG.

The output processing from the line buffer to the video output unit and the rotation processing (write processing from the bit map to the bit array) for the remaining second processing unit (block 3) are independent processings that do not affect each other. So,
These two processes can be performed in parallel.

In the case of a 66 MHz system bus clock, it is necessary to convert the data of the block 2 of A4 portrait (long side direction) having a resolution of 600 dpi into a landscape (short side direction) and write the data to the video output unit. The time T can be calculated as follows when the SDRAM (clock latency CL = 3) is used for the memory.

(1) Data transfer time per 1 long word (1 word × 4) = 180 ns (2) Number of dots on long side of A4 portrait = 7040 dots (3) Number of data read from bit map = 7040 words (4) Number of block 2 data written to bit array =
7040 words (5) Number of block 2 data read from bit array = 7040 words (6) Write bit array read data to line buffer = 7040 words (7) Number of write from line buffer to video output unit = 7
040 words

Of the above, five data transfers (3) to (7) are executed by the processor, and the processing time T is represented by the following equation. T = 180 ns × (7040/4) × 5 = 1.584 m
If the processing overhead of the processor is doubled, the total processing time is 2T, and 1.584 ms × 2 =
3.168 ms.

On the other hand, the cycle of one line of our page printer (VSP4701) with a speed of 40 ppm is about 235 μm.
s, the cycle of 32 lines is calculated as 235 μs × 32 = 7.52 ms.

As described above, since the total processing time 2T of the second processing unit is sufficiently faster than the period of 32 lines of the printer engine, it is sufficient to prepare two sets of line buffers for 32 lines. If one is used for conversion / storage and the other is used for output to the video output unit, the data is sequentially rotated (rotated), so that a bit developed in a portrait image can be used without having a memory for rotation processing in page units. The map data can be rotated (converted to landscape data) and output to the video output unit.

Although the data transfer by the processor has been described as an embodiment, the data transfer control master is
An MA controller may be used. Also,
In the above embodiment, the case where the bitmap data expanded in the portrait direction (long side direction) is converted in the landscape direction (short side direction) has been described. On the contrary, the conversion from the landscape to the portrait direction is also performed. It is possible by using similar processing.

In the above embodiment, as shown in FIG. 1, the case where the line buffer 14 is connected to the system bus is considered. However, the line buffer 14 is provided with two sets of line buffers not connected to the system bus. You can also. FIG.
2 is a block diagram showing the configuration of a second embodiment of the image data processing apparatus according to the present invention.

Here, the output side terminal of the bit array 15 is not connected to the system bus, two line buffers 16 are provided (16a, 16b), and both are not connected to the system bus. 1 is different from the configuration of the embodiment shown in FIG. 1 in that a line buffer control circuit 17 for writing data into the video buffer and reading data from the line buffer to the video output unit 8 is newly provided. According to the configuration of FIG. 7, the load on the processor can be reduced. Here, reading and writing are alternately used for the two line buffers (16a and 16b in FIG. 8), but when data read from the bit array 15 is written to one of them, the video output unit is sent from the other. 8 is controlled by the line buffer control circuit 17 so that data is read out.

FIG. 9 shows a configuration diagram of the bit array 15 according to the second embodiment of the present invention. FIG. 5 shown in the first embodiment.
Is different from the bit array 13 in the following two points. 1) FIG.
Is connected to the system bus via the output buffer 13-6, but the bit array 15 in FIG. 9 is not connected to the system bus. 2) In the bit array 15 of FIG.
5c.

The outputs of the two cell groups from the bit array are connected to the multiplexer 15c. One is the output (MTX (0, 0) of 32 cells arranged in the vertical direction at the position of X = 0 similarly to the bit array of FIG.
Y)), and the other is the output (MTX (X, 3) of 32 cells arranged in the horizontal direction at the position of Y = 31.
1)). The output of MTX (X, 31) corresponds to one horizontal word of data written in the bit array, which corresponds to the output when no rotation processing is required. In other words, the output of MTX (X, 31) takes into consideration the case where the direction of the data developed in the bitmap matches the transport direction of the paper when printing, and by providing this output path, The horizontal data written in the bit array can be easily output as it is.

The operation of the multiplexer 15c is controlled by the UNROT signal from the processor. Here, the UNROT signal is a signal indicating whether or not to perform the rotation processing, and UNROT = "1" means that the rotation processing is not performed. At this time, the multiplexer 15c outputs the output M
TX (X, 31) is selected, and the data is sent to the line buffer. Further, UNROT = "0" means that the rotation process is performed. At this time, the multiplexer 15c selects the output MTX (0, Y), and the data is sent to the line buffer.

There are two basic configurations of the bit array 15, as shown in FIG. The basic configuration 1 shown by reference numeral 15a in FIG. 9 is a configuration other than 32 cells arranged in the vertical direction of X = 31, and the basic configuration 2 shown by reference numeral 15b is X = 31 located at the right end of the bit array 15. Is a configuration of 32 cells arranged in the vertical direction. Basic configuration 1 in FIG.
In (2) and (2), a circuit (reference numerals 15-6 and 15-7 in FIG. 9) indicating the logic of reading or writing to the bit array when the rotation processing is not performed, and shifting the data in the minus direction of the X coordinate at the time of reading. A logic for performing a rotation process (reference numeral 15-3 in FIG. 9) is added as a condition.

For example, when no rotation processing is performed at the time of reading, or at the time of writing, that is, UNROT =
“1” and READ = “1” or WRITE =
When “1”, the shift of the data in the plus direction of the Y coordinate is selected. In the case of performing a rotation process at the time of reading, that is, UNROT = "0" and READ =
When "1", data shift in the minus direction of the X coordinate is selected.

Next, FIG. 8 shows a configuration diagram of an embodiment of the line buffer and the line buffer control circuit of the present invention.
Here, the line buffer control circuit 17 controls the bit array 1
5 is for controlling the transfer of the data of the bit array 15 to the video output unit via the line buffer after the data has been written to the data array 5, and can operate in hardware independently of the processing of the processor. is there. The rotation processing of the bitmap data according to the second embodiment of the present invention will be described below. Here, a case is considered in which the bitmap data developed in the portrait direction is rotated in the landscape direction.

In FIG. 8, "WRITE READ"
The "Y" signal is a write permission signal sent from the line buffer control circuit 17 to the processor 2. This "WR" signal is used.
Only when the "ITEREADY" signal is "1", the processor 2 can write data to the bit array 15. This is because the line buffer control circuit 17 reads the data of the bit array 15 during the next first operation. This is because if the data of the block of the processing unit is written, correct reading cannot be performed.

In FIG. 8, the line buffer 16
Line buffers 2a and 2b (reference numerals 16a and 16b)
And a multiplexer 16c. The input of each of the line buffers 16a and 16b is connected to the output terminal of the bit array 15, and the output is connected to the multiplexer 16c. The multiplexer 16c has a BUF
Based on the SEL signal, two line buffers 16a,
The operation of selecting one of the outputs 16b and transferring it to the video output unit is performed. The data output from the bit array 15 is written into one of the line buffers (16a or 16b) by the line buffer control circuit 17.

FIG. 10 is a timing chart of control signals related to the line buffer control circuit 17 of the present invention. The WRITE READY signal is initially "1".
(= Writable) and the input ready signal of the line buffer selected by the BWSEL signal which is one of the internal signals of the line buffer control circuit (the internal signal IRDYA or IRDY of the line buffer control circuit).
Asserted only when B) is "1".

When the WRITE READY signal is asserted, it indicates that data of 32 words can be written into the bit array 15 by the processor, and if this writing is performed even once, it is negated. (The WRITE READY signal becomes “0”.) Then, after all of the 32 words of data written in the bit array 15 are read out to the line buffer 16, the signal is asserted again. Writing of data from the bit array 15 to the line buffer is performed by the line buffer control circuit 17.
Is controlled by an RR (READ READY) signal which is an internal signal of

The line buffer is selected by asserting one of the * READa and * READb signals for reading and the * WRITEa and * WRITEb signals for writing. That is, when the RR signal is asserted, data is read from the bit array and the read data is written to the currently selected line buffer (for example, reference numeral 16a).

In the second embodiment, assuming that the number of words in the line direction (that is, the short side direction) of the line buffer is 256, the line buffer corresponding to address A to address A + 31x / 32 in FIG. The write address of the data to each is hexadecimal,
"0", "100", ... "1F00".

The read signal READ and the write signal * WRITEa output from the line buffer control circuit 17 are pulse signals that change at the same timing. Here, the * WRITEa signal is a negative logic signal (“0” is true)
It is.

The timing of writing the data read from the bit array to the line buffer is controlled by the * WRITEa signal. With one READ pulse, the bit array is shifted by one in the minus direction of the X coordinate, and
With one * WRITEa pulse, the upper byte of the write address of the line buffer is incremented by one. This is repeated for 32 words, and 32 words from the bit array are read.
Upon completion of the reading of the word, that is, completion of writing of the 32nd word to the line buffer, RR is negated, and WRITE READY is asserted again.

The write address of the line buffer is such that the lower byte is incremented by 1 and the upper byte is reset to 0 to prepare for writing to the next 32 words of the line buffer. The assertion of WRITE READY causes the processor to write the next block of the first processing unit to the bit array, and then read from the bit array and write to the line buffer. Such processing is repeatedly performed, and the rotation processing (portrait-landscape conversion) of the block 2 as the second processing unit is performed.

After writing the last word (address n) of the second processing unit into the bit array, the processor asserts the TC signal. This is for notifying the line buffer control circuit 17 that the second processing unit is the last in writing the word.

The block 32 in which the TC signal was asserted
After the data reading of the word is completed, the following signal transition is performed in the line buffer control circuit. BWSEL: “0” → “1” This means that the storage line buffer for the read data of the bit array is switched from 2a to 2b. IRDYA: “1” → “0” ORDYA: “0” → “1” This means that the line buffer 2a is switched from the write mode to the read mode.

As a result, the line buffer for storing the read data of the bit array becomes 2b, and the data of the next second processing unit is sequentially stored in the bit array 15 by the same processing as that of the line buffer 2a. The data is written, converted, and stored in the line buffer 2b.

On the other hand, the line buffer 2a switched to the read mode operates as follows. BUFSEL = 1 is set by the assertion of the line synchronization signal BD from the print engine after the assertion of ORDYA, and the multiplexer 16c selects the output of the line buffer 2a. From the video output unit, a data request signal DREQ is sent to the video buffer control circuit 17. The DREQ signal is asserted every time 32 serial data is sent to the print engine after the assertion of the BD, and is negated by the response signal * DACK.

When the TCA indicating the transmission of the last word of the line to the video output unit is asserted together with * DACK, DREQ is started until the next line is started, that is, until a new BD signal is asserted. Is not asserted.

In response to the data request DREQ from the video output unit, first, the data of the first line is read from the address “0” sequentially in increments. * DACK, which is a pulse signal that changes at the same timing as the read signal * READa, is output to the video output unit as a DREQ response signal, and data selected and output from the multiplexer 16c is written to the video output unit.

As in the first embodiment, the video output unit performs parallel-serial data conversion and sends the video data to the print engine. The number of transmissions to the video output unit is equal to the lower byte value of the address value when the last data of the block of the first processing unit for which TC is asserted is stored in the line buffer. This value is held in the line buffer control circuit, and when the number of words to be transmitted to the video output unit becomes equal to this value, TCA is asserted to terminate data transmission to the video output unit.

The transmission of the data of the second line is started by the assertion of the next BD. As for the start address, the upper byte is incremented by "1" and the lower byte is reset by the assertion of the BD signal to "100" (16
The transmission is restarted from the data of the address (hex). Such an operation is performed over 32 lines.

After the last word of the 32nd line is output to the video output unit, the following signal transition is performed in the line buffer control circuit. IRDYA: “0” → “1” ORDYA: “1” → “0” This means that the line buffer 2a is switched from the read mode to the write mode.

The time for storing the data obtained by converting the bitmap data into the landscape is 32 lines.
It is much faster than the video transmission time for the line. Therefore, the BWSEL for selecting the storage destination of the read data of the bit array has already been switched to the line buffer 2a side by the completion of the conversion data storage in the other line buffer 2b (see the timing of Time-B in FIG. 10).

However, at this timing, the input ready signal IRDYA of the line buffer is "0". Therefore, since IRDYA = "0", the WRITE READY signal to the processor is not asserted, remains negated, and the writing of data in the bit array is prohibited.

When all the data in the line buffer 2a is output to the video output unit, IRDYA = 1, and W
RITE READY is also asserted, and the conversion process of the block of the new second processing unit can be executed (see the timing of Time-C in FIG. 10).

By executing such an operation over one page, it is possible to rotate the bitmap data developed in the portrait direction in the landscape direction and send it to the video output unit.

According to the second embodiment, since the line buffer control circuit 17 is provided, the following three data transfer processes among the five data transfer processes performed by the processor described in the first embodiment are unnecessary. Becomes (1) Read processing from the bit array by the processor (2) Write processing to the line buffer by the processor (3) Write processing from the line buffer to the video output unit by the processor

At this time, the total processing time required for the rotation processing until writing to the video output unit is (180 ns × (704)
0/4) × 2) × 2 = 1.267 ms, so that the rotation processing time can be reduced as compared with the first embodiment (3.168 ms).

FIG. 11 and FIG. 12 are explanatory diagrams of the processing for expanding the data into the line buffer according to the third embodiment of the present invention. This indicates a process in a case where the developing direction of the data developed into the bitmap matches the paper transport direction. The bit array 15 and the line buffer 16 are shown in FIGS.
The MTX (X, 3) shown in FIG.
The data is transferred from the bit array 15 to the line buffer 16 via the path 1), and further output to the video output unit.

In the case of FIG. 11, there is no need to perform the rotation process as shown in FIG. 4, and therefore, as shown in FIG. 11A, the addresses n, n + m,...
The bitmap data may be read out and written to the bit array 15. That is, when the data of 32 words of the block 1 of FIG. 11A is written into the bit array, the state of FIG. 11B and FIG.
It becomes like 1 (d).

The data written in the bit array is not converted (rotated) as it is,
Is transferred to the line buffer as shown in FIG. At this time,
The read direction control signal UNROT shown in FIG.
, The data output from the path MTX (X, 31) is selected by the multiplexer 15c and transferred to the line buffer.

Address n in the uppermost row shown in FIG.
Is stored in the upper left position of the line buffer, then the data at the address n + m shown in FIG. 11C is stored in the second line which is one line below, and the data at the address n + 31m is stored in the line buffer. Is stored at the lower left position. Further, the processing order for each block is different from that in FIG. 2, and as shown in FIG. The details of the processing by the line buffer control circuit 17, that is, the writing processing to the line buffer and the reading processing from the line buffer to the video output unit may be performed in the same manner as in the second embodiment. The image data processing apparatus according to the present invention can be incorporated in a printing apparatus as in the above-described embodiment, and can be used in various image processing apparatuses that require bitmap development and rotation processing.

[0102]

According to the present invention, even if the developing direction of the bitmap-developed image data is different from the conveying direction of the sheet, the image data can be rotated without increasing the memory capacity, and the processor can be used. It is possible to provide an image data processing apparatus capable of performing a rotation process of image data without reducing a load and reducing a printing speed.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a first embodiment of an image data processing device of the present invention.

FIG. 2 is an explanatory diagram of storage contents of an embodiment of a bit map memory according to the present invention.

FIG. 3 is a configuration diagram of one embodiment of a line buffer according to the present invention;

FIG. 4 is an explanatory diagram of a process of reading data from a bit array according to the present invention.

FIG. 5 is a configuration diagram of a bit array according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a timing of a read / write operation of the bit array of the present invention.

FIG. 7 is a configuration block diagram of a second embodiment of the image data processing device of the present invention.

FIG. 8 is a configuration diagram of one embodiment of a line buffer and a line buffer control circuit of the present invention.

FIG. 9 is a configuration diagram of a bit array according to a second embodiment of the present invention.

FIG. 10 is a time chart of control signals related to the line buffer control circuit of the present invention.

FIG. 11 is an explanatory diagram of a process of expanding a line buffer in a third embodiment of the present invention.

FIG. 12 is an explanatory diagram of expansion processing to a line buffer in a third embodiment of the present invention.

FIG. 13 is an explanatory diagram of a sheet conveying direction of the printing apparatus.

[Explanation of symbols]

 Reference Signs List 1 image data processing device 2 processor 3 ROM 4 RAM 5 bitmap memory 6 peripheral I / F 7 font ROM 8 video output unit 9 printer I / F 10 processor bus 11 host 12 printer engine 13 bit array 13a line buffer basic configuration 1 13b Line buffer basic configuration 2 14 Line buffer 15 Bit array 15a Line buffer basic configuration 1 15b Line buffer basic configuration 2 15c Multiplexer 16 Line buffer 16a Line buffer 2a 16b Line buffer 2b 16c Multiplexer 17 Line buffer control circuit

Claims (6)

[Claims] 1. A page memory for storing bitmap-deployed image data in page units, and a bit for reading and storing image data present in a predetermined block of the page memory in a bit array arranged in a predetermined line direction. An array memory, rotation processing control means for extracting image data for each line in a direction different from the bit array direction with respect to the image data stored in the bit array memory,
Image data processing comprising: a line buffer memory for storing image data taken out by a rotation processing control means in a predetermined order; and image data output means for sequentially reading the image data stored in the line buffer memory. apparatus. 2. The image processing apparatus according to claim 1, wherein the line buffer includes two line buffers. When one of the line buffers is used to store image data extracted by the rotation processing control unit, the other line buffer is used. 2. The image data processing apparatus according to claim 1, wherein the first line buffer is used for reading by the image data output unit, and the two line buffers are used exclusively cyclically. 3. The image data processing apparatus according to claim 2, further comprising a line buffer switching unit for cyclically using said two line buffers. 4. The image data processing apparatus according to claim 3, wherein each of the plurality of bit arrays stored in the bit array memory has a unit word length. 5. When the image data stored in the page memory is data expanded in a portrait direction, the block is constituted by a predetermined number of bit arrays on a line arranged in the portrait direction, 5. The image data retrieved by the rotation processing control means from the bit array memory is a second bit arrangement on a line arranged in a direction perpendicular to the portrait direction. An image data processing apparatus as described in the above. 6. An image data processing apparatus according to claim 1, further comprising a paper transport unit, wherein a developing direction of the image data stored in the page memory and a transport direction of the paper set in the paper transport unit. Wherein the rotation processing control means extracts the image data for each line in a direction different from the direction of the bit array of the image data stored in the bit array memory.